Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes an interposer, at least one semiconductor integrated circuit die mounted over a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molded portion contacting the second surface of the interposer and laterally surrounding the package substrate. The package substrate may be laterally constrained relative to the interposer such that at least one horizontal dimension of the package substrate may be less than a corresponding horizontal dimension of the interposer. In various embodiments, reliability of bond connections between the interposer and the package substrate may be provided, thereby providing increased yield and improved package performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor package, and more particularly to a semiconductor package in which a packaging substrate is laterally-confined with respect to an interposer. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications. Some example uses can include personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon. Typically, dozens or hundreds of integrated circuits are fabricated on a single semiconductor wafer, and the individual die on the wafer are separated by sawing along scribe lines between the integrated circuits. Each die is typically individually packaged, e.g., in a multi-chip module or in other types of packages.

[0003] As semiconductor packages become increasingly complex, it becomes more difficult to ensure the mechanical integrity of the package, including the electrical interconnections between the various components of the package. Summary of the Utility Model

[0004] Some embodiments of the present disclosure provide a semiconductor package. The semiconductor package includes: an interposer; at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer; a packaging substrate bonded to a second surface of the interposer; and a molding portion contacting the second surface of the interposer and laterally surrounding the packaging substrate.

[0005] In some embodiments, the packaging substrate includes a packaging substrate width dimension that is less than a corresponding interposer width dimension of the interposer.

[0006] In some embodiments, a plurality of semiconductor integrated circuit dies are mounted on the first surface of the interposer, and the molding portion includes a second molding portion, wherein the semiconductor package further includes: a plurality of first bonding structures bonding the plurality of semiconductor integrated circuit dies to the first surface of the interposer; an underfill material portion located between the plurality of semiconductor integrated circuit dies and the first surface of the interposer and laterally surrounding the plurality of first bonding structures; a first molding portion laterally surrounding the plurality of semiconductor integrated circuit dies; and a plurality of second bonding structures bonding the packaging substrate to the second surface of the interposer, wherein the second molding portion extends at least partially within a space between the packaging substrate and the second surface of the interposer.

[0007] In some embodiments, multiple side surfaces of the semiconductor package are formed by the first molding part, the interposer, and the second molding part.

[0008] In some embodiments, the semiconductor package further includes at least one of an annular structure and a lid structure mounted on an upper surface of the first molding part.

[0009] In some embodiments, the lid structure is mounted on the upper surface of the first molding part and extends over the plurality of semiconductor integrated circuit dies, and a thermal interface material is located between the upper surface of the plurality of semiconductor integrated circuit dies and the lid structure.

[0010] In some embodiments, the semiconductor package further includes a functional component bonded to the second surface of the interposer, wherein at least a portion of the functional component is located between the second surface of the interposer and the package substrate.

[0011] Some embodiments of the present disclosure provide a semiconductor package. The semiconductor package includes: an interposer; at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer; a plurality of package substrates bonded to a second surface of the interposer; and a molding part in contact with the second surface of the interposer and located in a gap between adjacent ones of the package substrates.

[0012] In some embodiments, the molding part laterally surrounds each of the plurality of package substrates, and a thickness of the molding part between an outer periphery of the plurality of package substrates and a periphery of the interposer is at least 40 μm.

[0013] In some embodiments, the semiconductor package further includes a functional component mounted on the second surface of the interposer, wherein the molding part laterally surrounds the functional component and extends within a gap between the functional component and one of the plurality of package substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The concepts of the embodiments of the present disclosure can be better understood according to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clear illustration.

[0015] Figure 1 is a vertical cross-sectional view of an intermediate structure during the process of forming a semiconductor package according to various embodiments of the present disclosure, the intermediate structure including an interposer located on a first carrier substrate.

[0016] Figure 2is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a plurality of semiconductor integrated circuit (IC) dies mounted on a first side surface of an interposer.

[0017] Figure 3 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing an underfill material portion located between a lower surface of a semiconductor IC die and a first side surface of an interposer.

[0018] Figure 4 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a first molding portion laterally surrounding the underfill material portion and the semiconductor IC die.

[0019] Figure 5 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a second release layer located above upper surfaces of a plurality of semiconductor IC dies, an exposed upper surface of the underfill material portion, and an exposed upper surface of the first molding portion, and a second carrier substrate located above the second release layer.

[0020] Figure 6 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing an exemplary intermediate structure that is inverted (i.e., flipped) such that the interposer and the plurality of semiconductor IC dies are located above and supported by the second carrier substrate.

[0021] Figure 7A is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a package substrate located above a second side surface of the interposer.

[0022] Figure 7B is according to various embodiments of the present disclosure Figure 7A a horizontal plan bottom up view of an intermediate structure, showing a package substrate located above a second side surface of the interposer.

[0023] Figure 8 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a second molding portion that contacts the second side surface of the interposer and laterally surrounds the package substrate.

[0024] Figure 9 is a vertical cross-sectional view of a semiconductor package according to various embodiments of the present disclosure.

[0025] Figure 10A vertical cross - sectional view of a semiconductor package according to various embodiments of the present disclosure, the semiconductor package including a plurality of solder balls located on a lower surface of a package substrate and a ring structure mounted to an upper surface of a first molding portion.

[0026] Figure 11 A vertical cross - sectional view of a semiconductor package mounted to a support substrate according to various embodiments of the present disclosure.

[0027] Figure 12 A vertical cross - sectional view of a semiconductor package according to another embodiment of the present disclosure, the semiconductor package including a plurality of solder balls located on a lower surface of a package substrate, a thermal interface material (TIM) located above a plurality of semiconductor IC dies, and a lid structure mounted to an upper surface of a first molding portion.

[0028] Figure 13 A vertical cross - sectional view of an intermediate structure according to various embodiments of the present disclosure, the intermediate structure including functional components mounted above a second side surface of an interposer.

[0029] Figure 14 A vertical cross - sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a plurality of package substrates located above a second side surface of an interposer and functional components.

[0030] Figure 15 A vertical cross - sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a second molding portion that contacts a second side surface of an interposer and laterally surrounds each package substrate.

[0031] Figure 16 A vertical cross - sectional view of a semiconductor package according to various embodiments of the present disclosure.

[0032] Figure 17 A vertical cross - sectional view of a semiconductor package according to various embodiments of the present disclosure, the semiconductor package including a plurality of solder balls located on a lower surface of a package substrate and a ring structure mounted to an upper surface of a first molding portion.

[0033] Figure 18 A flowchart showing a method of manufacturing a semiconductor package according to various embodiments of the present disclosure.

[0034] Wherein, the reference numerals are explained as follows:

[0035] 101: First carrier substrate

[0036] 103: Interposer

[0037] 104: Dielectric material

[0038] 105: Conductive interconnect structure

[0039] 106: (First) bonding structure

[0040] 107: Semiconductor integrated circuit die / semiconductor IC die

[0041] 108: Underfill material portion

[0042] 109: First molding portion

[0043] 110: (Second) carrier substrate

[0044] 111: Package substrate

[0045] 112: Substrate core

[0046] 113: Redistribution structure

[0047] 114: Conductive interconnect feature

[0048] 115: Dielectric material matrix / dielectric material

[0049] 116: Conductive interconnect feature

[0050] 117: Bonding material portion

[0051] 118: (Second) molding portion

[0052] 119: Ring structure

[0053] 120: Dicing tape

[0054] 121: Tape frame

[0055] 122: Solder ball / (Second) bonding structure / solder portion

[0056] 123: Support substrate

[0057] 124: Underfill material portion

[0058] 125: Thermal interface material

[0059] 126: Cover structure

[0060] 130: Functional component

[0061] 131: Bonding structure

[0062] 133: Gap

[0063] 137: First release layer

[0064] 138: Second release layer

[0065] 141: First side surface / first surface

[0066] 142: Second side surface / Second surface

[0067] 143: First side surface

[0068] 144: Bonding pad

[0069] 145: Bonding pad

[0070] 152: Bonding pad

[0071] 200: Method

[0072] 201, 203, 205: Steps

[0073] d: Thickness

[0074] hd1, hd2: Horizontal direction

[0075] UA: Unit area

[0076] W int : Interposer width

[0077] W sub : Package substrate width Detailed implementation manners

[0078] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations described.

[0079] Furthermore, spatially relative terms such as "below", "beneath", "lower", "above", "upper" and the like may be used herein for ease of description to describe the relationship between one element or feature shown in the drawings and another (or some) element or feature. In addition to the orientation shown in the drawings, these spatially relative terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted accordingly. Unless otherwise clearly stated, each element having the same reference symbol is assumed to have the same material composition and a thickness within the same thickness range.

[0080] Various embodiments disclosed herein relate to semiconductor devices, and more particularly to semiconductor packages and methods of manufacturing semiconductor packages. The semiconductor package includes an interposer, at least one semiconductor integrated circuit (IC) die mounted on a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molding portion that contacts the second surface of the interposer and laterally surrounds the package substrate. In various embodiments, the package substrate of the semiconductor package may be laterally-confined relative to the interposer such that at least one horizontal dimension of the package substrate is less than a corresponding horizontal dimension of the interposer.

[0081] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) dies (i.e., "wafers") may be mounted to a common substrate, which may also be referred to as a "package substrate". In some semiconductor packages, such as in a fan out wafer level package (FOWLP) and / or a fan-out panel level package (FOPLP), multiple semiconductor IC dies may be mounted to an interposer, such as an organic interposer or a semiconductor (e.g., silicon) interposer, which may include interconnect structures extending therethrough. The resulting package structure (including the interposer and the semiconductor IC dies mounted thereon) may then be mounted to the surface of a package substrate using solder connections.

[0082] Many semiconductor packages can include a large number of semiconductor IC dies integrated within the semiconductor package. For example, a semiconductor package for high-performance computing (HPC) applications can include a large number of different types of semiconductor IC dies (e.g., processor dies, memory dies, wafers, etc.) integrated into a single package. To accommodate a relatively large number of semiconductor IC dies within the semiconductor package, the interposer and the package substrate of the semiconductor package may require a relatively large area. However, an interposer and a package substrate having a large area may result in mechanical instability of the package substrate. For example, when bonding the interposer and the semiconductor IC dies mounted thereon to the package substrate, it may be difficult to maintain coplanarity tolerances. The relatively large-sized interposer and package substrate may also be prone to crack defects and poor signal integrity (SI) and / or power integrity (PI) characteristics. Thus, relatively large-sized semiconductor packages may result in a greater risk of defective bonding, poor performance, and / or lower yield.

[0083] To improve the performance and yield of semiconductor packages, various embodiments disclosed herein include a semiconductor package and a method of manufacturing a semiconductor package. The semiconductor package includes an interposer, at least one semiconductor integrated circuit die mounted on a first surface of the interposer, a package substrate bonded to a second surface of the interposer, and a molding portion that contacts the second surface of the interposer and laterally surrounds the package substrate. In various embodiments, the package substrate may be laterally-confined relative to the interposer such that at least one horizontal dimension of the package substrate is less than a corresponding horizontal dimension of the interposer.

[0084] In various embodiments, one or more laterally constrained package substrates can be mounted to a second surface of an interposer, while the interposer and the semiconductor IC die are supported on a carrier substrate. In some embodiments, by bonding the package substrate to a package structure including the interposer and the semiconductor IC die, while the package structure is supported on the carrier substrate, additional mechanical support can be provided and thermally induced warpage during the bonding process can be suppressed. This can help improve the coplanarity characteristics of the bonding structure (e.g., solder balls) that bond the package substrate to the interposer. Then, a molding portion (e.g., an epoxy mold compound (EMC)) can be formed over the second surface of the interposer and laterally around each package substrate to provide enhanced structural integrity to the semiconductor package. Accordingly, the bonding connections between the interposer and the package substrate can have increased reliability, thereby providing increased yield and improved package performance within a compact package size. Various embodiments can also enable the use of a relatively thick interposer and / or a relatively thin package substrate, including a "coreless" package substrate, which can help improve the signal integrity (SI) and / or power integrity (PI) characteristics of the semiconductor package.

[0085] Figure 1 is a vertical cross-sectional view of an intermediate structure during the process of forming a semiconductor package according to various embodiments of the present disclosure. Refer to Figure 1 , the intermediate structure includes a first carrier substrate 101 and an interposer 103 formed and mounted over a front-side surface of the first carrier substrate 101. The first carrier substrate 101 can provide mechanical support for the interposer 103. The first carrier substrate 101 can be formed of a suitable substrate material, such as a glass material, a ceramic material (e.g., a sapphire substrate), a semiconductor material (e.g., a silicon substrate), etc. Other suitable materials for the first carrier substrate 101 are within the scope of the present disclosure. In some embodiments, the first carrier substrate 101 can be formed of an optically transparent material.

[0086] In some embodiments, the first release layer 137 may be located over the front-side surface of the first carrier substrate 101, and the interposer layer 103 may be located over the first release layer 137. The first release layer 137 may include an adhesive material that can adhere the interposer layer 103 to the front-side surface of the first carrier substrate 101. In some embodiments, the first release layer 137 may include an adhesive material that can be subsequently processed to cause the adhesive material of the first release layer 137 to lose its adhesive properties, such that the first carrier substrate 101 can be separated from the interposer layer 103. In some embodiments, when processed using an energy source (e.g., thermal, light (e.g., UV, laser, etc.), and / or acoustic (e.g., ultrasonic) energy sources), the adhesive material of the first release layer 137 can lose its adhesive properties. In one non-limiting example, the first release layer 137 may include a light-to-heat conversion (LTHC) material that can selectively absorb light radiation (e.g., ultraviolet radiation) within certain wavelength ranges, causing the LTHC material to heat up and lose its adhesion. In other embodiments where the first carrier substrate 101 is formed of an optically transparent material, applying a light energy source may cause the first release layer 137 to lose its adhesive properties. Alternatively, the first release layer 137 may include an adhesive material, such as an acrylic pressure-sensitive adhesive material, that can decompose when subjected to high temperatures. Other suitable materials for the first release layer 137 are within the scope of this disclosure.

[0087] Referring again to Figure 1 , the interposer layer 103 may include a first side surface 141 and a second side surface 142 opposite the first side surface. The second side surface 142 of the interposer layer 103 may face the front-side surface of the first carrier substrate 101. A plurality of conductive interconnect structures 105 (e.g., metal lines and vias) may extend within the interposer layer 103 between the first side surface 141 and the second side surface 142 of the interposer layer 103. The conductive interconnect structures 105 may be formed in and surrounded by an insulating matrix, which may be composed of a dielectric material 104. The conductive interconnect structures 105 of the interposer layer 103 may be configured to route electrical signals between semiconductor integrated circuit (IC) dies and a package substrate in a subsequently formed semiconductor package. Accordingly, the conductive interconnect structures 105 of the interposer layer 103 may also be referred to as "redistribution structures".

[0088] In some embodiments, the interposer layer 103 can be an organic interposer layer. The organic interposer layer 103 can be formed on the first carrier substrate 101. In a non-limiting example, the interposer layer 103 can be formed by sequentially depositing multiple dielectric materials 104 (e.g., dielectric polymer materials) over the front-side surface of the first carrier substrate 101 (and over the first release layer 137, in embodiments including the first release layer 137). Each layer of the multiple dielectric materials 104 can be lithographically patterned and etched to form opening regions (e.g., trenches and / or via openings), and then the opening regions can be filled using a metallization process to form conductive interconnect structures 105 (e.g., metal lines and vias) within each successive layer of the dielectric material 104. In this way, the interposer layer 103 can be constructed layer by layer over the front-side surface of the first carrier substrate 101. Each layer of the dielectric material 104 and the corresponding conductive interconnect structure 105 of the interposer layer 103 can be referred to as a redistribution layer (RDL). In some embodiments, the interposer layer 103 can include at least two (2) redistribution layers (RDLs). In some embodiments, the interposer layer 103 can have a thickness between the first side surface 141 and the second side surface 142 of the interposer layer 103 that is at least 40 μm, e.g., between about 40 μm and about 80 μm. It should be understood that larger or smaller thicknesses of the interposer layer 103 can also be used.

[0089] In some embodiments, each layer of the dielectric material 104 of the interposer layer 103 can include a suitable dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of this disclosure. The multiple dielectric materials 104 of the interposer layer 103 can be formed using suitable deposition processes, such as spin coating and drying processes. Other suitable deposition processes are also within the scope of this disclosure.

[0090] The conductive interconnect structure 105 of the interposer layer 103 can be formed of a suitable conductive material, such as Cu, Ni, W, Co, Mo, Ru, etc., including alloys and combinations thereof. In some embodiments, the conductive interconnect structure 105 can include a metal barrier layer (e.g., a Ti, TiN, TaN, or WN layer) that contacts the dielectric material 104 and a metal fill layer (which can include elemental metals (e.g., Cu, Ni, etc.), alloys, or combinations thereof). Other suitable materials for the conductive interconnect structure 105 of the interposer layer 103 are within the scope of this disclosure. The conductive interconnect structure 105 of the interposer layer 103 can be formed using any suitable deposition process. By way of example, suitable deposition processes can include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof.

[0091] Referring again to Figure 1 , an instance of the interposer layer 103 located above the front surface of the first carrier substrate 101 can be referred to as a unit area (UA) of the first carrier substrate 101. The interposer layer 103 can have an interposer width W int . Figure 1 A single unit area (UA) is shown in

[0092] Figure 2A vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a plurality of semiconductor integrated circuit (IC) dies 107 mounted on a first side surface 141 of the interposer 103. Refer to Figure 2 , in some embodiments, the plurality of semiconductor IC dies 107 may include at least one processor die, such as a system-on-chip (SoC) die, an application specific integrated circuit (ASIC) die, a central processing unit die, and / or a graphics processing unit die. In some embodiments, the plurality of semiconductor IC dies 107 may include at least one chiplet configured to perform specific, limited processing functions. In some embodiments, the plurality of semiconductor IC dies 107 may include at least one memory die, such as a high bandwidth memory (HBM) die and / or a dynamic random access memory (DRAM) die. In some embodiments, the plurality of semiconductor IC dies 107 may be homogeneous, meaning that all semiconductor IC dies 107 may be of the same type (e.g., all are SoC dies, all are HBM dies, all are DRAM dies, etc.). Alternatively, the plurality of semiconductor IC dies 107 may be heterogeneous, meaning that the plurality of semiconductor IC dies 107 may include different types of semiconductor IC dies 107 (e.g., at least one processor die and at least one memory die). Although Figure 2 the embodiment of

[0093] Refer again to Figure 2, a plurality of bonding structures 106 may bond each semiconductor IC die 107 to the first side surface 141 of the interposer 103. In various embodiments, each semiconductor IC die 107 may be mounted on the first side surface 141 of the interposer 103 by placing each semiconductor IC die 107 on top of the first side surface 141 of the interposer 103 (e.g., using a pick-and-place device). The semiconductor IC die 107 may be aligned on the first side surface 141 of the interposer 103 such that semiconductor die bonding structures (e.g., metal bumps, pillars, stacks, and / or pads) on the bottom surface of the semiconductor IC die 107 contact corresponding interposer bonding structures (e.g., metal bumps, pillars, stacks, and / or pads) on the first side surface 141 of the interposer 103. A reflow process may be used to bond the semiconductor die bonding structures on the bottom surface of the semiconductor IC die 107 to the corresponding interposer bonding structures on the first side surface 141 of the interposer 103, thereby providing a mechanical and electrical connection between each semiconductor IC die 107 and the interposer 103. In some embodiments, the semiconductor IC die 107 may be bonded to the first side surface 141 of the interposer 103 using microbump bonding (i.e., C2 bonding), although it should be understood that other bonding techniques and processes are also within the scope of the present disclosure. In various embodiments, a plurality of semiconductor IC dies 107 may be mounted on the first side surface 141 of the interposer 103 within each unit area (UA) of the first carrier substrate 101.

[0094] Figure 3 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a portion of underfill material 108 located between the bottom surface of the semiconductor IC die 107 and the first side surface 141 of the interposer 103. Refer to Figure 3 , the underfill material portion 108 may be applied to the space between the first side surface 141 of the interposer 103 and the plurality of semiconductor IC dies 107 mounted to the interposer 103. The underfill material portion 108 may laterally surround and contact each bonding structure 106 that bonds an individual semiconductor IC die 107 to the interposer 103. The underfill material portion 108 may also be located between adjacent semiconductor IC dies 107 among the plurality of semiconductor IC dies 107 mounted to the interposer 103.

[0095] The underfill material portion 108 may include any underfill material known in the art. For example, the underfill material portion 108 may be composed of an epoxy-based material, which may include a composite of a resin and a filler material. Other suitable materials for the underfill material portion 108 are within the scope of the present disclosure. Any known underfill material application method may be used to apply the underfill material portion 108.

[0096] Figure 4 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a first molding portion 109 that laterally surrounds the underfill material portion 108 and the semiconductor IC die 107. Refer to Figure 4 , the first molding portion 109 may laterally surround a plurality of semiconductor IC dies 107 mounted to the interposer 103. The first molding portion 109 may contact at least some of the lateral side surfaces of the semiconductor IC dies 107 and may also contact the underfill material portion 108. In various embodiments, the first molding portion 109 may include an epoxy resin material. For example, the first molding portion 109 may include an epoxy molding compound (EMC), which may include an epoxy resin, a hardener (i.e., a curing agent), silica or other filler materials, and optional additional additives. The EMC may be applied in a liquid or solid form around the periphery of the semiconductor IC die 107 and may be hardened (i.e., cured) to form the first molding portion 109 having sufficient rigidity and mechanical strength around the plurality of semiconductor IC dies 107. The portion of the first molding portion 109 that extends above the horizontal plane including the top surface of the semiconductor IC die 107 may be removed using a planarization process such as a chemical mechanical planarization (CMP) process.

[0097] In various embodiments, each unit area (UA) of the first carrier substrate 101 may include an underfill material portion 108 located between the first side surface 141 of the interposer 103 and the lower side of the plurality of semiconductor IC dies 107 mounted to the interposer 103, and a first molding portion 109 that surrounds the outer periphery of the plurality of semiconductor IC dies 107. In some embodiments, the first molding portion 109 may form a continuous matrix extending between the plurality of unit areas (UAs) of the first carrier substrate 101 and laterally surround and embed groups of semiconductor IC dies 107 within each unit area (UA) of the first carrier substrate 101.

[0098] Figure 5 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a second release layer 138 located above the upper surface of the plurality of semiconductor IC dies 107, the exposed upper surface of the underfill material portion 108, and the exposed upper surface of the first molding portion 109, and a second carrier substrate 110 located above the second release layer 138. Refer to Figure 5, the second release layer 138 may include an adhesive material that can adhere the second carrier substrate 110 to the upper surfaces of the plurality of semiconductor IC dies 107, the underfill material portion 108, and the first molding portion 109. Similar to the above-described first release layer 137, the second release layer 138 may also be configured to lose its adhesive properties when processed using an energy source (e.g., heat, light (e.g., UV, laser, etc.), and / or acoustic (e.g., ultrasonic) energy source). In some embodiments, the first release layer 137 and the second release layer 138 may be composed of the same material. Alternatively, the first release layer 137 and the second release layer 138 may be composed of different materials.

[0099] Referring again to Figure 5 , the second carrier substrate 110 may be formed of a suitable substrate material, such as the materials described above with reference to Figure 1 the first carrier substrate 101 shown. In some embodiments, the second carrier substrate 110 may be composed of the same material as the first carrier substrate 101. Alternatively, the second carrier substrate 110 and the first carrier substrate 101 may be composed of different materials. In various embodiments, the second carrier substrate 110 may extend over each unit area (UA) of the first carrier substrate 101 such that each unit area (UA) of the first carrier substrate 101 may correspond to an equivalent unit area (UA) of the second carrier substrate 110.

[0100] Figure 5 The removal of the first carrier substrate 101 from the intermediate structure is also shown. Any suitable method known in the art may be used to remove the first carrier substrate 101. In embodiments where the first carrier substrate 101 is adhered to the interposer 103 via the first release layer 137, the first release layer 137 may be subjected to a process that causes the first release layer 137 to lose its adhesive properties. This may enable the first carrier substrate 101 to be separated from the exemplary intermediate structure. For example, the first release layer 137 may include a light-to-heat conversion (LTHC) material that can be irradiated with light radiation (e.g., ultraviolet radiation) within a specific wavelength range, causing the LTHC material to heat up and lose its adhesive force. In embodiments where the first carrier substrate 101 is composed of an optically transparent material, the first release layer 137 may optionally be irradiated through the first carrier substrate 101. Alternatively, the first release layer 137 may include a thermally decomposable adhesive material. The exemplary intermediate structure is subjected to a thermal annealing process at a debonding temperature sufficient to cause the first release layer 137 to decompose, enabling the first carrier substrate 101 to be detached from the exemplary intermediate structure. In embodiments where the first carrier substrate 101 is removed using a thermal annealing process, the debonding temperature for thermally decomposing the first release layer 137 may not be sufficient to cause the second release layer 138 to lose its adhesive properties.

[0101] Figure 6 is a vertical cross-sectional view of an intermediate structure, showing an exemplary intermediate structure that has been inverted (i.e., flipped) such that the interposer layer 103 and the plurality of semiconductor IC dies 107 are located on and supported by the second carrier substrate 110. The intermediate structure may be inverted before or after removing the first carrier substrate 101.

[0102] Figure 7A is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, showing a package substrate 111 located above the second side surface 142 of the interposer layer 103. Figure 7B is Figure 7A a horizontal plan bottom up view of the intermediate structure of , showing a package substrate 111 located above the second side surface 142 of the interposer layer 103. In various embodiments, the package substrate 11 may include a dielectric material matrix 115 and have conductive interconnect features 114, 116 (e.g., metal lines, vias, bond pads, etc.) located in and extending through the dielectric material matrix 115. In some embodiments, the package substrate 11 may include a solid substrate core 112 and have conductive interconnect features 114 (e.g., vias) extending through the substrate core 112. In one exemplary embodiment, the substrate core 112 may be composed of laminated reinforced resin sheets. A redistribution structure 113 may be formed on the front and back surfaces of the substrate core 112. The redistribution structure 113 may include a polymer-based dielectric material layer, such as Ajinomoto Buildup Film (ABF) from Ajinomoto Co., Ltd. of Tokyo, Japan product and have conductive interconnect features 116 (e.g., metal lines, vias, and / or bond pads) formed on and / or within the dielectric material layer. An optional outer coating (e.g., solder mask) may be located on the redistribution structure 113. Other suitable materials and / or configurations for the package substrate 111 are within the scope of the present disclosure. In some embodiments, the package substrate 111 may be a "coreless" package substrate 111 without a substrate core 112, as described in further detail below. In some embodiments, the package substrate 111 may have a thickness of about 1.8 mm or less, e.g., between about 0.2 mm and about 1.8 mm. It should be understood that larger or smaller thicknesses of the package substrate 111 may also be used.

[0103] Referring again to Figure 7A and Figure 7B, the encapsulation substrate 111 can be bonded to the second side surface 142 of the interposer 103 via a plurality of bonding material portions 117 (e.g., solder joints). To bond the encapsulation substrate 111 to the interposer 103, the encapsulation substrate 111 can be aligned over the second side surface 142 of the interposer 103 such that the first side surface 143 of the encapsulation substrate 111 faces the second side surface 142 of the interposer 103. A plurality of bonding material portions 117 (e.g., solder balls) can be located between the bonding pads 144 on the first side surface 143 of the encapsulation substrate 111 and the corresponding bonding pads 145 on the second side surface 142 of the interposer 103. A reflow process can be performed to reflow the bonding material portions 117, thereby causing bonding between the encapsulation substrate 111 and the interposer 103. The reflow process can be performed at an elevated temperature, such as between 150°C and 350°C (e.g., about 250°C). After the reflow process, each bonding material portion 117 can be bonded to a corresponding one of the bonding pads 144 on the first side surface 143 of the encapsulation substrate 111 and a corresponding one of the bonding pads 145 on the second side surface 142 of the interposer 103. In some embodiments, the bonding material portions 117 can include C4 solder balls, and the encapsulation substrate 111 can be bonded to the interposer 103 via an array of C4 solder balls.

[0104] In various embodiments, as Figure 7A and Figure 7B shown, the encapsulation substrate 111 can be mounted over the interposer 103 within each unit area (UA) of the second carrier substrate 110. In each unit area (UA), each encapsulation substrate 111 can be laterally-confined relative to the underlying interposer 103. Specifically, each encapsulation substrate 111 can have dimensions along at least one horizontal direction (e.g., Figure 7A and Figure 7B hd1 and / or hd2 in sub that are less than the corresponding dimensions of the interposer 103 to which the encapsulation substrate 111 is bonded. Stated another way, along one or both of the horizontal directions hd1 and hd2, the width W int of the encapsulation substrate can be less than the width W sub of the interposer. In some embodiments, the dimensions of the encapsulation substrate 111 along two perpendicular horizontal directions can be less than the corresponding dimensions of the interposer 103 to which the encapsulation substrate 111 is bonded (i.e., the width W int)。In some embodiments, the horizontal cross-sectional area of each encapsulation substrate 111 may be smaller than the horizontal cross-sectional area of the interposer 103 to which the encapsulation substrate 111 is bonded. This may be contrasted with related semiconductor packages, where the encapsulation substrate may have a larger area than the interposer. As Figure 7B shown in the embodiment, the encapsulation substrate 111 may be smaller than the interposer 103 in two horizontal directions hd1 and hd2. The bonding pads 152 on the bottom of the encapsulation substrate 111 are shown in an array. In other embodiments, fewer or more bonding pads 152 may be provided.

[0105] The method of manufacturing a semiconductor package according to various embodiments of the present disclosure may also be different from the methods currently used to manufacture related semiconductor packages. For example, in the method of manufacturing a related package structure, a dicing process may be utilized to separate each unit area (UA) of an intermediate structure to provide a plurality of discrete package structures, where each package structure includes an interposer 103, a plurality of semiconductor IC chips 107 mounted on a first side surface 141 of the interposer 103, a bottom fill material portion 108 located between the semiconductor IC chips 107 and the first side surface 141 of the interposer 103, and a first molding portion 109 laterally surrounding the plurality of semiconductor IC chips 107. Then, each package structure may be aligned over the surface of an encapsulation substrate and bonded to the surface of the encapsulation substrate via a plurality of bonding material portions 117 (e.g., solder connectors). The encapsulation substrate typically has a larger horizontal cross-sectional area than the horizontal cross-sectional area of the package structure. However, as described above, as the number of semiconductor IC chips 107 mounted on the interposer 103 increases and / or the size of the interposer 103 increases, it becomes increasingly difficult to maintain the coplanarity tolerance of the plurality of bonding material portions 117 (e.g., solder balls) when bonding the package structure to the encapsulation substrate 111. This may be at least partially attributed to the thermally induced warping of the package structure during the process of bonding the package structure to the encapsulation substrate. Therefore, the risk of defective bonding and other defects (e.g., crack formation) may increase, resulting in poor semiconductor package performance and / or reduced yield.

[0106] In various embodiments of the present disclosure, a laterally constrained package substrate 111 can be mounted to the second side surface 142 of the interposer 103 before singulation (e.g., dicing) of the respective unit areas (UAs) of the exemplary intermediate structure (i.e., when the interposer 103 and the semiconductor IC die 107 are supported on the second carrier substrate 110). This can help improve the coplanarity characteristics of the bonding material portion 117 (e.g., solder balls) of the bonding connection member formed between the package substrate 111 and the second side surface 142 of the interposer 103. In some embodiments, the coplanarity tolerance can be defined as the maximum allowable height difference between the surface of the bonding material portion 117 and a reference plane (i.e., the bottom drop plane). In various embodiments, as Figure 7A shown, during the bonding of the laterally constrained package substrate 111 to the second side surface 142 of the interposer 103, the coplanarity of the bonding material portion 117 can be less than 12 mils (i.e., 304.8 μm). This can result in an increase in the reliability of the bonding connection member between the interposer 103 and the package substrate 111, thereby providing increased yield and improved package performance within a compact package size.

[0107] In some embodiments, the package performance and the wiring density management can also be improved by using a relatively thick interposer 103 (e.g., ≥40 μm) and a relatively thin package substrate 111 (e.g., ≤1.8 mm). Accordingly, a relatively large portion of the redistribution structure and / or the redistribution layer can be provided in the interposer 103 rather than in the package substrate 111, which can help improve the signal integrity (SI) and / or power integrity (PI) characteristics of the semiconductor package.

[0108] Figure 8 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, showing a second molding portion 118 that contacts the second side surface 142 of the interposer 103 and laterally surrounds the package substrate 111. Referring to Figure 8 , the second molding portion 118 can contact the second side surface 142 of the interposer 103 and can extend at least partially within the gap between the second side surface 142 of the interposer 103 and the package substrate 111. In some embodiments, the second molding portion 118 can contact and can laterally surround some or all of the bonding material portions 117 that bond the package substrate 111 to the interposer 103. In some embodiments, for example, as referred to above Figure 3The described underfill material 108 may not be present between the package substrate 111 and the interposer 103. The second molding portion 118 may also laterally surround the package substrate 111. In some embodiments, the thickness d of the second molding portion 118 above the side surface of the package substrate 111 within each unit area (UA) may be at least 40 μm, such as between about 40 μm and about 2000 μm.

[0109] In various embodiments, the second molding portion 118 may comprise an epoxy resin material. For example, the second molding portion 118 may comprise an epoxy molding compound (EMC), which may comprise an epoxy resin, a hardener (i.e., a curing agent), silica or other filler materials, and optional additional additives. The EMC may be applied in liquid or solid form over the second side surface 142 of the interposer 103 and around the periphery of the package substrate 111 and may be hardened (i.e., cured) to form the second molding portion 118 having sufficient rigidity and mechanical strength around the package substrate 111. The portion of the second molding portion 118 that extends above the horizontal plane including the upper surface of the package substrate 111 may be removed using a planarization process such as a chemical mechanical planarization (CMP) process. Thus, the upper surface of the second molding portion 118 may be substantially coplanar with the upper surface of the package substrate 111. In some embodiments, the second molding portion 118 may comprise the same material as the first molding portion 109 described above with reference to Figure 4 Or, the second molding portion 118 may be composed of a material different from that of the first molding portion 109.

[0110] In various embodiments, each unit area (UA) of the second carrier substrate 110 may include the second molding portion 118 that laterally surrounds the package substrate 111. In some embodiments, the second molding portion 118 may form a continuous matrix extending between multiple unit areas (UAs) of the second carrier substrate 110 and laterally surround the package substrate 111 within each unit area (UA) of the second carrier substrate 110.

[0111] Figure 9 is a vertical cross-sectional view of the semiconductor package 100 according to various embodiments of the present disclosure. Referring to Figure 9 , the second carrier substrate 110 can be removed from the exemplary intermediate structure shown in Figure 8 . Any suitable method known in the art may be used to remove the second carrier substrate 110, such as any of the methods described above for removing the first carrier substrate 101. In embodiments where the second carrier substrate 110 is adhered to the semiconductor IC die 107, the underfill material portion 108, and the first molding portion 109 using the second release layer 138, the second release layer 138 may be subjected to a process that causes the second release layer 138 to lose its adhesive properties, such as that described above with reference to Figure 5The described thermal annealing and / or light irradiation treatment processes.

[0112] A dicing process can be used to separate each unit area (UA) of the exemplary intermediate structure to provide a plurality of discrete semiconductor packages 100. Each semiconductor package 100 can include an interposer 103, a plurality of semiconductor IC dies 107 mounted on a first side surface 141 of the interposer 103, a bottom fill material portion 108 located in a gap between the first side surface 141 of the interposer 103 and each semiconductor IC die 107, and a first molding portion 109 laterally surrounding the plurality of semiconductor IC dies 107. A second side surface 142 of the interposer 103 can be bonded to a package substrate 111 by a plurality of bonding material portions 117. The package substrate 111 can be laterally restricted relative to the interposer 103 such that at least one horizontal dimension of the interposer 103 can be greater than a corresponding horizontal dimension of the package substrate 111. A second molding portion 118 can contact the second side surface 142 of the interposer 103 and can laterally surround the package substrate 111. In some embodiments, a thickness d of the second molding portion 118 above a side surface of the package substrate 111 can be at least 40 μm, such as between about 40 μm and about 2000 μm. A side surface of the semiconductor package 100 can be formed by the first molding portion 109, the interposer 103, and the second molding portion 118.

[0113] Referring again to Figure 9 , the semiconductor package 100 can be disposed on a suitable support element, which can be a flexible support, such as a dicing tape 120 supported by a tape frame 121. The semiconductor package 100 can be inverted (i.e., flipped) relative to the Figure 8 orientation shown such that the interposer 103 and the plurality of semiconductor IC dies 107 can be located above the package substrate 111.

[0114] Figure 10 is a vertical cross-sectional view of a semiconductor package 100 according to various embodiments of the present disclosure, which includes a plurality of solder balls 122 located on a lower surface of the package substrate 111 and a ring structure 119 mounted to an upper surface of the first molding portion 109. Each solder ball 122 can contact a bonding pad exposed through the lower surface of the package substrate 111. The solder balls 122 can be used to mount the semiconductor package 100 to a support substrate including electrical interconnects, such as a printed circuit board (PCB). In some embodiments, the solder balls 122 can include a ball grid array (BGA), and the semiconductor package 100 can be mounted to the support substrate via BGA connectors.

[0115] Referring again to Figure 10, the ring structure 119 can be mounted to the upper surface of the first molded portion 109. The ring structure 119 can include a suitable structural material such as copper or stainless steel. The ring structure 119 can provide additional mechanical strength to the semiconductor package 100 and can help suppress warping.

[0116] Figure 11 is a vertical cross-sectional view of a semiconductor package 100 mounted to a support substrate 123 according to various embodiments of the present disclosure. Refer to Figure 11 , the support substrate 123 can be a printed circuit board (PCB) including an array of bonding pads on the upper surface of the support substrate 123. The pattern of the bonding pads on the upper surface of the support substrate 123 can correspond to the pattern of the bonding pads on the lower surface of the package substrate 111. The semiconductor package 100 can be aligned above the upper surface of the support substrate 123, and a reflow process can be performed to reflow the solder balls 122, thereby causing bonding between the package substrate 111 of the semiconductor package 100 and the support substrate 123. Each solder ball 122 can be bonded to a corresponding one of the bonding pads on the lower surface of the package substrate 111 and a corresponding one of the bonding pads on the upper surface of the support substrate 123. An optional underfill material portion 124 can be applied to the space between the lower surface of the package substrate 111 and the upper surface of the support substrate 123. The underfill material portion 124 can laterally surround and contact each solder ball 122 that bonds the package substrate 111 to the support substrate 123.

[0117] Figure 12 is a vertical cross-sectional view of a semiconductor package 100 according to another embodiment of the present disclosure, which includes a plurality of solder balls 122 located on the lower surface of the package substrate 111, a thermal interface material (TIM) 125 located above the plurality of semiconductor IC dies 107, and a lid structure 126 mounted to the upper surface of the first molded portion 109. Figure 12 The semiconductor package 100 shown can be similar to the semiconductor package 100 referred to above with reference to Figure 10 described. Therefore, for the sake of brevity, the repeated description of similar features is omitted. Figure 12 The semiconductor package 100 shown and Figure 10The difference of the semiconductor package 100 is that the thermal interface material (TIM) 125 is located on top of the multiple semiconductor IC chips 107 and the lid structure 126 is mounted to the upper surface of the first molding portion 109. The thermal interface material 125 may include a suitable material to facilitate heat transfer from the semiconductor IC chips 107. Suitable materials for the thermal interface material 125 may include, for example, aluminum gel, graphite, indium metal, etc. The lid structure 126 may include a suitable structural material, such as copper or stainless steel. The lid structure 126 may extend over the thermal interface material 125 and may be in thermal contact with the thermal interface material 125. The lid structure 126 may replace the ring structure 119 as described above with reference to Figure 10 or may be additionally provided. For example, in different embodiments, the ring structure 119 may be omitted and the lid structure 126 may be directly mounted to the upper surface of the first molding portion 109. Alternatively, the ring structure 119 may be mounted to the upper surface of the first molding portion 109 and the lid structure 126 may be mounted to the ring structure 119. In additional embodiments, both the ring structure 119 and the lid structure 126 may be mounted to different regions of the first molding portion 109. The thermal interface material 125 and the lid structure 126 may provide improved thermal management for the semiconductor package 100. The lid structure 126 may also provide protection for the semiconductor package 100 and may enhance the structural integrity of the semiconductor package 100. Figure 12 The semiconductor package 100 shown may be mounted to a support substrate (e.g., a PCB) as shown in Figure 11 shown.

[0118] Figures 13 to 17 is a sequential vertical cross-sectional view showing the manufacturing process of a semiconductor package 100 according to another embodiment of the present disclosure. Figure 13 is a vertical cross-sectional view of an intermediate structure according to various embodiments of the present disclosure, which includes functional components 130 mounted on the second side surface 142 of the interposer 103. Figure 13 The intermediate structure of Figure 6 may be derived from the intermediate structure described above with reference to Figure 13In the intermediate structure, one or more functional components 130 may be mounted on the second side surface 142 of the interposer 103. The one or more functional components 130 may include semiconductor material (e.g., silicon). The one or more functional components 130 may include, but are not limited to, dies, intelligent power devices (IPDs), and / or bridging dies, such as local-silicon interconnects (LSIs), which may be used to bridge two or more semiconductor IC dies 107 mounted on the first side surface 141 of the interposer 103. Other suitable functional components 130 are within the scope of the present disclosure. A bonding structure 131, such as a microbump bonding structure, may be used to bond the one or more functional components 130 to the second side surface 142 of the interposer 103.

[0119] Figure 14 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, showing a plurality of package substrates 111 located above the second side surface 142 of the interposer 103 and the functional components 130. Refer to Figure 14 , each package substrate 111 may include a dielectric material matrix 115 and have conductive interconnect features 116 (e.g., metal lines, vias, bond pads, etc.) located within and extending through the dielectric material matrix 115. In Figure 14 the illustrated embodiment, a pair of package substrates 111 are shown located above the second side surface 142 of the interposer 103 within the unit area (UA), although it should be understood that more than two package substrates 111 may be located above the second side surface 142 of the interposer 103 within the unit area (UA).

[0120] In Figure 14 the embodiment, the package substrate 111 is a "coreless" package substrate 111 that lacks a solid substrate core 112 as described above with reference to Figure 7A and Figure 7B . Instead, the package substrate 111 may include a dielectric material 115 (e.g., a laminated film, an organic material layer, a polymer film, an oxide layer, a nitride layer, or a combination thereof), in which the conductive interconnect features 116 are formed. In some embodiments, the coreless package substrate 111 may be fabricated by, for example, using the methods described above with reference to Figure 7A and Figure 7BThe multilayer redistribution structure 113 is formed in the manner described, and then the multilayer redistribution structure 113 is separated from the carrier substrate to provide the coreless package substrate 111. An optional outer coating (e.g., solder mask) may be located over the redistribution structure 113. Other suitable materials and / or configurations for the package substrate 111 are within the scope of this disclosure. In some embodiments, one or more of the plurality of package substrates 111 over the second side surface 142 of the interposer 103 may include the solid substrate core 112 as described above. In some embodiments, each package substrate 111 may have a thickness of about 1.8 mm or less, such as between about 0.2 mm and about 1.8 mm. It should be understood that larger or smaller thicknesses of the package substrate 111 may also be used.

[0121] Referring again to Figure 14 , each package substrate 111 may be bonded to the second side surface 142 of the interposer 103 via a plurality of bonding material portions 117 (e.g., solder joints). To bond the package substrate 111 to the interposer 103, the package substrate 111 may be aligned over the second side surface 142 of the interposer 103 such that the first side surface 143 of the package substrate 111 faces the second side surface 142 of the interposer 103. As Figure 14 shown, one or more package substrates 111 may at least partially cover the functional components 130. A plurality of bonding material portions 117 (e.g., solder balls) may be located between the bonding pads 144 on the first side surface 143 of each package substrate 111 and the corresponding bonding pads 145 on the second side surface 142 of the interposer 103. A reflow process may be performed to reflow the bonding material portions 117, thereby causing bonding between each package substrate 111 and the interposer 103. The reflow process may be performed at an elevated temperature, such as between 150 °C and 350 °C (e.g., about 250 °C). After the reflow process, each bonding material portion 117 may be bonded to a corresponding one of the bonding pads 144 on the first side surface 143 of the package substrate 111 and a corresponding one of the bonding pads 145 on the second side surface 142 of the interposer 103. In some embodiments, the bonding material portions 117 may include C4 solder balls, and the package substrate 111 may be bonded to the interposer 103 via an array of C4 solder balls. In some embodiments, after the bonding process, the first side surface 143 of the package substrate 111 may be vertically spaced apart from the underlying functional components 130. Alternatively, one or more package substrates 111 may contact the underlying functional components 130.

[0122] In various embodiments, as Figure 14 shown, the plurality of package substrates 111 may be mounted over the second side surface 142 of the interposer 103 within each unit area (UA) of the second carrier substrate 110. The package substrates 111 may be laterally spaced apart from each other. As referred to aboveFigure 7A and Figure 7B In the embodiments described and shown in Figure 14 , each encapsulation substrate 111 may be laterally restricted relative to the interposer 103 such that one or more horizontal dimensions of each encapsulation substrate 111 are less than the corresponding dimensions of the interposer 103. In some embodiments, as shown in Figure 14 , the peripheral edges of the plurality of encapsulation substrates 111 within each unit area (UA) may be spaced apart from the peripheral edge of the interposer 103 within that unit area (UA). Figure 14 As shown, the peripheral edges of the plurality of encapsulation substrates 111 within each unit area (UA) may be spaced apart from the peripheral edge of the interposer 103 within that unit area (UA).

[0123] Figure 15 FIG. Figure 15 is a vertical cross - sectional view of an exemplary intermediate structure in accordance with various embodiments of the present disclosure, showing a second molding portion 118 that contacts a second side surface 142 of the interposer 103 and laterally surrounds each encapsulation substrate 111. Referring to Figure 15 , the second molding portion 118 may contact the second side surface 142 of the interposer 103 and may extend at least partially within a gap between the second side surface 142 of the interposer 103 and each encapsulation substrate 111. In some embodiments, the second molding portion 118 may contact and may laterally surround some or all of the bonding material portions 117 that bond the encapsulation substrates 111 to the interposer 103. In some embodiments, the second molding portion 118 may contact each functional component 130 mounted to the second side surface 142 of the interposer 103. In some embodiments, the second molding portion 118 may laterally surround each functional component 130 and may be located within a gap between the lower surface of each functional component 130 and the second side surface 142 of the interposer 103. The second molding portion 118 may also fill a gap between the upper surface of each functional component 130 and the first side surface 143 of the encapsulation substrate 111 that covers the corresponding functional component 130. Figure 15 Referring to Figure 15 , the second molding portion 118 may contact the second side surface 142 of the interposer 103 and may extend at least partially within a gap between the second side surface 142 of the interposer 103 and each encapsulation substrate 111. In some embodiments, the second molding portion 118 may contact and may laterally surround some or all of the bonding material portions 117 that bond the encapsulation substrates 111 to the interposer 103. In some embodiments, the second molding portion 118 may contact each functional component 130 mounted to the second side surface 142 of the interposer 103. In some embodiments, the second molding portion 118 may laterally surround each functional component 130 and may be located within a gap between the lower surface of each functional component 130 and the second side surface 142 of the interposer 103. The second molding portion 118 may also fill a gap between the upper surface of each functional component 130 and the first side surface 143 of the encapsulation substrate 111 that covers the corresponding functional component 130.

[0124] The second molding portion 118 may laterally surround each encapsulation substrate 111 bonded to the second side surface 142 of the interposer 103. Thus, the second molding portion 118 may be located within and may fill a gap 133 between adjacent encapsulation substrates 111 within each unit area (UA). The second molding portion 118 may also extend around the periphery of the plurality of encapsulation substrates 111 within each unit area (UA). The thickness d of the second molding portion 118 above the side surface of the encapsulation substrate 111 between the outer periphery of the encapsulation substrate 111 and the periphery of the unit area (UA) may be at least 40 μm, for example, between about 40 μm and about 2000 μm.

[0125] In various embodiments, the second molding portion 118 may be composed of a suitable material, such as an epoxy resin material, as referred to above in reference to Figure 8 Figure 8As described. The portion of the second molding part 118 that extends above the horizontal plane including the upper surface of the encapsulation substrate 111 can be removed using a planarization process such as a chemical mechanical planarization (CMP) process. Thus, the upper surface of the second molding part 118 can be substantially coplanar with the upper surface of the encapsulation substrate 111. In some embodiments, the second molding part 118 can include the same material as the first molding part 109 described above with reference to Figure 4 Or, the second molding part 118 can be composed of a material different from that of the first molding part 109.

[0126] In various embodiments, each unit area (UA) of the second carrier substrate 110 can include a second molding part 118 that laterally surrounds a plurality of encapsulation substrates 111. In some embodiments, the second molding part 118 can form a continuous matrix extending between the unit areas (UAs) of the second carrier substrate 110 and laterally surround a plurality of encapsulation substrates 111 within each unit area (UA) of the second carrier substrate 110.

[0127] Figure 16 is a vertical cross-sectional view of a semiconductor package 100 according to various embodiments of the present disclosure. Referring to Figure 16 , the second carrier substrate 110 can be removed from the exemplary intermediate structure, as described above with reference to Figure 9 A cutting process can be used to separate each unit area (UA) of the exemplary intermediate structure to provide a plurality of discrete semiconductor packages 100. After the cutting process, the semiconductor packages 100 can be disposed on a suitable support element, such as a dicing tape 120 supported by a tape frame 121. The semiconductor packages 100 can be inverted (i.e., flipped) with respect to the Figure 15 orientation shown such that the interposer 103 and the plurality of semiconductor IC dies 107 can be located above the plurality of encapsulation substrates 111.

[0128] Referring again to Figure 16, according to various embodiments, a semiconductor package 100 may include an interposer 103, a plurality of semiconductor IC dies 107 mounted on a first side surface 141 of the interposer 103, an underfill material portion 108 in a gap between the first side surface 141 of the interposer 103 and each semiconductor IC die 107, and a first molding portion 109 laterally surrounding the plurality of semiconductor IC dies 107. A second side surface 142 of the interposer 103 may be bonded to a plurality of package substrates 111 through a plurality of bonding material portions 117. The package substrates 111 may be laterally restricted relative to the interposer 103 such that at least one horizontal dimension of the interposer 103 may be greater than a corresponding horizontal dimension of each package substrate 111. In some embodiments, one or more of the package substrates 111 may be coreless package substrates 111. At least one functional component 130 may be bonded to the second side surface 142 of the interposer 103. At least a portion of each functional component 130 may be located between the second side surface 142 of the interposer 103 and a first side surface 143 of at least one package substrate 111.

[0129] A second molding portion 118 may contact the second side surface 142 of the interposer 103 and may laterally surround each package substrate 111. The second molding portion 118 may be located within a gap 133 between adjacent package substrates 111 and may also laterally surround an outer periphery of the plurality of package substrates 111. In some embodiments, a thickness d of the second molding portion 118 on a side surface of the package substrate 111 between an outer periphery of the package substrate 111 and an outer peripheral side surface of the semiconductor package 100 may be at least 40 μm, such as between about 40 μm and about 2000 μm. A side surface of the semiconductor package 100 may be formed by the first molding portion 109, the interposer 103, and the second molding portion 118.

[0130] Figure 17 is a vertical cross-sectional view of a semiconductor package 100 according to various embodiments of the present disclosure, which includes a plurality of solder balls 122 on a lower surface of the package substrate 111 and an annular structure 119 mounted to an upper surface of the first molding portion 109. Refer to Figure 17 , the plurality of solder balls 122 and the annular structure 119 may be as described above with reference to Figure 10 . Accordingly, for the sake of brevity, a repeated description of similar features is omitted. In other embodiments, a lid structure 126 and / or an optional thermal interface material (TIM) 125 may be provided as shown in Figure 12 . The semiconductor package 100 may be mounted to a suitable support substrate 123 (e.g., a PCB) as described above with reference to Figure 11 .

[0131] Figure 18is a flowchart showing a method 200 of manufacturing a semiconductor package 100 according to various embodiments of the present disclosure. Referring to Figure 2 and Figure 18 , in step 201 of the exemplary method 200, at least one semiconductor integrated circuit (IC) die 107 may be mounted on a first surface 141 of the interposer 103. Referring to Figure 7A , Figure 7B , Figure 14 and Figure 18 , in step 203 of the exemplary method 200, a package substrate 111 may be mounted on a second surface 142 of the interposer 103, wherein at least one horizontal dimension of the package substrate 111 is smaller than a corresponding horizontal dimension of the interposer 103. Referring to Figure 8 , Figure 12 , Figure 15 and Figure 18 , in step 205 of the exemplary method 200, a molding portion 118 may be formed on the second surface 142 of the interposer 103 and laterally surround the package substrate 111.

[0132] Referring to all the drawings and according to various embodiments of the present disclosure, a semiconductor package 100 may include an interposer 103, at least one semiconductor integrated circuit (IC) die 107 mounted on a first surface 141 of the interposer 103, a package substrate 111 bonded to a second surface 142 of the interposer 103, and a molding portion 118 contacting the second surface 142 of the interposer 103 and laterally surrounding the package substrate 111.

[0133] In one embodiment, the package substrate 111 includes at least one horizontal dimension (e.g., package substrate width) that is smaller than a corresponding horizontal dimension (e.g., interposer width) of the interposer 103.

[0134] In another embodiment, a thickness d of the molding portion 118 above a side surface of the package substrate 111 is at least 40 μm.

[0135] In another embodiment, a plurality of semiconductor IC dies 107 are mounted on a first surface 141 of the interposer 103, and the molding portion 118 includes a second molding portion 118, wherein the semiconductor package 100 further includes a plurality of first bonding structures 106 that bond the plurality of semiconductor IC dies 107 to the first surface 141 of the interposer 103, a underfill material portion 108 that is located between the plurality of semiconductor IC dies 107 and the first surface 141 of the interposer 103 and laterally surrounds the plurality of first bonding structures 106, a first molding portion 109 that laterally surrounds the plurality of semiconductor IC dies 107, and a plurality of second bonding structures 122 that bond the package substrate 111 to the second surface 142 of the interposer 103, wherein the second molding portion 118 extends at least partially within a space between the package substrate 111 and the second surface 142 of the interposer 103.

[0136] In another embodiment, a plurality of side surfaces of the semiconductor package 100 are formed by the first molding portion 109, the interposer 103, and the second molding portion 118.

[0137] In another embodiment, the semiconductor package 100 further includes at least one of an annular structure 119 and a lid structure 126 mounted on an upper surface of the first molding portion 109.

[0138] In another embodiment, the lid structure 126 is mounted on the upper surface of the first molding portion 109 and extends over the plurality of semiconductor IC dies 107, and a thermal interface material (TIM) 125 is located between the upper surface of the plurality of semiconductor IC dies 107 and the lid structure 126.

[0139] In another embodiment, the plurality of second bonding structures 122 include a plurality of solder portions 122, and the second molding portion 118 contacts and laterally surrounds the plurality of solder portions 122.

[0140] In another embodiment, the interposer 103 includes an organic interposer having a thickness of at least 40 μm.

[0141] In another embodiment, the package substrate 111 has a thickness of 1.8 mm or less.

[0142] In another embodiment, the package substrate 111 includes a coreless package substrate 111.

[0143] In another embodiment, the semiconductor package 100 includes a plurality of package substrates 111 bonded to the second surface 142 of the interposer 103.

[0144] In another embodiment, the semiconductor package 100 further includes a functional component 130 bonded to the second surface 142 of the interposer 103, wherein at least a portion of the functional component 130 is located between the second surface 142 of the interposer 103 and the package substrate 111.

[0145] Another embodiment relates to a semiconductor package 100, including an interposer 103, at least one semiconductor integrated circuit (IC) die 107 mounted on the first surface 141 of the interposer 103, a plurality of package substrates 111 bonded to the second surface 142 of the interposer 103, and a molding portion 118 contacting the second surface 142 of the interposer 103 and located in the gap between adjacent package substrates 111 among the plurality of package substrates 111.

[0146] In one embodiment, the molding portion 118 laterally surrounds each package substrate 111, and the thickness d of the molding portion 118 between the outer periphery of the plurality of package substrates 111 and the periphery of the interposer 103 is at least 40 μm.

[0147] In another embodiment, the semiconductor package 100 further includes a functional component 130 mounted on the second surface 142 of the interposer 103, wherein the molding portion 118 laterally surrounds the functional component 130 and extends in the gap between the functional component 130 and one of the plurality of package substrates 111.

[0148] In another embodiment, the functional component 130 includes at least one of a die, an intelligent power device (IPD), and a bridging die.

[0149] Another embodiment relates to a method of at least a semiconductor package 100, which includes mounting at least one semiconductor integrated circuit (IC) die 107 on the first surface 141 of the interposer 103; mounting a package substrate 111 on the second surface 142 of the interposer 103, wherein at least one horizontal dimension of the package substrate 111 is smaller than the corresponding horizontal dimension of the interposer 103; and forming a molding portion 118 on the second surface 142 of the interposer 103 and laterally surrounding the package substrate 111.

[0150] In one embodiment, the method further includes providing a package structure on a carrier substrate 110, the package structure including an interposer 103 and at least one semiconductor IC die 107 mounted to the first surface 141 of the interposer 103, wherein when the package structure is located on the carrier substrate 110, the package substrate 111 is mounted to the second surface 142 of the interposer 103, and the molding portion 118 is formed on the second surface 142 of the interposer 103 and laterally surrounds the package substrate 111.

[0151] In another embodiment, the method further includes removing the carrier substrate 111; and performing a cutting process through the interposer 103 and the molding portion 118 to provide discrete semiconductor packages 100, wherein the thickness d of the molding portion 118 above the side surface of the package substrate 111 is at least 40 μm.

[0152] The features of many embodiments are outlined above, enabling those of ordinary skill in the art to which the present disclosure pertains to better understand the various embodiments of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present disclosure pertains should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, and alterations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, characterized in that, Comprising: An interposer; At least one semiconductor integrated circuit die, mounted on a first surface of the interposer; A package substrate, bonded to a second surface of the interposer; And A molding portion, contacting the second surface of the interposer and laterally surrounding the package substrate.

2. The semiconductor package according to claim 1, wherein The package substrate includes a package substrate width dimension that is less than a corresponding interposer width dimension of the interposer.

3. The semiconductor package according to claim 1, wherein, A plurality of semiconductor integrated circuit dies are mounted on the first surface of the interposer, and the molding portion includes a second molding portion, wherein the semiconductor package further includes: A plurality of first bonding structures for bonding the plurality of semiconductor integrated circuit dies to the first surface of the interposer; An underfill material portion, located between the plurality of semiconductor integrated circuit dies and the first surface of the interposer and laterally surrounding the plurality of first bonding structures; A first molding portion, laterally surrounding the plurality of semiconductor integrated circuit dies; and A plurality of second bonding structures for bonding the package substrate to the second surface of the interposer, wherein the second molding portion at least partially extends within a space between the package substrate and the second surface of the interposer.

4. The semiconductor package according to claim 3, wherein, A plurality of side surfaces of the semiconductor package are formed by the first molding portion, the interposer, and the second molding portion.

5. The semiconductor package according to claim 4, wherein, Further including at least one of a ring structure and a cover structure mounted on an upper surface of the first molding portion.

6. The semiconductor package according to claim 5, wherein, The cover structure is mounted on the upper surface of the first molding portion and extends over the plurality of semiconductor integrated circuit dies, and a thermal interface material is located between an upper surface of the plurality of semiconductor integrated circuit dies and the cover structure.

7. The semiconductor package according to claim 1, wherein Further including a functional component bonded to the second surface of the interposer, wherein at least a portion of the functional component is located between the second surface of the interposer and the package substrate.

8. A semiconductor package, characterized in that, Comprising: An interposer; At least one semiconductor integrated circuit die, mounted on a first surface of the interposer; A plurality of package substrates, bonded to a second surface of the interposer; And A molding portion, contacting the second surface of the interposer and located in a gap between adjacent ones of the plurality of package substrates.

9. The semiconductor package according to claim 8, wherein, The molding portion laterally surrounds each of the plurality of package substrates, and a thickness of the molding portion between an outer periphery of the plurality of package substrates and an outer periphery of the interposer is at least 40 μm.

10. The semiconductor package according to claim 8, wherein, Further including a functional component mounted on the second surface of the interposer, wherein the molding portion laterally surrounds the functional component and extends within a gap between the functional component and one of the plurality of package substrates.

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