Intermediate structure for circuit preparation process of packaging carrier plate

Abstract

The utility model provides an intermediate structure used in the preparation process of a packaging carrier board circuit, which comprises a substrate, a carrier board circuit, an auxiliary copper layer and a dry film layer, the carrier board circuit is arranged on the upper surface of the substrate, the auxiliary copper layer covers the upper surface of the substrate and is provided with an opening for exposing the carrier board circuit, the side wall of the opening is not contacted with the carrier board circuit, and the dry film layer is arranged on the substrate. The auxiliary copper layer incompletely surrounds the carrier board circuit, and the dry film layer covers the upper surface and the side wall of the carrier board circuit. The intermediate structure for the preparation process of the packaging carrier board circuit can be used for preparing the packaging carrier board, the uniformity of the copper thickness of the packaging carrier board circuit is improved, the phenomenon that etching liquid medicine laterally etches the carrier board circuit is reduced, the scrap of the packaging carrier board is reduced, and the yield of products is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to an intermediate structure for the preparation process of a packaging carrier board circuit. Background Art

[0002] With the continuous upgrading of electronic products, electronic devices are becoming increasingly thin, light, short, and small, and the requirements for printed circuit boards are also getting higher and higher. As a high-density interconnection printed circuit board, the line density of an IC packaging carrier board is required to be higher than that of an ordinary printed circuit board, and the refined requirement for line width even reaches below 20μm. Therefore, the traditional subtractive process (Tenting) has far been unable to meet the requirements of such refined circuits. The minimum line width that can be achieved by the conventional subtractive process is only 30μm, and there are also strong restrictions on the copper thickness. In order to produce more refined circuits, an improved semi-additive process (modify Smei-Additive Process, mSAP) with a minimum line width and line pitch design of 15μm has been derived. The mSAP process uses a method of patterning the circuit first and then electroplating. When the distribution of the circuit pattern is uneven, there are differences in the current distribution of electroplating copper for the circuit patterns in different regions, which will cause uneven electroplated copper thickness for the circuits in different regions, resulting in poor circuit uniformity and a series of problems in the subsequent processing, thus reducing the product yield.

[0003] Therefore, how to provide an intermediate structure for the preparation process of a packaging carrier board circuit to improve the copper thickness uniformity and integrity of the carrier board circuit and enhance the product yield has become an important problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Utility Model

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide an intermediate structure for the preparation process of a packaging carrier board circuit to solve the problem of poor copper thickness uniformity of the carrier board circuit in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present utility model provides an intermediate structure for the preparation process of a packaging carrier board circuit, including:

[0007] A substrate;

[0008] A carrier board circuit, which is located on the upper surface of the substrate;

[0009] An auxiliary copper layer, which covers the upper surface of the substrate and is provided with an opening exposing the carrier board circuit. The side wall of the opening does not contact the carrier board circuit, and the auxiliary copper layer does not completely surround the carrier board circuit;

[0010] A dry film layer, which covers the upper surface and the side wall of the carrier board circuit.

[0011] Optionally, copper pillars are arranged in the substrate, and the top ends of the copper pillars contact the carrier board circuit.

[0012] Optionally, the number of the carrier board circuits is at least two, and the shortest distance between two adjacent carrier board circuits is not less than 550 μm.

[0013] Optionally, the distance between the auxiliary copper layer and the carrier board circuit is not less than 200 μm, the length between the boundary of the dry film layer and the upper surface boundary of the carrier board circuit is not less than 160 μm, and the distance between the auxiliary copper layer and the carrier board circuit is greater than the length between the boundary of the dry film layer and the upper surface boundary of the carrier board circuit.

[0014] Optionally, the thickness of the dry film layer is greater than or equal to 50 μm.

[0015] Optionally, the carrier board circuit includes solder pads. The number of the solder pads is at least two. A first air guiding opening connecting the two solder pads is arranged in the auxiliary copper layer. A second air guiding opening is also arranged in the auxiliary copper layer. The second air guiding opening connects the solder pad and any edge of the substrate. The first opening and the second opening are long strip openings.

[0016] Optionally, the width of the first air guiding opening is not less than 180 μm.

[0017] Optionally, the width of the second air guiding opening is not less than 180 μm.

[0018] Optionally, the number of the first air guiding openings is one or more, and the number of the second air guiding openings is one or more.

[0019] Optionally, the range of the inclination angle of the extending direction of the second air guiding opening relative to a predetermined horizontal direction is 0° to 180°.

[0020] As described above, the intermediate structure for the preparation process of the encapsulation carrier board circuit of the present utility model includes a substrate, a carrier board circuit, an auxiliary copper layer, and a dry film layer. Among them, the carrier board circuit is located on the upper surface of the substrate, the auxiliary copper layer covers the upper surface of the substrate and is provided with an opening exposing the carrier board circuit. The side wall of the opening does not contact the carrier board circuit, and the auxiliary copper layer does not completely surround the carrier board circuit. The dry film layer covers the upper surface and the side wall of the carrier board circuit. The intermediate structure for the preparation process of the encapsulation carrier board circuit of the present utility model can be used for preparing an encapsulation carrier board, improving the uniformity of the encapsulation carrier board circuit, solving the problems of poor line width uniformity of the carrier board circuit, uneven thickness of the carrier board after lamination, uneven thickness of the ink on the pattern after solder mask, and the existence of pseudo exposed copper or true copper leakage on some ink surfaces. In addition, the present utility model covers the upper surface and the side wall of the carrier board circuit with a dry film, which can effectively reduce the side etching of the carrier board circuit by the etching solution when removing the auxiliary copper layer, reduce the scrap rate of the encapsulation carrier board, and improve the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shows a flowchart of the Tenting process.

[0022] Figure 2 Shows a flowchart of the mSAP process.

[0023] Figure 3 Shows a cross-sectional view of the intermediate structure for the preparation process of the encapsulation carrier board circuit of the present utility model in an embodiment ( Figure 4 in the direction of P-P').

[0024] Figure 4 Shows Figure 3 a top view of the structure in

[0025] Figure 5 Shows Figure 4 a top view of the structure obtained after removing the dry film layer from the structure in

[0026] Figure 6 Shows a flowchart of an improved mSAP process.

[0027] Figure 7 Shows Figure 4 a top view of the structure obtained after removing the auxiliary copper layer from the structure in

[0028] Figure 8 Shows Figure 7 a top view of the structure obtained after removing the dry film layer from the structure in

[0029] Figure 9 Shows a top view of the intermediate structure for the preparation process of the encapsulation carrier board circuit of the present utility model in another embodiment.

[0030] Figure 10Shown is a top view of an intermediate structure without a gas guiding opening provided.

[0031] Figure 11 Shown is a top view of the intermediate structure of the present utility model for the preparation process of the encapsulation carrier board circuit in yet another embodiment.

[0032] Explanation of reference numerals

[0033] 1 Substrate

[0034] 101 Core layer

[0035] 102 Copper foil layer

[0036] 2 Copper pillar

[0037] 3 Carrier board circuit

[0038] 4 Auxiliary copper layer

[0039] 5 Dry film layer

[0040] 6 Spacing

[0041] 7 Pad

[0042] 8 First gas guiding opening

[0043] 9 Second gas guiding opening

[0044] 10 Zigzag wire

[0045] L1 Spacing between the auxiliary copper layer and the carrier board circuit

[0046] L2 Shortest spacing between two adjacent carrier board circuits

[0047] L3 Width of the first gas guiding opening

[0048] L4 Width of the second gas guiding opening

[0049] θ Inclination angle of the second gas guiding opening Detailed implementation manners

[0050] Please refer to Figure 1 and Figure 2 , wherein, Figure 1 Shown is a flowchart of the Tenting process, including the following steps: First step, the process before drilling; Second step, laser drilling or mechanical drilling; Third step, desmearing and electroless copper plating; Fourth step, full panel copper electroplating (hole filling electroplating); Fifth step, pretreatment before patterning, microetching and roughening the board surface; Sixth step, laminating dry film / coating wet film (sensitization); Seventh step, exposure and pattern transfer; Eighth step, developing to remove the redundant dry film; Ninth step, etching to remove the redundant copper surface; Tenth step, removing the dry film / wet film on the pattern; Eleventh step, pattern inspection; Twelfth step, post-patterning process.Figure 2 Shown is a flowchart of the mSAP process, including the following steps: First step, the processes before drilling; Second step, laser drilling or mechanical drilling; Third step, desmearing and electroless copper plating; Fourth step, pre-graphical treatment to pickle and clean the board surface; Fifth step, laminating dry film (photosensitive / anti-electroplating solution); Sixth step, exposure and pattern transfer; Seventh step, developing to remove the dry film on the pattern; Eighth step, pattern electroplating (hole filling electroplating); Ninth step, removing the redundant dry film; Tenth step, flash etching to remove the copper surface outside the pattern; Eleventh step, pattern inspection; Twelfth step, post-graphical processes. Compared with Figure 1 with Figure 2 , the biggest difference between the Tenting process and the mSAP process lies in the way of copper electroplating. The Tenting process adopts full-panel copper electroplating and then makes circuit patterns. The thickness uniformity of the electroplated copper layer in this way is relatively good. While in the mSAP process, the circuit patterns are made first and then copper electroplating for the patterns. Due to the uncertainty of the pattern distribution, and most pattern designs are uneven and irregular, for example, there are areas with dense circuits and open areas. When electroplating copper, there will be differences in the current distribution in different areas, which ultimately leads to differences in the thickness of the electroplated copper layer in different areas. Therefore, the thickness uniformity of the electroplated copper layer in the mSAP process is worse than that of the full-panel copper electroplated layer in the Tenting process, resulting in worse uniformity of line width and line pitch (large R value), and even some areas exceeding the customer's specifications. In addition, the uneven thickness of the copper layer in the inner-layer pattern leads to uneven thickness of the carrier board after lamination, and the uneven thickness of the copper layer in the outer-layer pattern leads to uneven thickness of the ink layer on the pattern after solder mask, and even there are defects such as pseudo-exposed copper or true copper leakage on some ink surfaces. After the final surface treatment such as nickel-palladium-gold or electroless gold, there is a problem of insufficient ink layer thickness in the areas with thicker copper layers.

[0051] For products that need to use the mSAP process, the inventors of the present application designed an intermediate structure for the preparation process of the encapsulation carrier board circuit, which can realize the improvement of the mSAP process flow and obtain an encapsulation carrier board circuit with more uniform copper thickness and line width.

[0052] The following illustrates the implementation manners of the present utility model through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present utility model from the content disclosed in this specification. The present utility model can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model.

[0053] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole pieces, steps or components, but does not exclude the presence or addition of one or more other features, whole pieces, steps or components.

[0054] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0055] When detailing the embodiments of the present utility model, for the convenience of description, the schematic diagrams showing the device structure may be enlarged locally without following the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present utility model here. In addition, the three-dimensional spatial dimensions of length, width, and depth should be included in actual production.

[0056] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present utility model in a schematic manner. The structures, proportions, sizes, etc. shown in the drawings are only used to cooperate with the disclosed content for those skilled in this art to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have technical substance. Thus, only the components related to the present utility model are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components may also be more complex. Any modification of the structure, adjustment of the proportion or size, without affecting the functions that the present invention can generate and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0057] Embodiment 1

[0058] The present utility model provides an intermediate structure for the preparation process of a package substrate circuit. Please refer to Figures 3 to 4 shown as a schematic diagram of the structure of the intermediate structure in an embodiment, where Figure 3 is a cross-sectional view, Figure 4 is a partial top view. The intermediate structure includes a substrate 1, a carrier circuit 3, an auxiliary copper layer 4, and a dry film layer 5. Among them, the carrier circuit 3 is located on the upper surface of the substrate 1.

[0059] Specifically, the auxiliary copper layer 4 covers the upper surface of the substrate 1 and is provided with an opening exposing the carrier circuit 3. The side wall of the opening does not contact the carrier circuit 3, and the auxiliary copper layer 4 does not completely surround the carrier circuit 3, that is, the auxiliary copper layer 4 is located in the open area of the carrier circuit 3 pattern, making the pattern to be copper-plated evenly distributed. On the other hand, it also increases the residual copper rate of the pattern. When performing pattern electroplating subsequently, the presence of the auxiliary copper layer 4 enables the current in the electroplating process to flow more evenly, effectively avoiding the problems caused by uneven copper thickness of the carrier circuit 3 and improving the yield of the product.

[0060] Specifically, the dry film layer 5 covers the upper surface and side walls of the carrier board circuit 3. Since the auxiliary copper layer 4 is used to assist in improving the graphic copper thickness uniformity of the carrier board circuit 3, after the graphic electroplating is completed, the auxiliary copper layer 4 still needs to be removed. Therefore, an additional step of forming the patterned dry film layer 5 is added in the mSAP process, so that the dry film layer 5 completely covers the pattern of the carrier board circuit 3 (i.e., the dry film layer 5 covers the upper surface and side walls of the carrier board circuit 3) without covering the pattern of the auxiliary copper layer 4, exposing the auxiliary copper layer 4, thereby ensuring that the carrier board circuit 3 will not be damaged by etching, such as side etching, when removing the auxiliary copper layer 4 through acid etching, and improving the integrity of the carrier board circuit 3.

[0061] As an example, the substrate 1 includes a core layer 101 and copper foil layers 102. In some embodiments, the copper foil layers 102 are provided on both sides of the core layer 101.

[0062] As an example, copper pillars 2 are provided in the substrate 1, and the tops of the copper pillars 2 are in contact with the carrier board circuit 3.

[0063] As an example, the number of the carrier board circuits 3 is at least two, and the specific number can be determined according to specific circumstances. The shortest distance L2 between two adjacent carrier board circuits 3 is not less than 550 μm. When the shortest distance L2 between two adjacent carrier board circuits 3 is greater than or equal to 550 μm, there is a relatively large empty area in the pattern of the carrier board circuit 3, and it is necessary to design the auxiliary copper layer 4 to make the pattern uniform. When the shortest distance L2 between two adjacent carrier board circuits 3 is less than 550 μm, the pattern of the carrier board circuit 3 itself is relatively uniform, and there is no need to add the auxiliary copper layer 4 to improve the pattern uniformity.

[0064] For a clearer display Figure 4 of the distribution of the carrier board circuits 3 Figure 5 in Figure 4 , the dry film layer 5 is removed. Please refer to

[0065] As an example, Figure 5The spacing L1 between the auxiliary copper layer 4 and the carrier board circuit 3 (i.e., the width of the interval 6) is shown in [Figure 0]. In some embodiments, L1 is not less than 200 μm, so that the carrier board circuit 3 is independent, which is conducive to the dry film layer 5 completely covering the carrier board circuit 3, and the carrier board circuit 3 can be protected when the auxiliary copper layer 4 is removed. The length between the boundary of the dry film layer 5 and the upper surface boundary of the carrier board circuit 3 is not less than 160 μm, and the spacing L1 between the auxiliary copper layer 4 and the carrier board circuit 3 is greater than the length between the boundary of the dry film layer 5 and the upper surface boundary of the carrier board circuit 3, so that the dry film layer 5 can completely cover the carrier board circuit 3 without contacting the auxiliary copper layer 4, facilitating the removal of the auxiliary copper layer 4. The spacing L1 between the auxiliary copper layer 4 and the carrier board circuit 3 and the length between the boundary of the dry film layer 5 and the upper surface boundary of the carrier board circuit 3 can be reasonably adjusted to appropriate values according to the specific design of the pattern and the requirements of the circuit copper thickness.

[0066] As an example, the thickness of the dry film layer 5 is greater than or equal to 50 μm. The dry film layer 5 is patterned. To form the dry film layer 5, the entire dry film needs to be pasted on the carrier board circuit 3 and the auxiliary copper layer 4 first, and then patterned. Since there is the interval 6 between the carrier board circuit 3 and the auxiliary copper layer 4, the surface of the pasted film is uneven, so the thickness of the dry film layer 5 is thicker than that of a general dry film.

[0067] In some embodiments, the dry film layer 5 can use a dry film resistant to acid etching solution, which can better protect the carrier board circuit 3 when the auxiliary copper layer 4 is etched in acid.

[0068] As an example, please refer to Figure 6 Shown is a flowchart of an improved mSAP process, including the following steps: The first step is the process before drilling; the second step is laser drilling or mechanical drilling; the third step is desmearing and electroless copper plating; the fourth step is pre-graphical treatment to pickle and clean the board surface; the fifth step is to paste a dry film (photosensitive / anti-electroplating solution); the sixth step is exposure and pattern transfer; the seventh step is developing to remove the dry film on the pattern; the eighth step is pattern electroplating (hole filling electroplating); the ninth step is to remove the excess dry film; the tenth step is 2DF pre-treatment to pickle and clean the board surface; the eleventh step is 2DF to paste a dry film (photosensitive); the twelfth step is 2DF exposure and pattern transfer; the thirteenth step is 2DF developing to remove the excess dry film; the fourteenth step is 2DF etching to remove the excess copper surface; the fifteenth step is 2DF to remove the dry film on the pattern; the sixteenth step is flash etching to remove the copper surface outside the pattern; the seventeenth step is pattern inspection; the eighteenth step is post-pattern process. Among them, 2DF represents adding a layer of patterned dry film, indicating that the improved mSAP process adopts the intermediate structure of the present invention.

[0069] Specifically, asFigure 3 As shown, in the improved mSAP process described above, the auxiliary copper layer 4 is added before the copper plating step, and a patterned dry film (i.e., the dry film layer 5) is added before removing the auxiliary copper layer 4. Among them, after step twelve, "2DF development to remove the excess dry film", an intermediate structure for the preparation process of the package substrate circuit of the present utility model is obtained.

[0070] As an example, please refer to Figure 7 , which shows a top view of the structure obtained after removing the auxiliary copper layer 4 on the basis of the structure shown in Figure 4 . In some embodiments, the auxiliary copper layer 4 is removed by acid etching.

[0071] As an example, please refer to Figure 8 , which shows a top view of the structure obtained after removing the dry film layer 5 on the basis of the structure shown in Figure 7 . At this time, the production of the carrier board circuit 3 is completed.

[0072] The intermediate structure for the preparation process of the package substrate circuit in this embodiment includes a substrate, a carrier board circuit, an auxiliary copper layer, and a dry film layer, and can be used for preparing a package substrate by the mSAP process. By adopting the pattern of the auxiliary copper layer to improve the pattern uniformity of the entire carrier board circuit, the copper thickness of the carrier board circuit after electroplating is more uniform, which can effectively avoid the problems caused by uneven copper thickness of the carrier board circuit. In addition, a dry film layer that completely covers the upper surface and side walls of the carrier board route is adopted, so that the carrier board route is not etched and damaged when the auxiliary copper layer is removed, thereby ensuring the integrity of the carrier board route and improving the yield of the product.

[0073] Embodiment 2

[0074] This embodiment adopts basically the same technical solution as Embodiment 1, except that in Embodiment 1, the carrier board circuit 3 uses a wire, while in this embodiment, the carrier board circuit 3 uses a pad 7.

[0075] Please refer to Figure 9 , which shows a top view of an intermediate structure for the preparation process of the package substrate circuit in this embodiment, and the carrier board circuit 3 includes the pad 7.

[0076] As an example, the number of the pads 7 is at least two. The auxiliary copper layer 4 is provided with a first air guiding opening 8 connecting the two pads 7. The auxiliary copper layer 4 is further provided with a second air guiding opening 9, and the second air guiding opening 9 connects the pad 7 and any plate edge of the substrate 1, that is, both the first air guiding opening 8 and the second air guiding opening 9 are openings exposing the upper surface of the substrate 1 to prevent the auxiliary copper layer 4 from completely surrounding the pad 7.

[0077] As a comparison, please refer to Figure 10, shown as a top view of an intermediate structure without a gas guiding opening provided (i.e., Figure 9 a top view of the structure obtained by removing the first gas guiding opening 8 and the second gas guiding opening 9 from the intermediate structure), wherein, the auxiliary copper layer 4 forms a closed area around the pad 7. When laminating the dry film layer 5, there will be a problem of poor vacuum pumping, resulting in bubbles being easily generated at the gap 6 between the pad 7 (the carrier board circuit 3) and the auxiliary copper layer 4. The etching solution penetrates into the gap 6 and laterally etches the pad 7, and even etches away the entire pad 7, causing the encapsulation carrier board to be scrapped. And as Figure 9 shown, due to the existence of the first gas guiding opening 8 and the second gas guiding opening 9 in the intermediate structure of the present invention, bubbles can be avoided from being generated at the gap 6 during the lamination of the dry film layer 5, effectively reducing the lateral etching damage of the pad 7 and ensuring the integrity of the pad 7.

[0078] As an example, the width of the first gas guiding opening 8 is not less than 180 μm. The width L3 of the first gas guiding opening 8 can be reasonably adjusted to a suitable value according to the specific design of the pattern and the requirements of the circuit copper thickness. In this embodiment, the width L3 of the first gas guiding opening 8 is 180 μm.

[0079] As an example, the width of the second gas guiding opening 9 is not less than 180 μm. The width L4 of the second gas guiding opening 9 can be reasonably adjusted to a suitable value according to the specific design of the pattern and the requirements of the circuit copper thickness. In this embodiment, the width L4 of the second gas guiding opening 9 is 180 μm.

[0080] As an example, the number of the first gas guiding openings 8 is at least one, the number of the second gas guiding openings 9 is at least one, and the numbers of the first gas guiding openings 8 and the second gas guiding openings 9 can be determined according to specific situations and are not limited herein. In this embodiment, the number of the first gas guiding openings 8 is four, and the number of the second gas guiding openings 9 is five.

[0081] As an example, the range of the inclination angle θ of the extending direction of the second gas guiding opening 9 relative to a predetermined horizontal direction is 0° to 180°, such as 20°, 40°, 55°, 75°, 110° or 180°. The second gas guiding opening 9 can be changed to any angular direction according to the actual situation.

[0082] In the intermediate structure of this embodiment, the carrier board circuit is an independent pad. The first gas guiding opening and the second gas guiding opening are added to avoid bubbles from being generated at the gap during the lamination of the dry film layer, which can effectively reduce the lateral etching of the pad and ensure the integrity of the pad.

[0083] Embodiment Three

[0084] This embodiment adopts a technical solution that is basically the same as that of the second embodiment, except that the pattern of the carrier board circuit 3 is different. Among them, the carrier board circuit 3 in the second embodiment includes a plurality of independently arranged circular pads, while the carrier board circuit 3 in this embodiment includes a plurality of independently arranged zigzag conductors 10.

[0085] As an example, please refer to Figure 11 , which shows a top view of an intermediate structure for the preparation process of the carrier board circuit of this embodiment. The carrier board circuit 3 includes a plurality of zigzag conductors 10, and different from the conductors in the first embodiment, the zigzag conductors 10 in this embodiment do not contact any of the board edges of the substrate 1.

[0086] As an example, in this embodiment, the number of the first air guide openings 8 is four, and the number of the second air guide openings 9 is one.

[0087] The intermediate structure of this embodiment can avoid generating air bubbles at the gaps during the dry film laminating on the carrier board circuit, effectively reduce the side etching of the carrier board circuit, and ensure the integrity of the carrier board circuit.

[0088] In summary, the intermediate structure for the preparation process of the carrier board circuit of the present invention includes a substrate, a carrier board circuit, an auxiliary copper layer, and a dry film layer. Among them, the carrier board circuit is located on the upper surface of the substrate, the auxiliary copper layer covers the upper surface of the substrate and is provided with an opening exposing the carrier board circuit. The side wall of the opening does not contact the carrier board circuit, and the auxiliary copper layer does not completely surround the carrier board circuit. The dry film layer covers the upper surface and the side wall of the carrier board circuit. The intermediate structure for the preparation process of the carrier board circuit of the present invention can be used to prepare a carrier board, improve the copper thickness uniformity of the carrier board circuit, solve the problems of the poor copper thickness and line width uniformity of the carrier board circuit, uneven carrier board thickness after lamination, uneven ink thickness on the pattern after solder mask, and false copper exposure or true copper leakage on some ink surfaces. In addition, the present invention covers the upper surface and the side wall of the carrier board circuit with a dry film, which can effectively reduce the side etching of the carrier board circuit when removing the auxiliary copper layer, reduce the scrapping of the carrier board, and improve the product yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0089] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An intermediate structure for the preparation process of the circuit on the encapsulation carrier board, characterized in that, Comprising: A substrate; Carrier board lines located on the upper surface of the substrate; An auxiliary copper layer covering the upper surface of the substrate and having an opening exposing the carrier board lines, with the sidewall of the opening not in contact with the carrier board lines, and the auxiliary copper layer not completely surrounding the carrier board lines; A dry film layer covering the upper surface and sidewalls of the carrier board lines.

2. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 1, wherein: Copper pillars are provided in the substrate, and the top ends of the copper pillars are in contact with the carrier board lines.

3. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 1, wherein: The number of the carrier board lines is at least two, and the shortest distance between adjacent two carrier board lines is not less than 550 μm.

4. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 1, characterized in that: The distance between the auxiliary copper layer and the carrier board lines is not less than 200 μm, the length between the boundary of the dry film layer and the upper surface boundary of the carrier board lines is not less than 160 μm, and the distance between the auxiliary copper layer and the carrier board lines is greater than the length between the boundary of the dry film layer and the upper surface boundary of the carrier board lines.

5. The intermediate structure for the preparation process of the encapsulated carrier board circuit according to claim 1, wherein: The thickness of the dry film layer is greater than or equal to 50 μm.

6. The intermediate structure for the preparation process of the encapsulated carrier board circuit according to claim 1, characterized in that: The carrier board lines include solder pads, the number of the solder pads is at least two, a first air guiding opening connecting the two solder pads is provided in the auxiliary copper layer, a second air guiding opening is also provided in the auxiliary copper layer, the second air guiding opening connects the solder pad and any one edge of the substrate, and the first air guiding opening and the second air guiding opening are long strip openings.

7. The intermediate structure for preparing the circuit of the encapsulation carrier board according to claim 6, wherein: The width of the first air guiding opening is not less than 180 μm.

8. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 6, characterized in that: The width of the second air guiding opening is not less than 180 μm.

9. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 6, wherein: The number of the first air guiding openings is one or more, and the number of the second air guiding openings is one or more.

10. The intermediate structure for the preparation process of the circuit of the encapsulation carrier board according to claim 6, wherein: The range of the inclination angle of the extending direction of the second air guiding opening relative to a predetermined horizontal direction is 0° to 180°.

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