PCIe transmission module based on optical communication

Abstract

The utility model provides a PCIe transmission module based on optical communication, in one scheme, a first DP interface is correspondingly connected to a third DP interface through a first optical fiber DP wire; the second DP interface is correspondingly connected to the fourth DP interface through a second optical fiber DP wire; a clock signal pin and a differential sending signal pin of the first PCIe interface are connected to a clock signal pin and a differential receiving signal pin of the second PCIe interface through high-speed signal pins of the first DP interface and the third DP interface; a differential receiving signal pin of the second PCIe interface is connected to a differential transmitting signal pin of the second PCIe interface through high-speed signal pins of the second DP interface and the fourth DP interface, and a non-data signal pin of the second PCIe interface is connected to a non-data signal pin of the second PCIe interface through low-speed signal pins of the first DP interface, the second DP interface, the third DP interface and the fourth DP interface respectively; therefore, a technical scheme for realizing long-distance high-speed transmission of PCIe data with low cost is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of PCIe transmission modules, in particular to a PCIe transmission module based on optical communication. Background Art

[0002] At present, electronic technology has been continuously developed, and the requirements for corresponding data transmission in various application scenarios are also getting higher and higher. In the field of data acquisition, a PCIe interface is often integrated on a data acquisition card, and the data collected by the data acquisition card is transmitted to the PCIe interface of a computer host through a corresponding data transmission line, and the computer host realizes centralized management of the collected data. At present, the data transmission between conventional PCIe interfaces mainly relies on a transmission line made of metal to achieve electrical transmission. Although relatively high-speed transmission can also be achieved, affected by the material of the transmission medium and the manufacturing process of the transmission line, the data transmission distance between existing PCIe interfaces is generally short. At present, a small part of PCIe transmission technologies based on optical fiber communication have been applied, which can achieve relatively long-distance data transmission, but they require additional processing chips such as FPGAs for auxiliary processing, and the implementation cost is relatively high.

[0003] Therefore, it is necessary to provide a technical solution with low cost that can achieve long-distance high-speed transmission of PCIe data. Summary of the Utility Model

[0004] To solve the above technical problems, the utility model provides a PCIe transmission module based on optical communication.

[0005] The first PCIe transmission module based on optical communication provided by the utility model includes a first DP interface, a second DP interface, a third DP interface, a fourth DP interface, a first PCIe interface, a second PCIe interface, a first optical fiber DP line, and a second optical fiber DP line;

[0006] The high-speed signal pins of the first DP interface are connected to the high-speed signal pins of the third DP interface through the optical fiber of the first optical fiber DP line, and its low-speed signal pins are connected to the low-speed signal pins of the third DP interface through the copper wire of the first optical fiber DP line;

[0007] The high-speed signal pins of the second DP interface are connected to the high-speed signal pins of the fourth DP interface through the optical fiber of the second optical fiber DP line, and its low-speed signal pins are connected to the low-speed signal pins of the fourth DP interface through the copper wire of the second optical fiber DP line;

[0008] The clock signal pin and differential transmission signal pins of the first PCIe interface are connected to the high-speed signal pins of the first DP interface, its differential reception signal pin is connected to the high-speed signal pin of the second DP interface, and its non-data signal pins are respectively connected to the low-speed signal pins of the first DP interface and the second DP interface;

[0009] The clock signal pin and differential reception signal pins of the second PCIe interface are connected to the high-speed signal pins of the third DP interface, its differential transmission signal pin is connected to the high-speed signal pin of the fourth DP interface, and its non-data signal pins are respectively connected to the low-speed signal pins of the third DP interface and the fourth DP interface.

[0010] In a possible implementation, in the first optical communication-based PCIe transmission module, the non-data signal pins of the first PCIe interface and the second PCIe interface at least include a reset pin, a wake-up pin, a voltage pin, and a ground pin.

[0011] In a possible implementation, in the first optical communication-based PCIe transmission module, both the first optical fiber DP line and the second optical fiber DP line have a 4-core optical fiber and 8-core copper wire structure.

[0012] In a possible implementation, in the first optical communication-based PCIe transmission module, the first DP interface, the second DP interface, and the first PCIe interface are arranged on a first PCB board.

[0013] In a possible implementation, in the first optical communication-based PCIe transmission module, the third DP interface, the fourth DP interface, and the second PCIe interface are arranged on a second PCB board.

[0014] The present utility model further provides a second optical communication-based PCIe transmission module, including a first QSFP interface, a second QSFP interface, a first electrical transmission interface, a second electrical transmission interface, a first PCIe interface, a second PCIe interface, an optical fiber line, and an electrical transmission data line;

[0015] The transmitting pins and receiving pins of the first QSFP interface are connected to the receiving pins and transmitting pins of the second QSFP interface through a plurality of the optical fiber lines;

[0016] The first electrical transmission interface is connected to the second electrical transmission interface through the electrical transmission data line;

[0017] The clock signal pin and differential transmission signal pins of the first PCIe interface are connected to the transmit pins of the first QSFP interface, its differential receive signal pins are connected to the receive pins of the first QSFP interface, and its non-data signal pins are connected to the first electrical transmission interface;

[0018] The clock signal pin and differential receive signal pins of the second PCIe interface are connected to the receive pins of the second QSFP interface, its differential transmit signal pins are connected to the transmit pins of the second QSFP interface, and its non-data signal pins are connected to the second electrical transmission interface.

[0019] In a possible implementation, in the second PCIe transmission module based on optical communication, the non-data signal pins of the first PCIe interface and the second PCIe interface at least include a reset pin, a wake-up pin, a voltage pin, and a ground pin.

[0020] In a possible implementation, in the second PCIe transmission module based on optical communication, both the first electrical transmission interface and the second electrical transmission interface are USB interfaces;

[0021] The electrical transmission data line is a USB data line.

[0022] In a possible implementation, in the second PCIe transmission module based on optical communication, the first QSFP interface, the first electrical transmission interface, and the first PCIe interface are disposed on a first PCB board.

[0023] In a possible implementation, in the second PCIe transmission module based on optical communication, the second QSFP interface, the second electrical transmission interface, and the second PCIe interface are disposed on a second PCB board.

[0024] The technical solution provided by the present utility model has at least the following beneficial effects:

[0025] By introducing the first DP interface, the second DP interface, the third DP interface, the fourth DP interface, the first optical fiber DP line, and the second optical fiber DP line, or by introducing the first QSFP interface, the second QSFP interface, the first electrical transmission interface, the second electrical transmission interface, the optical fiber line, and the electrical transmission data line, the corresponding pins can be connected correspondingly based on optical fiber transmission and electrical transmission, thereby respectively establishing a high-speed optical fiber transmission channel and a low-speed electrical transmission channel. The data that needs to be transmitted at high speed and over a long distance between the first PCIe interface and the second PCIe interface is transmitted through the optical fiber transmission channel, and other signals are transmitted through the electrical transmission channel, thereby achieving low-cost long-distance high-speed transmission of PCIe data. Description of the Drawings

[0026] Figure 1 The circuit schematic diagram of the first PCIe transmission module based on optical communication provided by the embodiment of the present invention;

[0027] Figure 2 The circuit schematic diagram of the second PCIe transmission module based on optical communication provided by the embodiment of the present invention. Detailed implementation manners

[0028] To deepen the understanding of the present invention, the present invention will be further described in detail below in conjunction with the drawings and embodiments. The embodiments are only used to explain the present invention and do not limit the protection scope of the present invention.

[0029] Please refer to Figure 1 , the first PCIe transmission module based on optical communication provided by the present invention includes a first DP interface, a second DP interface, a third DP interface, a fourth DP interface, a first PCIe interface, a second PCIe interface, a first optical fiber DP line, and a second optical fiber DP line;

[0030] The high-speed signal pins of the first DP interface are connected to the high-speed signal pins of the third DP interface through the optical fiber of the first optical fiber DP line, and its low-speed signal pins are connected to the low-speed signal pins of the third DP interface through the copper wire of the first optical fiber DP line;

[0031] The high-speed signal pins of the second DP interface are connected to the high-speed signal pins of the fourth DP interface through the optical fiber of the second optical fiber DP line, and its low-speed signal pins are connected to the low-speed signal pins of the fourth DP interface through the copper wire of the second optical fiber DP line;

[0032] The clock signal pin CLK1 and the differential transmission signal pins TX1[1:n] of the first PCIe interface are connected to the high-speed signal pins of the first DP interface, its differential reception signal pins RX1[1:n] are connected to the high-speed signal pins of the second DP interface, and its non-data signal pins [RST1, WAKE1,..., V11, V12, GND1] are respectively connected to the low-speed signal pins of the first DP interface and the second DP interface;

[0033] The clock signal pin CLK2 and the differential reception signal pins RX2[1:n] of the second PCIe interface are connected to the high-speed signal pins of the third DP interface, its differential transmission signal pins TX2[1:n] are connected to the high-speed signal pins of the fourth DP interface, and its non-data signal pins [RST2, WAKE2,..., V21, V22, GND2] are respectively connected to the low-speed signal pins of the third DP interface and the fourth DP interface.

[0034] In this embodiment, the first DP interface, the second DP interface, the third DP interface, and the fourth DP interface are conventional DP interfaces. The first PCIe interface and the second PCIe interface are conventional PCIe interfaces. The first optical fiber DP cable and the second optical fiber DP cable are conventional optical fiber DP cables. PCIe transmission is achieved between the first PCIe interface and the second PCIe interface based on optical communication and electrical signals. The high-speed signal pins of the first DP interface, the second DP interface, the third DP interface, and the fourth DP interface are the pins for data transmission through the optical fibers in the optical fiber DP cable, and the low-speed signal pins of the first DP interface, the second DP interface, the third DP interface, and the fourth DP interface are the pins for data transmission through the copper wires in the optical fiber DP cable. The transmission direction of the optical signal in the first optical fiber DP cable is from the side of the first DP interface to the side of the third DP interface. The transmission direction of the optical signal in the second optical fiber DP cable is from the side of the fourth DP interface to the side of the second DP interface.

[0035] In a specific implementation, such as Figure 1 , assuming n = 1, each of the first DP interface, the second DP interface, the third DP interface, and the fourth DP interface includes 2 pairs of optical communication pins and 8 electrical transmission pins, and each of the first optical fiber DP cable and the second optical fiber DP cable includes 2 optical fiber transmission channels (i.e., each includes 4 optical fibers) and 8 electrical transmission channels (such as 8 copper core wires). A specific line connection relationship is as follows: The clock signal pins CLK1 (a total of 2) of the first PCIe interface are sequentially connected to the clock signal pins CLK2 (a total of 2) of the second PCIe interface through the first pair of optical communication pins of the first DP interface, the first optical fiber transmission channel of the first optical fiber DP cable, and the first pair of optical communication pins of the third DP interface. The differential transmission signal pins TX1[1] (a total of 2) of the first PCIe interface are sequentially connected to the differential reception signal pins RX2[1] (a total of 2) of the second PCIe interface through the second pair of optical communication pins of the first DP interface, the second optical fiber transmission channel of the first optical fiber DP cable, and the second pair of optical communication pins of the third DP interface. The differential reception signal pins RX1[1] (a total of 2) of the first PCIe interface are sequentially connected to the differential transmission signal pins TX2[1] (a total of 2) of the second PCIe interface through the first pair of optical communication pins of the second DP interface, the first optical fiber transmission channel of the second optical fiber DP cable, and the first pair of optical communication pins of the fourth DP interface. The non-data signal pins [RST1, WAKE1,..., V11, V12, GND1] of the first PCIe interface are sequentially connected to the non-data signal pins [RST2, WAKE2,..., V21, V22, GND2] of the second PCIe interface through the selected electrical transmission pins in the first DP interface and the second DP interface, the selected electrical transmission channels in the first optical fiber DP cable and the second optical fiber DP cable, and the selected electrical transmission pins in the third DP interface and the fourth DP interface according to the specific quantity.

[0036] By introducing a first DP interface, a second DP interface, a third DP interface, a fourth DP interface, a first optical fiber DP cable, and a second optical fiber DP cable, and connecting the corresponding pins based on optical fiber transmission and electrical transmission, high-speed optical fiber transmission channels and low-speed electrical transmission channels can be established respectively. The data that needs to be transmitted at high speed and over a long distance between the first PCIe interface and the second PCIe interface is transmitted through the optical fiber transmission channel, and other signals are transmitted through the electrical transmission channel, thereby achieving low-cost long-distance high-speed transmission of PCIe data.

[0037] In a possible implementation, in the first PCIe transmission module based on optical communication, the non-data signal pins of the first PCIe interface and the second PCIe interface at least include a reset pin RST, a wake-up pin WAKE, voltage pins [V1, V2], and a ground pin GND.

[0038] In this embodiment, the reset pin RST, the wake-up pin WAKE, the voltage pins [V1, V2], and the ground pin GND are all conventional pins in the PCIe interface. The reset pin RST is used to transmit a reset signal, the wake-up pin WAKE is used to transmit a wake-up signal, the voltage pins [V1, V2] are used to transmit power supply signals (such as V1 = +3.3V and V2 = +12V), and the ground pin GND is used to provide a reference potential.

[0039] In a possible implementation, in the first PCIe transmission module based on optical communication, both the first optical fiber DP cable and the second optical fiber DP cable have a structure of 4-core optical fiber and 8-core copper wire.

[0040] In this embodiment, when both the first optical fiber DP cable and the second optical fiber DP cable have a structure of 4-core optical fiber and 8-core copper wire, there are a total of 8 optical fiber lines and 16 copper wires. Every 2 optical fiber lines in the first optical fiber DP cable form 1 high-speed signal transmission channel, and every 2 optical fiber lines in the second optical fiber DP cable form 1 high-speed signal transmission channel. The 16 copper wires are used to transmit low-speed signals. Thus, 4 high-speed signal transmission channels can be formed to transmit differential signals. It should be noted that not all 4 high-speed signal transmission channels must be used. 2 high-speed signal transmission channels in the first optical fiber DP cable can be used to transmit clock differential signals and a data transmission differential signal respectively, and 1 high-speed signal transmission channel in the second optical fiber DP cable can be used to transmit a data reception differential signal.

[0041] In a possible implementation, in the first PCIe transmission module based on optical communication, the first DP interface, the second DP interface, and the first PCIe interface are arranged on the first PCB board.

[0042] In this embodiment, the first PCB board is a conventional PCB substrate. Since the DP interface and the PCIe interface cannot be directly matched, setting the first DP interface, the second DP interface, and the first PCIe interface on the first PCB board can effectively improve the operation convenience. At the same time, it also helps to prevent misconnection of each component during the connection process.

[0043] In a possible implementation, in the first PCIe transmission module based on optical communication, the third DP interface, the fourth DP interface, and the second PCIe interface are arranged on the second PCB board.

[0044] In this embodiment, the second PCB board is a conventional PCB substrate. Since the DP interface and the PCIe interface cannot be directly matched, setting the third DP interface, the fourth DP interface, and the second PCIe interface on the second PCB board can effectively improve the operation convenience. At the same time, it also helps to prevent misconnection of each component during the connection process.

[0045] Please refer to Figure 2 , the present utility model further provides a second PCIe transmission module based on optical communication, including a first QSFP interface, a second QSFP interface, a first electrical transmission interface, a second electrical transmission interface, a first PCIe interface, a second PCIe interface, an optical fiber line, and an electrical transmission data line;

[0046] The transmitting pins and receiving pins of the first QSFP interface are connected to the receiving pins and transmitting pins of the second QSFP interface through a plurality of the optical fiber lines;

[0047] The first electrical transmission interface is connected to the second electrical transmission interface through the electrical transmission data line;

[0048] The clock signal pin CLK1 and the differential transmission signal pins TX1[1:n] of the first PCIe interface are connected to the transmitting pins of the first QSFP interface, its differential receiving signal pins RX1[1:n] are connected to the receiving pins of the first QSFP interface, and its non-data signal pins [RST1, WAKE1,..., V11, V12, GND1] are connected to the first electrical transmission interface;

[0049] The clock signal pin CLK2 and the differential receiving signal pins RX2[1:n] of the second PCIe interface are connected to the receiving pins of the second QSFP interface, its differential transmitting signal pins TX2[1:n] are connected to the transmitting pins of the second QSFP interface, and its non-data signal pins [RST2, WAKE2,..., V21, V22, GND2] are connected to the second electrical transmission interface.

[0050] In this embodiment, the first QSFP interface and the second QSFP interface are conventional QSFP interfaces, the first electrical transmission interface and the second electrical transmission interface are conventional data interfaces based on electrical transmission (such as composed of single or multiple USB interfaces), the first PCIe interface and the second PCIe interface are conventional PCIe interfaces, the optical fiber line uses a conventional type of optical fiber, and the electrical transmission data line is a conventional data line based on electrical transmission (such as a USB data line, specifically determined according to the first electrical transmission interface and the second electrical transmission interface). PCIe transmission is realized between the first PCIe interface and the second PCIe interface based on optical communication and electrical signals. The first QSFP interface and the second QSFP interface are connected by an optical fiber line, which can realize bidirectional long-distance transmission of high-speed signals, and the first electrical transmission interface and the second electrical transmission interface realize the transmission of low-speed signals based on electrical transmission.

[0051] In a specific implementation manner, such as Figure 2, assume n = 1. The first QSFP interface and the second QSFP interface each include 4 pairs of optical communication pins (2 pairs for transmission and 2 pairs for reception). The first electrical transmission interface and the second electrical transmission interface can select an electrical transmission interface with at least 8 electrical transmission pins (the increase in the number of electrical transmission pins can be achieved by paralleling the same type of electrical transmission interfaces). The number of optical fiber lines includes 4 optical fiber transmission channels (i.e., a total of 8 optical fibers), and the electrical transmission data line selects a data line with at least 8 electrical transmission channels (such as 8 copper core wires, specifically determined according to the first electrical transmission interface and the second electrical transmission interface). A specific line connection relationship is as follows: The clock signal pins CLK1 (a total of 2) of the first PCIe interface are sequentially connected to the clock signal pins CLK2 (a total of 2) of the second PCIe interface through the first pair of optical communication pins for transmission of the first QSFP interface, the first optical fiber transmission channel, and the first pair of optical communication pins for reception of the second QSFP interface. The differential transmission signal pins TX1[1] (a total of 2) of the first PCIe interface are sequentially connected to the differential reception signal pins RX2[1] (a total of 2) of the second PCIe interface through the second pair of optical communication pins for transmission of the first QSFP interface, the second optical fiber transmission channel, and the second pair of optical communication pins for reception of the second QSFP interface. The differential reception signal pins RX1[1] (a total of 2) of the first PCIe interface are sequentially connected to the differential transmission signal pins TX2[1] (a total of 2) of the second PCIe interface through the first pair of optical communication pins for reception of the first QSFP interface, the third optical fiber transmission channel, and the first pair of optical communication pins for transmission of the second QSFP interface. The non-data signal pins [RST1, WAKE1,..., V11, V12, GND1] of the first PCIe interface are sequentially connected to the non-data signal pins [RST2, WAKE2,..., V21, V22, GND2] of the second PCIe interface through the selected electrical transmission pins in the first electrical transmission interface, the selected electrical transmission channels in the electrical transmission data line, and the selected electrical transmission pins in the second electrical transmission interface according to the specific quantity.

[0052] By introducing the first QSFP interface, the second QSFP interface, the first electrical transmission interface, the second electrical transmission interface, the optical fiber lines, and the electrical transmission data line, and connecting the corresponding pins based on optical fiber transmission and electrical transmission, high-speed optical fiber transmission channels and low-speed electrical transmission channels can be established respectively. The data that needs to be transmitted at high speed and over a long distance between the first PCIe interface and the second PCIe interface is transmitted through the optical fiber transmission channel, and other signals are transmitted through the electrical transmission channel, thus realizing the long-distance high-speed transmission of PCIe data at low cost.

[0053] In a possible implementation, in the second PCIe transmission module based on optical communication, the non-data signal pins of the first PCIe interface and the second PCIe interface at least include a reset pin RST, a wake-up pin WAKE, voltage pins [V1, V2], and a ground pin GND.

[0054] In this embodiment, the reset pin RST, the wake-up pin WAKE, the voltage pins [V1, V2], and the ground pin GND are all conventional pins in the PCIe interface. The reset pin RST is used to transmit a reset signal, the wake-up pin WAKE is used to transmit a wake-up signal, the voltage pins [V1, V2] are used to transmit power supply signals (such as V1 = +3.3V and V2 = +12V), and the ground pin GND is used to provide a reference potential.

[0055] In a possible implementation, in the second PCIe transmission module based on optical communication, the first electrical transmission interface and the second electrical transmission interface are both USB interfaces;

[0056] The electrical transmission data line is a USB data line.

[0057] In this embodiment, the USB interface and the USB data line both adopt conventional models. Since the USB interface and the USB data line are widely used and have low costs, applying the USB interface and the USB data line to the PCIe transmission module can effectively reduce the implementation cost of the PCIe transmission module. When there are not enough pins for electrical transmission, the first electrical transmission interface and the second electrical transmission interface can be implemented by connecting multiple USB interfaces in parallel, and the USB data line is increased or decreased according to the number of USB interfaces.

[0058] In a possible implementation, in the second PCIe transmission module based on optical communication, the first QSFP interface, the first electrical transmission interface, and the first PCIe interface are arranged on a first PCB board.

[0059] In this embodiment, the first PCB board is a conventional PCB substrate. Since the first QSFP interface, the first electrical transmission interface, and the first PCIe interface cannot be directly matched, arranging the first QSFP interface, the first electrical transmission interface, and the first PCIe interface on the first PCB board can effectively improve the operation convenience. At the same time, it also helps to prevent incorrect connections during the connection process of each component.

[0060] In a possible implementation, in the second PCIe transmission module based on optical communication, the second QSFP interface, the second electrical transmission interface, and the second PCIe interface are arranged on a second PCB board.

[0061] In this embodiment, the second PCB board is a conventional PCB substrate. Since the second QSFP interface, the second electrical transmission interface, and the second PCIe interface cannot be directly matched, setting the second QSFP interface, the second electrical transmission interface, and the second PCIe interface on the second PCB board can effectively improve the operation convenience. At the same time, it also helps to prevent misconnection of each component during the connection process.

[0062] The above embodiments should not limit the present invention in any way. All technical solutions obtained by means of equivalent replacement or equivalent conversion fall within the protection scope of the present invention.

Claims

1. A PCIe transmission module based on optical communication, characterized in that, It includes a first DP interface, a second DP interface, a third DP interface, a fourth DP interface, a first PCIe interface, a second PCIe interface, a first optical fiber DP cable, and a second optical fiber DP cable; The high-speed signal pins of the first DP interface are connected to the high-speed signal pins of the third DP interface through the optical fiber of the first optical fiber DP cable, and its low-speed signal pins are connected to the low-speed signal pins of the third DP interface through the copper wire of the first optical fiber DP cable; The high-speed signal pins of the second DP interface are connected to the high-speed signal pins of the fourth DP interface through the optical fiber of the second optical fiber DP cable, and its low-speed signal pins are connected to the low-speed signal pins of the fourth DP interface through the copper wire of the second optical fiber DP cable; The clock signal pins and differential transmission signal pins of the first PCIe interface are connected to the high-speed signal pins of the first DP interface, its differential reception signal pins are connected to the high-speed signal pins of the second DP interface, and its non-data signal pins are respectively connected to the low-speed signal pins of the first DP interface and the second DP interface; The clock signal pins and differential reception signal pins of the second PCIe interface are connected to the high-speed signal pins of the third DP interface, its differential transmission signal pins are connected to the high-speed signal pins of the fourth DP interface, and its non-data signal pins are respectively connected to the low-speed signal pins of the third DP interface and the fourth DP interface.

2. The PCIe transmission module according to claim 1, wherein The non-data signal pins of the first PCIe interface and the second PCIe interface at least include reset pins, wake-up pins, voltage pins, and ground pins.

3. The PCIe transmission module according to claim 2, wherein Both the first optical fiber DP cable and the second optical fiber DP cable have a structure of 4-core optical fiber and 8-core copper wire.

4. The PCIe transmission module according to claim 1, wherein The first DP interface, the second DP interface, and the first PCIe interface are provided on a first PCB board.

5. The PCIe transmission module according to claim 1, wherein The third DP interface, the fourth DP interface, and the second PCIe interface are provided on a second PCB board.

6. A PCIe transmission module based on optical communication, characterized in that It includes a first QSFP interface, a second QSFP interface, a first electrical transmission interface, a second electrical transmission interface, a first PCIe interface, a second PCIe interface, an optical fiber cable, and an electrical transmission data cable; The transmit pins and receive pins of the first QSFP interface are connected to the receive pins and transmit pins of the second QSFP interface through a plurality of the optical fiber cables; The first electrical transmission interface is connected to the second electrical transmission interface through the electrical transmission data cable; The clock signal pins and differential transmission signal pins of the first PCIe interface are connected to the transmit pins of the first QSFP interface, its differential reception signal pins are connected to the receive pins of the first QSFP interface, and its non-data signal pins are connected to the first electrical transmission interface; The clock signal pins and differential reception signal pins of the second PCIe interface are connected to the receive pins of the second QSFP interface, its differential transmission signal pins are connected to the transmit pins of the second QSFP interface, and its non-data signal pins are connected to the second electrical transmission interface.

7. The PCIe transmission module according to claim 6, characterized in that, The non-data signal pins of the first PCIe interface and the second PCIe interface at least include a reset pin, a wake-up pin, a voltage pin, and a ground pin.

8. The PCIe transmission module according to claim 7, wherein Both the first electrical transmission interface and the second electrical transmission interface are USB interfaces; The electrical transmission data line is a USB data line.

9. The PCIe transmission module according to claim 6, wherein The first QSFP interface, the first electrical transmission interface, and the first PCIe interface are disposed on a first PCB board.

10. The PCIe transmission module according to claim 6, wherein, The second QSFP interface, the second electrical transmission interface, and the second PCIe interface are disposed on a second PCB board.

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