Fan-out wafer level packaging unit

Abstract

The utility model discloses a fan-out type wafer-level packaging unit. The fan-out type wafer-level packaging unit comprises a carrier plate, at least two bare chips, a first dielectric layer, a second dielectric layer, a plurality of conducting circuits, at least two first welding pads, at least one first welding wire and an outer protective layer, wherein the dies are electrically connected with each other through the first bonding wires; wherein each conducting circuit is formed by metal paste filled in each first groove of the first dielectric layer and each second groove of the second dielectric layer, and a second welding pad is formed in each opening of the outer protective layer; wherein each bare crystal can be electrically connected with the outside through each second welding pad around the chip area on the second surface of each bare crystal, so that the problems that the manufacturing cost is high and the environmental protection is not facilitated when each conducting circuit is manufactured by the existing fan-out type packaging technology are effectively solved.

Description

Technical Field

[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art

[0002] The development trend of the semiconductor industry is towards thin, light, short, and small packaging technologies with high efficiency and high reliability. Among them, fan-out wafer-level packaging (FOWLP) is an existing packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most critical. Because the conductive lines in the RDL can cause the XY-plane electrical extension and interconnection of multiple pads on the bare die, so that a plurality of pads can be formed more dispersedly around each bare die, thereby effectively improving the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of thin, light, short, and small effect while generating the XY-plane electrical extension and interconnection effect is the most critical for the production of each conductive line in the RDL. However, the forming method of each conductive line in the RDL technology applied in the existing FOWLP packaging technology is to use chemical plating forming technology or electroplating forming technology for production. In this way, in addition to the relatively high material cost and production cost, the existing processes also do not meet or are not conducive to environmental protection requirements.

[0004] In addition, when the FOWLP is used to provide products with higher performance or more functions, generally, at least two or more bare dies are arranged in the FOWLP and integrated through the RDL to form a multi-chip type fan-out wafer-level packaging unit. At this time, the demand for the design space of each conductive line in the RDL of the FOWLP will increase relatively, and the manufacturing technology of each conductive line in the RDL is also relatively more critical.

[0005] Furthermore, in the existing multi-chip type fan-out wafer-level packaging unit, there is a lack of an effective electrical connection method between at least two or more bare dies arranged inside, resulting in the disadvantage that the existing products have limited usage functions and are not conducive to meeting the more diverse market demands in the future. Summary of the Utility Model

[0006] The main purpose of the present utility model is to provide a fan-out wafer-level packaging unit, which includes a carrier plate, at least two bare dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, at least two first pads, at least one first bonding wire, and an outer protective layer; wherein each bare die is electrically connected to each other through each first bonding wire; wherein each conductive line is formed by metal paste filled in each first groove of the first dielectric layer and each second groove of the second dielectric layer, and second pads are formed in each opening of the outer protective layer; wherein each bare die can be externally electrically connected through each second pad located around the chip area on the second surface of each bare die, effectively solving the problems that the existing fan-out packaging technology is prone to high manufacturing costs and is not environmentally friendly when manufacturing each conductive line.

[0007] To achieve the above object, the present utility model provides a fan-out wafer-level packaging unit, which includes a carrier plate, at least two bare dies (Dies), a first dielectric layer, a second dielectric layer, a plurality of conductive lines, at least two first pads, at least one first wire, and an outer protective layer; wherein each of the bare dies is divided from the same wafer (Wafer) or different wafers, each of the bare dies is arranged side by side on the carrier plate in parallel and at intervals, each of the bare dies has a first surface and a second surface opposite thereto, the first surface of each of the bare dies is fixedly arranged on the carrier plate, a plurality of die pads are provided on the second surface of each of the bare dies, and the vertical chip area of the second surface is defined as a chip area; wherein the first dielectric layer is arranged on the carrier plate and the second surface of each of the bare dies, the first dielectric layer has a plurality of first grooves formed by extending in the horizontal direction, and each of the die pads of each of the bare dies is exposed to the outside by the plurality of first grooves; wherein the second dielectric layer is arranged on the first dielectric layer, the second dielectric layer has a plurality of second grooves formed by extending in the horizontal direction, and the plurality of second grooves communicate with the plurality of first grooves; wherein each of the conductive lines is composed of a metal paste filled in the plurality of first grooves and the plurality of second grooves, and each of the conductive lines is electrically connected to each of the die pads of each of the bare dies; wherein each of the first pads is formed on two corresponding conductive lines in each of the bare dies respectively; wherein each of the first wires is formed with a first solder joint and a second solder joint on each of the first pads in each of the bare dies through a wire bonding operation, so that each of the bare dies can be electrically connected through each of the first wires; wherein the outer protective layer is arranged on the second dielectric layer and covers each of the first pads and each of the first wires, the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip area on the second surface of each of the bare dies, each of the conductive lines can be exposed to the outside through each of the openings, each of the conductive lines forms a second pad in each of the openings by being exposed to the outside through each of the openings, and each of the bare dies can be electrically connected to the outside in sequence through the die pads, the conductive lines, and the second pads located around the chip area on the second surface of the bare die, so as to form the fan-out wafer-level packaging unit; wherein each of the bare dies in the fan-out wafer-level packaging unit is electrically connected to each other through each of the first wires.

[0008] In a preferred embodiment of the present utility model, each of the bare dies can be electrically connected to the first pads of other bare dies in sequence through the die pads, the conductive lines, and the first wires on the first pads located around the chip area on the second surface of the bare die.

[0009] In a preferred embodiment of the present utility model, each of the bare dies is divided from the same or different wafers.

[0010] In a preferred embodiment of the present utility model, the horizontal heights of the second surfaces between each of the bare dies on the carrier are the same.

[0011] In a preferred embodiment of the present utility model, the carrier includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0012] In a preferred embodiment of the present utility model, the metal paste includes silver paste, nano silver paste, copper paste, or nano copper paste.

[0013] In a preferred embodiment of the present utility model, the first surface of each of the bare dies is further disposed on the carrier by using a die attach film (DAF).

[0014] In a preferred embodiment of the present utility model, a solder ball is further disposed on each of the openings, and each of the solder balls can be electrically connected to each of the second pads in each of the openings.

[0015] In a preferred embodiment of the present utility model, the fan-out wafer-level packaging unit can be disposed on an electronic component in an electrically connected manner by using each of the solder balls. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic side cross-sectional view of the fan-out wafer-level packaging unit of the present utility model disposed on a printed circuit board.

[0017] Figure 2 is a schematic side cross-sectional view of the bare die of the present utility model disposed on the carrier.

[0018] Figure 3 is a schematic side cross-sectional view of the first dielectric layer of the present utility model disposed on the second surfaces of the carrier and the bare die.

[0019] Figure 4 is a schematic side cross-sectional view of the second dielectric layer of the present utility model disposed on the first dielectric layer.

[0020] Figure 5 is a schematic side cross-sectional view of the first groove and the second groove of the present utility model filled with metal paste.

[0021] Figure 6 is Figure 5 a schematic side cross-sectional view of the metal paste higher than the surface of the second dielectric layer in

[0022] Figure 7 is a schematic side cross-sectional view of the wire bonding operation of the present utility model.

[0023] Figure 8It is a schematic side cross-sectional view of the outer protective layer of the present utility model forming a plurality of openings.

[0024] Figure 9 It is a schematic side cross-sectional view of the fan-out type wafer-level packaging unit of the present utility model.

[0025] Figure 10 It is a schematic side cross-sectional view of another embodiment of the fan-out type wafer-level packaging unit of the present utility model.

[0026] Explanation of reference numerals: 1 - fan-out type wafer-level packaging unit; 1a - chip area; 10 - carrier plate; 20 - bare die; 20a - first bare die; 20b - second bare die; 21 - first surface; 22 - second surface; 23 - pad; 30 - first dielectric layer; 31 - first groove; 40 - second dielectric layer; 41 - second groove; 50 - connection line; 50a - metal paste; 51 - second pad; 60 - first pad; 70 - first bonding wire; 71 - first solder joint; 72 - second solder joint; 80 - outer protective layer; 81 - opening; 90 - chip bonding film; 100 - solder ball; 2 - electronic component. Detailed description of the specific implementation

[0027] In conjunction with the drawings, the structure and its technical features of the present utility model will be described in detail as follows. Each drawing is only used to illustrate the structural relationship and related functions of the present utility model. Therefore, the dimensions of each component in each drawing are not drawn according to the actual ratio and are not used to limit the present utility model.

[0028] Refer to Figure 8 , the present utility model provides a fan-out type wafer-level packaging unit 1, which includes a carrier plate 10, at least two bare dies (Die) 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of connection lines 50, at least two first pads 60, at least one first bonding wire 70 and an outer protective layer 80.

[0029] The carrier plate 10 includes a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate, but is not limited to, as Figure 2 shown.

[0030] Each bare die 20 is divided from the same wafer or different wafers. Each bare die 20 is arranged side by side on the carrier plate 10 in parallel and at intervals. Each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is fixedly arranged on the carrier plate 10. A plurality of pads 23 are provided on the second surface 22 of each bare die 20, and the vertical chip area of the second surface 22 is defined as a chip area 1a, as Figure 2 shown. In Figure 2 , two pads 23 are taken as an example for each pad 23 of each bare die 20, but it is not used to limit the present utility model.

[0031] In addition, in order to illustrate the structural relationship and related functions of the present utility model, in the embodiment shown in the present utility model, each bare die 20 on the carrier plate 10 further includes a first bare die 20a and a second bare die 20b, but it is not limited. That is, two bare dies 20 are taken as an example for illustration, but it is not used to limit the present utility model. Figures 1 to 9 The first dielectric layer 30 is disposed on the second surface 22 of the carrier plate 10 and each bare die 20 (the first bare die 20a and the second bare die 20b). The first dielectric layer 30 has a plurality of first grooves 31 formed by extending horizontally, as

[0032] shown; wherein each pad 23 of each bare die 20 (the first bare die 20a and the second bare die 20b) is exposed to the outside through each first groove 31, as Figure 3 shown. Figure 3 shown.

[0033] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 formed by extending horizontally. Each second groove 41 communicates with each first groove 31, as Figure 4 shown.

[0034] Each conductive line 50 is composed of a metal paste 50a filled in each first groove 31 and each second groove 32. Each conductive line 50 is electrically connected to each pad 23 of each bare die 20 (the first bare die 20a and the second bare die 20b), as Figure 6 shown; wherein the metal paste 50a includes silver paste, nano - silver paste, copper paste or nano - copper paste but is not limited. The above - mentioned nano - silver paste material has characteristics such as low cost, high conductivity and the ability to sinter at low temperature. However, since the nano - silver paste material is a common existing material, it will not be elaborated here.

[0035] Two corresponding first pads 60 are respectively formed on two of the conductive lines 50 in each bare die 20 (the first bare die 20a and the second bare die 20b), as Figure 7 shown. Each first pad 60 further bears the positive pressure generated during the wire bonding operation or the formation of solder joints, so that the internal circuit will not be damaged by the positive pressure, and the internal circuit (such as each conductive line 50) can be allowed to pass through or be arranged below each first pad 60.

[0036] Each first bonding wire 70 is subjected to a wire bonding operation to form a first solder joint 71 and a second solder joint 72 on each first pad 60 in each bare die 20 (the first bare die 20a and the second bare die 20b), so that each bare die 20 (the first bare die 20a and the second bare die 20b) can be electrically connected through each first bonding wire 70, asFigure 7 as shown

[0037] In addition, in order to illustrate the structural relationship and related functions of the present utility model, in the embodiment Figure 1 shown, the solder joints on the first bare die 20a are the first solder joints 71 but are not limited thereto, and the solder joints on the second bare die 20b are the second solder joints 72 but are not limited thereto. That is, one first bonding wire 70 is taken as an example for illustration, but it is not used to limit the present utility model.

[0038] The outer protective layer 80 is disposed on the second dielectric layer 40 and covers each first pad 60 and each first bonding wire 70. The outer protective layer 80 has a plurality of openings 81, and at least two of the openings 81 are located around the chip region 1a on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b), as Figure 8 shown; wherein each conductive line 50 can be exposed to the outside through each opening 81, as Figure 8 shown; wherein each conductive line 50 is exposed to the outside through each opening 81 and a second pad 51 is formed in each opening 81, as Figure 8 shown; wherein each bare die 20 (the first bare die 20a and the second bare die 20b) can be electrically connected to the outside in sequence through each pad 23, each conductive line 50, and each second pad 51 located around the chip region 1a on the second surface 22 of each bare die 20 (the first bare die 20a and the second bare die 20b), thereby forming the fan-out wafer-level packaging unit 1, as Figure 8 shown.

[0039] Each bare die 20 (the first bare die 20a and the second bare die 20b) in the fan-out wafer-level packaging unit 1 is electrically connected to each other through each first bonding wire 70, as Figure 8 shown.

[0040] The process of manufacturing the fan-out wafer-level packaging unit 1 may include the following steps, but is not limited thereto:

[0041] Step S1: Provide a carrier 10, as Figure 2 shown.

[0042] Step S2: Arrange a plurality of bare dies (Dies) 20 divided from the same wafer or different wafers in parallel and spaced side by side on the carrier 10, as Figure 2 shown; wherein each bare die 20 has a first surface 21 and a second surface 22 opposite thereto. The first surface 21 of each bare die 20 is disposed on the carrier 10, and a plurality of pads 23 are provided on the second surface 22 of each bare die 20, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as Figure 2 shown.

[0043] Step S3: Lay a first dielectric layer 30 on the second surface 22 of the carrier board 10 and each bare die 20, as Figure 3 shown.

[0044] Step S4: Form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, and expose each pad 23 of each bare die 20 through each first groove 31, as Figure 3 shown.

[0045] Step S5: Lay a second dielectric layer 40 on the first dielectric layer 30, as Figure 4 shown.

[0046] Step S6: Form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, and make each second groove 41 communicate with each first groove 31, as Figure 4 shown.

[0047] Step S7: Inject a metal paste 50a into each first groove 31 and each second groove 41, and make the thickness of the metal paste 50a higher than the surface of the second dielectric layer 40, as Figure 5 shown.

[0048] Step S8: Grind the metal paste 50a higher than the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of connection lines 50, as Figure 6 shown.

[0049] Step S9: Form a first pad 60 on each connection line 50 in each bare die 20, and each first pad 60 is correspondingly arranged on each connection line 50 in two, as Figure 7 shown.

[0050] Step S10: Perform a wire bonding operation so that at least one first wire 70 forms a first solder joint 71 and a second solder joint 72 on each first pad 60 in each bare die 20 respectively, as Figure 7 shown; wherein each bare die 20 is electrically connected through each first wire 70, as Figure 7 shown.

[0051] Step S11: Provide an outer protective layer 80 on the second dielectric layer 40, and make the outer protective layer 80 cover each first pad 60 and each first wire 70, as Figure 8 shown.

[0052] Step S12: Form a plurality of openings 81 in the outer protective layer 80, and make at least one of the openings 81 formed around the chip region 1a on the second surface 22 of each bare die 20, so that each conductive line 50 can be exposed to the outside through each opening 81 to form a second solder pad 51 in each opening, as Figure 8 shown.

[0053] Step S13: Perform a dicing operation and dice to form a plurality of fan-out wafer-level packaging units 1 in units of one package having at least two of the bare dies 20, as Figure 8 shown.

[0054] The processes of steps S3 to S9 and step S12 in the above process of manufacturing the fan-out wafer-level packaging unit 1 can be regarded as key steps in fabricating the redistribution layer (RDL, Redistribution Layer) of the fan-out wafer-level packaging unit 1. Among them, step S4 is to form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, step S6 is to form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, step S7 is to inject a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, and step S8 is to grind the metal paste 50a higher than the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive lines 50. Since steps S4 to S8 are all processes that are easy to implement precisely, the process is relatively simplified, which is sufficient to enable each conductive line 50 in the redistribution layer to generate XY-plane electrical extension and interconnection effects, and at the same time enable the fabricated fan-out wafer-level packaging unit 1 to still maintain or achieve a certain degree of thin, light, short, and small specific effects, and in the case where there are at least two of the bare dies 20 in the fan-out wafer-level packaging unit 1, still maintain or achieve a certain degree of thin, light, short, and small effects.

[0055] Refer to Figure 10 , each bare die 20 can be electrically connected to each first solder pad 60 of other bare dies 20 in sequence through each chip pad 23, each conductive line 50, and each first bonding wire 70 on each first solder pad 60 around the chip region 1a on the second surface 22 of each bare die 20, but not limited thereto. For example, the first bare die 20a can be electrically connected to the second bare die 20b through each first bonding wire 70.

[0056] Refer to Figure 2 , when each bare die 20 is diced from the same wafer, each bare die 20 is a bare die with the same specifications, performance, or intended functions, but not limited thereto.

[0057] Refer to Figure 2, when each bare die 20 is formed by dividing from different wafers, it is beneficial to increase the diversified applications of the product. Each bare die 20 can be a bare die with different specifications, performance, or functions to be achieved, but it is not limited. For example, Figure 2 the specification of the first bare die 20a in

[0058] Reference Figure 2 , the horizontal heights of the second surfaces 22 of each bare die 20 on the carrier 10 are the same, but it is not limited. So that the first grooves 31 of the first dielectric layer 30 and the second grooves 41 of the second dielectric layer 40 formed by the RDL technology later can be smoothly extended and formed, which is helpful for the subsequent structures stacked on each bare die 20 to maintain better structural flatness and increase the reliability of the product.

[0059] Reference Figure 2 , the first surface 21 of each bare die 20 is further disposed on the carrier by a die attach film (DAF), but it is not limited.

[0060] Reference Figure 9 , a solder ball 100 is further provided on each opening 81, but it is not limited. Each solder ball 100 can be electrically connected to each second pad 51 in each opening 81; wherein the fan-out wafer-level packaging unit 1 can be electrically connected and disposed on an electronic component 2 by using each solder ball 100, but it is not limited. For example, Figure 1 as shown; wherein the electronic component 2 is a printed circuit board (PCB), but it is not limited. For example, Figure 1 as shown.

[0061] Compared with the existing fan-out wafer-level packaging unit, the fan-out wafer-level packaging unit 1 of the present utility model has the following advantages:

[0062] (1) During the process of manufacturing the fan-out wafer-level packaging unit 1 of the present utility model, steps S3 to S9 and step S12, compared with the related manufacturing technologies of the existing fan-out wafer-level packaging unit, when manufacturing the present utility model, through the production of each conductive line in the RDL, each conductive line in the RDL can have the XY-plane electrical extension and interconnection effects, and at the same time can also maintain or achieve a certain degree of thin, light, short, and small effects. These are all simplified and easily precisely implemented steps, especially beneficial for reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present utility model is not only more simplified and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer-level packaging unit 1.

[0063] (2) In the forming process of each conductive connection line 50 of the present utility model, the metal paste 50a can be first filled into each first groove 31 and each second groove 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, as Figure 5 shown. Then, the metal paste 50a higher than the surface of the second dielectric layer 40 is ground so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each conductive connection line 50, as Figure 6 shown. Therefore, manufacturing the present utility model can effectively solve the problems of high manufacturing cost and environmental unfriendliness that are prone to occur in the existing fan-out packaging technology when manufacturing each conductive connection line.

[0064] (3) Each bare die 20 of the present utility model can be electrically connected externally in sequence through each pad 23, each conductive connection line 50 (formed by RDL technology), and each pad 51 around the chip area 1a on the second surface 22 of each bare die 20. That is, in the state where each conductive connection line in RDL generates XY-plane electrical extension and interconnection effects, it can also enable the fan-out wafer-level packaging unit in a multi-chip form to maintain or achieve a certain degree of thin, light, short, and small integration effect, so as to provide a product with higher performance (such as each bare die 20 is a bare die with the same specifications, performance, or intended functions) or more functions (such as each bare die 20 is a bare die with different specifications, performance, or intended functions), increasing the market competitiveness of the product.

[0065] (4) Each bare die 20 of the present utility model can be more electrically connected to each first pad 60 on each other bare die 20 in sequence through each pad 23, each conductive connection line 50, and each first bonding wire 70 on each first pad 60 around the chip area 1a on the second surface 22 of each bare die 20. However, it is not limited. For example, the first bare die 20a can be electrically connected to the second bare die 20b through each first bonding wire 70, effectively solving the problem of the lack of an effective electrical connection method between bare dies in the existing fan-out wafer-level packaging unit in a multi-chip form, so as to increase the more diversified applications of the product, which is beneficial to increasing the market competitiveness of the product.

[0066] The above is only the preferred embodiment of the present utility model, which is illustrative rather than restrictive to the present utility model; those of ordinary skill in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the present utility model, but all will fall within the protection scope of the present utility model.

Claims

1. A fan-out wafer-level packaging unit, characterized in that Comprising: A carrier board; At least two bare dies, each of which is separated from the same wafer or different wafers. Each bare die is arranged side by side on the carrier board in parallel and at intervals. Each bare die has a first surface and a second surface opposite thereto. The first surface of each bare die is fixedly provided on the carrier board. There are a plurality of pads on the second surface of each bare die, and the vertical chip area of the second surface is defined as a chip area; A first dielectric layer, which is provided on the carrier board and the second surface of each bare die. The first dielectric layer has a plurality of first grooves formed by extending in the horizontal direction; wherein each pad of each bare die is exposed through a plurality of the first grooves; A second dielectric layer, which is provided on the first dielectric layer. The second dielectric layer has a plurality of second grooves formed by extending in the horizontal direction. The plurality of second grooves communicate with the plurality of first grooves; A plurality of conductive lines, each of which is composed of a metal paste filled in the plurality of first grooves and the plurality of second grooves. Each conductive line is electrically connected to each pad of each bare die; At least two first pads, each of which is formed on two corresponding conductive lines in each bare die respectively; At least one first bonding wire, each of which is subjected to a wire bonding operation to form a first solder joint and a second solder joint on each first pad in each bare die respectively, so that each bare die can form an electrical connection through each first bonding wire; and An outer protective layer, which is provided on the second dielectric layer and covers each first pad and each first bonding wire. The outer protective layer has a plurality of openings, and at least two of the openings are located around the chip area on the second surface of each bare die; Wherein each conductive line can be exposed through each opening; wherein each conductive line forms a second pad in each opening by being exposed through each opening; wherein each bare die can be electrically connected externally in sequence through the pad, the conductive line, and the second pad located around the chip area on the second surface of the bare die, thereby forming the fan-out wafer-level packaging unit; Wherein each bare die in the fan-out wafer-level packaging unit is electrically connected to each other through each first bonding wire.

2. The fan-out wafer-level packaging unit according to claim 1, wherein Each bare die can be electrically connected to the first pad on the first bonding wire of other bare dies in sequence through the pad, the conductive line, and the chip area on the second surface of the bare die.

3. The fan-out wafer-level packaging unit according to claim 1, wherein, Each bare die is formed by separating from the same or different wafers.

4. The fan-out wafer-level packaging unit according to claim 1, wherein The horizontal height of each second surface between each bare die on the carrier board is the same.

5. The fan-out wafer-level packaging unit according to claim 1, wherein The carrier board includes a silicon carrier board, a glass carrier board, or a ceramic carrier board.

6. The fan-out type wafer-level packaging unit according to claim 1, wherein The metal paste includes silver paste, nano silver paste, copper paste, or nano copper paste.

7. The fan-out wafer-level packaging unit as claimed in claim 1, wherein The first surface of each bare die is arranged on the carrier board by using a chip bonding film.

8. The fan-out wafer-level packaging unit according to claim 1, wherein A solder ball is further provided on each opening, and each solder ball can be electrically connected to each second pad in each opening.

9. The fan-out type wafer-level packaging unit according to claim 8, wherein The fan-out wafer-level packaging unit is disposed on an electronic component in an electrically connected manner by each of the solder balls.

Images