Balancing and sampling interlocking circuit, battery management system and energy storage equipment

Abstract

The utility model discloses a balancing and sampling interlocking circuit, a battery management system and energy storage equipment. In the equalization and sampling interlocking circuit, each processing unit is electrically connected between the controller and the corresponding battery monomer, and in the processing unit, a sampling switch is electrically connected between the corresponding sampling end and the corresponding battery monomer; each equalization switch is electrically connected between one corresponding equalization end and one corresponding battery monomer; the sampling switch is electrically connected with the equalization end; and the controller is configured to control the sampling switch to be switched on and switched off through the equalization end, sample parameters of the single batteries through the sampling end, and control the sampling switch to be switched off and the equalization switch to be switched on through the equalization end, so that the equalization circuit equalizes the first single battery. According to the balancing and sampling interlocking circuit, the universality can be improved.

Description

Technical Field

[0001] The utility model relates to the technical field of battery management, in particular to a balancing and sampling interlock circuit, a battery management system and an energy storage device. Background Art

[0002] In the related art, during the operation of a battery management system, the voltage sampling accuracy of battery cells is affected by whether balancing is enabled. However, currently, the solution to avoid simultaneous balancing and sampling is usually to achieve the time-sharing operation of balancing and sampling through software task scheduling, which has high requirements for the quality of the controller and low universality. Summary of the Utility Model

[0003] The embodiments of the utility model provide a balancing and sampling interlock circuit, a battery management system and an energy storage device to solve at least one of the above technical problems.

[0004] A balancing and sampling interlock circuit according to an embodiment of the utility model is used for an energy storage device, the energy storage device includes a plurality of battery cells, and the balancing and sampling interlock circuit includes:

[0005] A controller, the controller includes a plurality of sampling terminals and a plurality of balancing terminals;

[0006] A plurality of processing units, each processing unit is electrically connected between the controller and a corresponding one of the battery cells;

[0007] The processing unit includes a balancing circuit and a sampling circuit, the sampling circuit includes a sampling switch, and the sampling switch is electrically connected between a corresponding one of the sampling terminals and a corresponding one of the battery cells; the balancing circuit includes a balancing switch, and the balancing switch is electrically connected between a corresponding one of the balancing terminals and a corresponding one of the battery cells; the sampling switch is electrically connected to the balancing terminal;

[0008] The controller is configured to control the sampling switch to conduct and the balancing switch to disconnect through the balancing terminal and sample the parameters of the battery cell through the sampling terminal, and control the sampling switch to disconnect and the balancing switch to conduct through the balancing terminal to enable the balancing circuit to balance the first battery cell.

[0009] For the above-mentioned balancing and sampling interlock circuit, the controller can control the sampling switch and the balancing switch not to conduct simultaneously, thereby avoiding the simultaneous execution of the balancing operation and voltage sampling, reducing the interference to voltage sampling, and improving the accuracy of voltage sampling. At the same time, the above-mentioned balancing and sampling interlock circuit avoids the simultaneous execution of the balancing operation and voltage sampling by controlling the conduction and disconnection of the switch, and has relatively low requirements for the controller, thereby improving the system robustness. In addition, compared with the related art in which the time-division operation of balancing and sampling is achieved through software task scheduling, the above-mentioned balancing and sampling interlock circuit is designed from the underlying hardware circuit to ensure that the balancing operation and the sampling operation do not occur simultaneously and reduce the workload of the battery management system.

[0010] In some embodiments, each processing unit includes a control resistor, and the control resistor is electrically connected between a corresponding balancing terminal and the ground;

[0011] The control resistor is configured to control the sampling switch to conduct and the balancing switch to disconnect.

[0012] In some embodiments, the balancing circuit includes a balancing resistor, and the balancing resistor is electrically connected between the balancing switch and a corresponding one of the battery cells;

[0013] The controller is configured to control the sampling switch to disconnect and the balancing switch to conduct through the balancing terminal so that the balancing resistor balances the first battery cell.

[0014] In some embodiments, the sampling circuit includes a filtering circuit, and the filtering circuit is electrically connected between the sampling terminal and the sampling switch.

[0015] In some embodiments, the filtering circuit includes a filtering resistor and a filtering capacitor. The filtering resistor is electrically connected between the sampling switch and the sampling terminal; the filtering capacitor is electrically connected between the filtering resistor and the ground.

[0016] In some embodiments, the processing unit includes a current-limiting resistor, and the current-limiting resistor is electrically connected to the balancing terminal.

[0017] In some embodiments, the balancing and sampling interlock circuit includes a plurality of electromagnetic interference-resistant capacitors, and the electromagnetic interference-resistant capacitors are electrically connected between the ground and a corresponding one of the battery cells.

[0018] In some embodiments, the balancing switch includes an N-type metal oxide field effect transistor, and the sampling switch includes a P-type metal oxide field effect transistor.

[0019] In some embodiments, when the controller outputs a low level, the balancing switch disconnects and the sampling switch conducts;

[0020] When the controller outputs a high level, the equalization switch is turned on and the sampling switch is turned off.

[0021] A battery management system according to an embodiment of the present invention includes the equalization and sampling interlock circuit in the above embodiment.

[0022] An energy storage device according to an embodiment of the present invention includes a plurality of battery cells and the battery management system in the above embodiment, and the battery management system is electrically connected to the plurality of battery cells.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 is a module schematic diagram of the equalization and sampling interlock circuit according to an embodiment of the present invention;

[0026] Figure 2 is a circuit diagram of the equalization and sampling interlock circuit according to an embodiment of the present invention;

[0027] Figure 3 is a circuit diagram of another equalization and sampling interlock circuit according to an embodiment of the present invention.

[0028] Description of the Main Element Reference Numerals:

[0029] Controller 1, processing unit 2, positive line 31 of the DC bus, negative line 32 of the DC bus, battery cell 10, sampling circuit 21, equalization circuit 22. Detailed Embodiments

[0030] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the embodiments of the present invention and should not be construed as limiting the embodiments of the present invention.

[0031] Please refer Figure 1, the present utility model provides a balancing and sampling interlock circuit for an energy storage device, which includes a plurality of battery cells. The balancing and sampling interlock circuit includes: a controller 1 and a plurality of processing units 21. The controller 1 includes a plurality of sampling terminals VB and a plurality of balancing terminals DB. Each processing unit 2 is electrically connected between the controller 1 and a corresponding battery cell 10.

[0032] The processing unit 2 includes a balancing circuit 22 and a sampling circuit 21. The sampling circuit 21 includes a sampling switch QC, and the sampling switch QC is electrically connected between a corresponding sampling terminal VB and a corresponding battery cell 10; the balancing circuit 22 includes a balancing switch QB, and the balancing switch QB is electrically connected between a corresponding balancing terminal DB and a corresponding battery cell 10; the sampling switch QC is electrically connected to the balancing terminal DB.

[0033] The controller 1 is configured to control the sampling switch QC to conduct and the balancing switch QB to disconnect through the balancing terminal DB and sample the parameters of the battery cell 10 through the sampling terminal VB, and control the sampling switch QC to disconnect and the balancing switch QB to conduct through the balancing terminal DB so that the balancing circuit 22 balances the first battery cell.

[0034] Specifically, the balancing and sampling interlock circuit is a circuit for a Battery Management System (BMS), aiming to ensure that the voltage sampling of the battery and the balancing operation of the battery do not occur simultaneously. The balancing and sampling interlock circuit includes a controller 1 and a plurality of processing units 2, and each processing unit 2 includes a balancing circuit 22 and a sampling circuit 21. The sampling circuit 21 is electrically connected between the sampling terminal VB of the controller 1 and the battery cell 10 through the sampling switch QC, and the balancing circuit 22 is electrically connected between the balancing terminal DB of the controller 1 and the battery cell 10 through the balancing switch QB. The controller 1 is responsible for coordinating the conduction and disconnection of the sampling switch QC and the balancing switch QB, so as to realize the interlock operation of sampling and balancing.

[0035] In the battery management system, accurate voltage sampling is crucial for the monitoring and management of the battery state. However, when the balancing operation is turned on, a balancing resistor RB is incorporated at both ends of the battery cell 10. Due to the internal resistance of the battery cell 10, the voltage at both ends of the battery cell 10 will change due to the incorporated balancing resistor RB, thereby interfering with the voltage sampling accuracy of the battery cell 10 and affecting the accurate monitoring of the battery state. Therefore, in order to ensure the accuracy of voltage sampling, it is necessary to avoid the simultaneous occurrence of the balancing operation and the sampling operation. The balancing and sampling interlock circuit ensures that the balancing operation stops when voltage sampling is performed, and vice versa, by controlling the conduction and disconnection of the sampling switch QC and the balancing switch QB, thereby ensuring the accuracy of voltage sampling and the effectiveness of battery balancing.

[0036] The battery management system can be applied to energy storage devices including but not limited to. In one embodiment, the energy storage device includes a plurality of battery cells 10, and the plurality of battery cells 10 can be connected in series or in a series-parallel combination. Series-parallel combination means that there are both parallel and series connections among the plurality of battery cells 10.

[0037] Specifically, the controller 1 can be a battery analog front end (AFE, Analog Front End). When the difference between the parameters of all battery cells 10 and the minimum parameter is less than a preset value, the controller 1 controls the sampling switch QC to conduct through the equalization terminal DB, and at the same time controls the equalization switch QB to disconnect, and samples the voltage of the battery cell 10 through the sampling terminal VB.

[0038] When the energy storage device is in the charging state and it is detected that the difference between the parameters of the first battery cell and the minimum parameter is greater than or equal to the preset value, the controller 1 controls the sampling switch QC to disconnect through the equalization terminal DB, and at the same time controls the equalization switch QB to conduct, so that the equalization circuit 22 performs an equalization operation on the first battery cell. During the whole process, the controller 1 ensures that the sampling switch QC and the equalization switch QB do not conduct simultaneously, thus realizing the interlock between the equalization operation and the voltage sampling.

[0039] The first battery cell is the battery cell 10 corresponding to the difference between the parameter and the minimum parameter being greater than or equal to the preset difference. In one embodiment, the parameter can be a voltage parameter. When the energy storage device is in the charging state, the controller collects the voltage parameters of all battery cells 10 through the sampling terminal. Exemplarily, the preset value can be 5 mV to 20 mV. If the difference between the voltage parameters of one or several battery cells 10 and the minimum voltage parameter is greater than or equal to the preset value, then this or these battery cells 10 are the first battery cells.

[0040] Optionally, in one embodiment, the controller 1 is configured to control the sampling switch QC to conduct and the equalization switch QB to disconnect through the equalization terminal DB and sample the parameters of the battery cell 10 through the sampling terminal VB. When the energy storage device is in the discharging state and the difference between the parameters of the first battery cell and the minimum parameter is greater than or equal to the preset value, the controller controls the sampling switch QC to disconnect and the equalization switch QB to conduct through the equalization terminal DB so that the equalization circuit 22 performs equalization on the first battery cell.

[0041] Specifically, in the above embodiment, the parameter can be a voltage parameter. When the energy storage device is in the discharging state, the controller collects the voltage parameters of all battery cells 10 through the sampling terminal. Exemplarily, the preset value can be 5 mV to 20 mV. If the difference between the voltage parameters of one or several battery cells 10 and the maximum voltage parameter is greater than or equal to the preset value, then this or these battery cells 10 are the first battery cells.

[0042] In the above-mentioned balancing and sampling interlocking circuit, the controller 1 can control the sampling switch QC and the balancing switch QB not to be turned on at the same time, thereby avoiding the balancing operation and voltage sampling to be performed at the same time, reducing the interference to the voltage sampling, and improving the accuracy of the voltage sampling. At the same time, the above-mentioned balancing and sampling interlocking circuit avoids the balancing operation and voltage sampling to be performed at the same time by controlling the on and off of the switch, and has lower requirements on the controller 1, thereby improving the robustness of the system. In addition, compared with the related art that realizes the staggered operation of balancing and sampling through software task scheduling, the above-mentioned balancing and sampling interlocking circuit is designed from the bottom hardware circuit to ensure that the balancing operation and the sampling operation will not occur at the same time and reduce the workload of the battery management system.

[0043] Optionally, when the energy storage device is in a charging state, the controller 1 is configured to control the sampling switch QC to be disconnected and the balancing switch QB to be turned on through the balancing terminal DB so that the balancing circuit 22 balances the first battery cell when the parameters of all battery cells 10 are greater than the preset parameter value and the difference between the parameter of the first battery cell and the minimum parameter is greater than or equal to the preset value. Exemplarily, the battery cell 10 may be a lithium iron phosphate battery, the parameter of the battery cell 10 is the sampled voltage of the battery cell 10, and the preset parameter value may be 3.3V.

[0044] Optionally, when the energy storage device is in a discharging state, the controller 1 is configured to control the sampling switch QC to be disconnected and the balancing switch QB to be turned on through the balancing terminal DB so that the balancing circuit 22 balances the first battery cell when the parameters of all battery cells 10 are less than the preset parameter value and the difference between the parameter of the first battery cell and the minimum parameter is greater than or equal to the preset value. Exemplarily, the battery cell 10 may be a lithium iron phosphate battery, the parameter of the battery cell 10 is the sampled voltage of the battery cell 10, and the preset parameter value may be 3.1V.

[0045] Optionally, in one embodiment, after the controller 1 operates normally, the controller 1 can make the balancing terminal DB output a low level, the balancing switch QB is disconnected under the action of the low level, the balancing and sampling interlock circuit does not perform a balancing operation, and the sampling switch QC is turned on under the action of the low level. The controller 1 intermittently reads the parameters (such as the voltage value) of the battery cell 10 according to the software task configuration in the battery management system. For example, the voltage value is read every 1 second, and the controller 1 is in a sampling and non-balancing state.

[0046] In one embodiment, during the operation of the controller 1, if it is detected that the voltage of a certain battery cell 10 is too high (too high means that the difference between the voltage value of the battery cell 10 and the minimum voltage is greater than or equal to a preset value) and balancing is required, the controller 1 can make the balancing terminal DB output a high level. The balancing switch QB is turned on under the action of the high level, and the balancing and sampling interlock circuit starts the balancing operation. The sampling switch QC is turned off under the action of the high level, and the controller 1 is in the balancing and non-sampling state. In one embodiment, if during the balancing process of a certain battery cell 10, the control software in the battery management system assigns the task of sampling the voltage of this battery cell 10 to the controller 1 and the controller 1 needs to execute the sampling command, then the corresponding balancing terminal DB is controlled to output a low level, the balancing switch QB is turned off, and the sampling switch QC is turned on. The sampling signal is transmitted to the controller 1 through the sampling switch QC.

[0047] Optionally, in one embodiment, for illustrative purposes, please refer to Figure 2 , the balancing and sampling interlock circuit is connected to three battery cells 10, that is, n = 2 (n is a natural number equal to 2), which are B_1, B_2, and B_3 respectively. The controller 1 detects that the voltages of the battery cells B_1, B_2, and B_3 are 3.5V, 3.503V, and 3.506V respectively, and the preset value is 5mV. The minimum parameter is the voltage value of the battery cell B_1, which is 3.5V. The difference between the voltage value of the battery cell B_3 and the minimum parameter is 6mV. It is determined that the first battery cell 10 is B_3. At this time, the controller 1 controls the corresponding balancing terminal DB_3 of the battery cell B_3 to output a high level, the sampling switch QC_3 corresponding to the battery cell B_3 is turned off, and at the same time the balancing switch QB_3 is turned on. The balancing and sampling interlock circuit starts the balancing operation on the battery cell B_3 until the balancing is completed.

[0048] In one embodiment, the balancing and sampling interlock circuit starts the balancing operation on the battery cell B_3. At this time, the controller 1 is in the balancing and non-sampling state. After the preset balancing duration, the balancing terminal DB_3 corresponding to the battery cell B_3 of the controller 1 outputs a low level, the balancing switch QB_3 is turned off, and at the same time the sampling switch QC_3 is turned on. The sampling signal is transmitted to the controller 1 through the sampling switch QC_3. If it is detected at this time that the difference between the sampled voltage of the battery cell B_3 and the minimum sampled voltage is still greater than or equal to the preset value, then the balancing terminal DB_3 corresponding to the battery cell B_3 of the controller 1 outputs a high level to balance the battery cell B_3 until it is detected that the difference between the sampled voltage of the battery cell B_3 and the minimum sampled voltage is less than the preset value, and the balancing is completed. Exemplarily, the preset duration can be 5 minutes.

[0049] In some embodiments, please refer to Figure 1 and Figure 2, each processing unit 2 includes a control resistor R3, and the control resistor R3 is electrically connected between a corresponding equalization terminal DB and the ground;

[0050] The control resistor R3 is configured to control the sampling switch QC to conduct and the equalization switch QB to disconnect.

[0051] The control resistor R3 includes a pull-down resistor for ensuring that the signal line is at a low voltage level when there is no signal input. To ensure that the controller 1 is in the sampling and non-equalization state when starting to run, the signal line connected to the equalization terminal DB is at a low voltage level through the control resistor R3 when there is no signal input.

[0052] Specifically, when the controller 1 is in the sleep or non-operating state, the signal line connected to the equalization terminal DB is at a low voltage level, the sampling switch QC conducts, and the equalization switch QB disconnects.

[0053] In the above embodiment, by adding a pull-down resistor to the signal line connected to the equalization terminal DB, it is ensured that when there is no signal input, that is, when the controller 1 is in the sleep or non-operating state, the sampling switch QC conducts and the equalization switch QB disconnects, thereby ensuring that the controller 1 is in the sampling and non-equalization state when starting to run.

[0054] Optionally, in one embodiment, when the controller 1 is not powered on or in the sleep state, the equalization switch QB remains in the off state under the action of the control resistor R3, the equalization is not enabled, while the sampling switch QC remains closed and conducts under the action of the control resistor R3, and the sampling signal can be transmitted to the analog-to-digital conversion module (ADC) of the controller 1.

[0055] In some embodiments, please refer to Figure 1 and Figure 2 , the equalization circuit 22 includes an equalization resistor RB, and the equalization resistor RB is electrically connected between the equalization switch QB and a corresponding battery cell 10;

[0056] The controller 1 is configured to control the sampling switch QC to disconnect and the equalization switch QB to conduct through the equalization terminal DB so that the equalization resistor RB equalizes the first battery cell.

[0057] The equalization resistor RB is a resistor used for battery equalization in the battery management system, and is electrically connected between the equalization switch QB and the battery cell 10. By dissipating the excess electrical energy, the voltage of the battery cell 10 is reduced, so that the voltages of all battery cells 10 reach consistency.

[0058] Specifically, when the difference between the parameters of the first battery cell and the minimum parameter is greater than or equal to the preset value, the controller 1 controls the sampling switch QC to disconnect through the balancing terminal DB, and at the same time controls the balancing switch QB to conduct, so that the balancing resistor RB is connected to the battery cell 10. The balancing resistor RB dissipates the excess electrical energy of the battery cell 10 and reduces its voltage to the same level as that of other battery cells 10.

[0059] In the above embodiment, through the balancing resistor RB, the excess electrical energy of the battery cell 10 with a higher voltage can be dissipated, improving the consistency between battery cells, so that the charging and discharging are more sufficient, that is, the energy stored in or discharged from the energy storage system is more.

[0060] In an alternative embodiment, please refer to Figure 3 , the balancing circuit 22 includes a DC-DC converter, and the DC-DC converter is electrically connected between the balancing switch QB and a corresponding battery cell 10, and the DC-DC converter is electrically connected to the DC bus;

[0061] When the difference between the parameters of the first battery cell and the minimum parameter is greater than or equal to the preset value, the controller 1 is configured to control the sampling switch QC to disconnect and the balancing switch QB to conduct through the balancing terminal DB so that the DC-DC converter balances the first battery cell.

[0062] Specifically, the DC bus includes the positive line 31 of the DC bus and the negative line 32 of the DC bus. A DC-DC converter is an electronic device that converts one DC voltage into another different DC voltage. The DC-DC converter includes a boost converter, a buck converter, and / or a buck-boost converter.

[0063] The DC-DC converter is a voltage converter used for battery balancing in the battery management system. It is electrically connected between the balancing switch QB and the battery cell 10, and the DC-DC converter is electrically connected to the DC bus. By converting and transferring the excess energy of the high-voltage battery cell 10 to the DC bus or converting and transferring the energy of the DC bus to the low-voltage battery cell 10, the voltage balance of multiple battery cells 10 is achieved. Exemplarily, the positive line 31 of the DC bus can be electrically connected to the positive electrode of the battery pack composed of multiple battery cells 10, and the negative line 32 of the DC bus can be electrically connected to the negative electrode of the battery pack composed of multiple battery cells 10.

[0064] In the above embodiment, through the DC-DC converter, the excess energy of the high-voltage battery cell 10 can be converted and transferred to the DC bus or the energy of the DC bus can be converted and transferred to the low-voltage battery cell 10, improving the consistency between battery cells, so that the charging and discharging are more sufficient, that is, the energy stored in or discharged from the energy storage system is more.

[0065] In some embodiments, refer to Figure 1 and Figure 2 , the sampling circuit 21 includes a filtering circuit, and the filtering circuit is electrically connected between the sampling terminal VB and the sampling switch QC.

[0066] A filtering circuit is a circuit used to process electrical signals, and its main function is to remove noise and unwanted frequency components from the signals. The filtering circuit can be designed as a low-pass filter, a high-pass filter, a band-pass filter or a band-stop filter according to needs.

[0067] In the battery management system, the voltage sampling circuit 21 needs to collect the voltage signals of the battery cells 10. However, these signals may be affected by various noises and interferences, such as switching noise. These noises will cause the collected voltage signals to be inaccurate, thus affecting the performance of the battery management system. Therefore, in order to reduce the inaccuracy of the collected voltage signals caused by noise, a filtering circuit is introduced between the sampling terminal VB and the sampling switch QC.

[0068] In the above embodiments, the high-frequency noises and interferences in the sampling signals are effectively removed by the filtering circuit, the purity of the signals is improved, and thus the accuracy of voltage sampling is enhanced.

[0069] In some embodiments, refer to Figure 2 , the filtering circuit includes a filtering resistor R1 and a filtering capacitor C1. The filtering resistor R1 is electrically connected between the sampling switch QC and the sampling terminal VB; the filtering capacitor C1 is electrically connected between the filtering resistor R1 and the ground.

[0070] The filtering resistor R1 is a resistor element in the filtering circuit used to limit the current and form a specific impedance. The filtering capacitor C1 is a capacitor element used to provide a specific impedance according to the frequency characteristics. When the signal passing through the filtering capacitor C1 is a low-frequency signal, the impedance of the filtering capacitor C1 is high, and the low-frequency signal is basically maintained; when the signal passing through the filtering capacitor C1 is a high-frequency signal, the impedance of the filtering capacitor C1 is low, and the high-frequency signal will be absorbed by the filtering capacitor C1 or bypassed to the ground. Among them, the frequency of the cutoff high-frequency signal is determined by the resistance value of the filtering resistor R1 and the capacitance value of the filtering capacitor C1.

[0071] In order to reduce the inaccuracy of the collected voltage signals caused by noise, a filtering capacitor C1 and a filtering resistor R1 are introduced between the sampling terminal VB and the sampling switch QC. Specifically, the sampling signal of the battery cell 10 is transmitted to the filtering resistor R1 through the conducting sampling switch QC. Then, the high-frequency part in the sampling signal is grounded along the filtering capacitor C1, and part of the high-frequency signal is absorbed by the filtering capacitor C1 and part is bypassed to the ground, thus suppressing and filtering out the high-frequency part in the sampling signal.

[0072] In the above-described embodiments, by means of the filtering capacitor C1 and the filtering resistor R1, the high-frequency components in the sampling signal can be effectively suppressed and filtered, thereby improving the sampling accuracy.

[0073] In some embodiments, please refer Figure 1 and Figure 2 , the processing unit 2 includes a current-limiting resistor R2, and the current-limiting resistor R2 is electrically connected to the equalization terminal DB.

[0074] The current-limiting resistor R2 is a resistor element for limiting current. The current-limiting resistor R2 is electrically connected to the equalization terminal DB to ensure that the current generated by driving the equalization switch QB and the sampling switch QC at the equalization terminal DB does not exceed the set safety value.

[0075] In the above-described embodiments, by limiting the current generated by the equalization terminal DB driving the equalization switch QB and the sampling switch QC through the current-limiting resistor R2 not to exceed the set safety value, it helps to reduce the over-current risk in the equalization and sampling interlock circuit, thereby preventing damage to the equalization switch QB and the sampling switch QC caused by excessive current and improving the long-term reliability of the system.

[0076] In some embodiments, please refer Figure 2 , the equalization and sampling interlock circuit includes a plurality of electromagnetic interference suppression capacitors C2, and the electromagnetic interference suppression capacitors C2 are electrically connected between the ground and a corresponding battery cell 10.

[0077] The electromagnetic interference suppression capacitor C2 includes an EMC capacitor (Electromagnetic Compatibility Capacitor), which is used to suppress and filter electromagnetic interference and improve the electromagnetic compatibility of the equalization and sampling interlock circuit, ensuring the normal operation of the equalization and sampling interlock circuit in a complex electromagnetic environment.

[0078] Specifically, the EMC capacitor can provide a low-impedance path for high-frequency noise, absorb the high-frequency noise or guide it from the power line to the ground.

[0079] In the above-described embodiments, by introducing the electromagnetic interference suppression capacitor C2 between the battery cell 10 and the ground, the electromagnetic interference outside the equalization and sampling interlock circuit can be effectively filtered, improving the anti-interference ability and electromagnetic compatibility of the equalization and sampling interlock circuit, thereby ensuring the stable operation of the equalization and sampling interlock circuit in a complex electromagnetic environment and improving the overall reliability and performance of the equalization and sampling interlock circuit.

[0080] In some embodiments, please refer Figure 2 , the equalization switch QB includes an N-type metal oxide field effect transistor, and the sampling switch QC includes a P-type metal oxide field effect transistor.

[0081] Specifically, the balancing switch QB includes an N-type metal-oxide-semiconductor field-effect transistor, that is, an NMOS (N-Metal-Oxide-Semiconductor), and the NMOS has a gate, a source, and a drain. The sampling switch QC includes a P-type metal-oxide-semiconductor field-effect transistor, that is, a PMOS (P-Metal-Oxide-Semiconductor), and the PMOS has a gate, a source, and a drain.

[0082] Specifically, the gates of the balancing switch QB and the sampling switch QC are both electrically connected to the balancing terminal DB of the controller 1. When the balancing terminal DB outputs a high level, the balancing switch QB conducts, and the sampling switch QC disconnects; when the balancing terminal DB outputs a low level, the balancing switch QB disconnects, and the sampling switch QC conducts.

[0083] In the above embodiment, by setting the balancing switch QB and the sampling switch QC as N-type and P-type MOSs respectively, the controller 1 can control the balancing and sampling interlock circuit through voltages at different levels, so as to meet the requirement of avoiding simultaneous occurrence of balancing and sampling.

[0084] In an alternative embodiment, the balancing switch QB includes an NPN bipolar junction transistor, and the sampling switch QC includes a PNP bipolar junction transistor.

[0085] Specifically, the balancing switch QB includes an NPN bipolar junction transistor, that is, an NPN transistor (NPN BJT, Negative-Positive-Negative Bipolar Junction Transistor), and the NPN BJT has a base, a collector, and an emitter. The sampling switch QC includes a PNP transistor, that is, a PNP BJT (Positive-Negative-Positive Bipolar Junction Transistor), and the PNP BJT has a base, a collector, and an emitter.

[0086] Specifically, the bases of the balancing switch QB and the sampling switch QC are both electrically connected to the balancing terminal DB of the controller 1. When the balancing terminal DB outputs a high level, the balancing switch QB conducts, and the sampling switch QC disconnects; when the balancing terminal DB outputs a low level, the balancing switch QB disconnects, and the sampling switch QC conducts.

[0087] In the above embodiment, by setting the balancing switch QB and the sampling switch QC as an NPN transistor and a PNP transistor respectively, the controller 1 can control the balancing and sampling interlock circuit through voltages at different levels, so as to meet the requirement of avoiding simultaneous occurrence of balancing and sampling.

[0088] In an alternative embodiment, the sampling switch QC is connected in parallel with a first capacitor C3.

[0089] In the above embodiments, when the sampling switch QC is connected in parallel with the first capacitor C3, the total capacitance increases, resulting in an extended conduction time of the sampling switch QC. Since there may be software delays or other forms of delays in the battery management system, for example, communication delays and / or data processing delays, etc., when the equalization terminal DB of the controller 1 outputs a low level, the equalization switch QB disconnects, and the sampling switch QC conducts after a certain time when the equalization switch QB disconnects. This delayed design of the sampling switch QC makes the start time point of the sampling operation later than the equalization end time point, thereby reducing the influence caused by software delays to a certain extent, and further ensuring that no equalization operation is performed when the sampling operation is carried out in the equalization and sampling interlock circuit, improving the sampling accuracy.

[0090] In some embodiments, when the controller 1 outputs a high level, the equalization switch QB conducts and the sampling switch QC disconnects;

[0091] When the controller 1 outputs a low level, the equalization switch QB disconnects and the sampling switch QC conducts.

[0092] Specifically, when the difference between the first battery cell and the minimum parameter is greater than or equal to the preset value, the controller 1 outputs a high level. The equalization terminal DB of the controller 1 is electrically connected to the equalization switch QB and the sampling switch QC. The sampling switch QC disconnects under the action of the high level. At the same time, the equalization switch QB conducts under the action of the high level, and both ends of the battery cell 10 are incorporated into an equalization resistor RB. The equalization resistor RB dissipates the excess electrical energy of the battery cell 10 to perform the equalization operation. After the equalization is completed, the controller 1 outputs a low level. The equalization switch QB disconnects under the action of the low level. At the same time, the sampling switch QC conducts under the action of the low level, and the sampling signal of the battery cell 10 is transmitted to the analog-to-digital conversion module of the controller 1 through the conducting sampling switch QC, so that the analog-to-digital conversion module converts the sampled analog (voltage) signal into a digital signal that the controller 1 can analyze and process.

[0093] In the above embodiments, by controlling the voltage level to control the conduction and disconnection of the sampling switch QC and the equalization switch QB, it is possible to avoid the simultaneous occurrence of the equalization operation and the sampling operation, improving the sampling accuracy and the effectiveness of the equalization.

[0094] A battery management system provided by an embodiment of the present invention includes the above-mentioned equalization and sampling interlock circuit.

[0095] A battery management system (Battery Management System, BMS) is an integrated system used to monitor and manage a battery pack, aiming to ensure the safe, reliable, and efficient operation of the battery.

[0096] An energy storage device provided by an embodiment of the present utility model includes a plurality of battery cells and the battery management system of the above embodiment, and the battery management system is electrically connected to the plurality of battery cells.

[0097] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples" or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0098] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, combinations, modifications, substitutions and variations to the above embodiments within the scope of the present utility model.

Claims

1. A balancing and sampling interlock circuit for an energy storage device, the energy storage device comprising a plurality of battery cells, characterized in that, The equalization and sampling interlock circuit includes: A controller, the controller including a plurality of sampling terminals and a plurality of equalization terminals; A plurality of processing units, each processing unit being electrically connected between the controller and a corresponding one of the battery cells; The processing unit includes an equalization circuit and a sampling circuit, the sampling circuit including a sampling switch, the sampling switch being electrically connected between a corresponding one of the sampling terminals and a corresponding one of the battery cells; the equalization circuit includes an equalization switch, the equalization switch being electrically connected between a corresponding one of the equalization terminals and a corresponding one of the battery cells; the sampling switch is electrically connected to the equalization terminal; The controller is configured to control the sampling switch to conduct and the equalization switch to disconnect through the equalization terminal and sample the parameters of the battery cell through the sampling terminal, and control the sampling switch to disconnect and the equalization switch to conduct through the equalization terminal to enable the equalization circuit to equalize the first battery cell.

2. The equalization and sampling interlock circuit according to claim 1, characterized in that, Each processing unit includes a control resistor, the control resistor being electrically connected between a corresponding one of the equalization terminals and the ground; The control resistor is configured to control the sampling switch to conduct and the equalization switch to disconnect.

3. The equalization and sampling interlock circuit according to claim 1, characterized in that, The equalization circuit includes an equalization resistor, the equalization resistor being electrically connected between the equalization switch and a corresponding one of the battery cells; The controller is configured to control the sampling switch to disconnect and the equalization switch to conduct through the equalization terminal to enable the equalization resistor to equalize the first battery cell.

4. The equalization and sampling interlock circuit according to claim 1, wherein The sampling circuit includes a filtering circuit, the filtering circuit being electrically connected between the sampling terminal and the sampling switch.

5. The equalization and sampling interlock circuit according to claim 4, wherein The filtering circuit includes a filtering resistor and a filtering capacitor, the filtering resistor being electrically connected between the sampling switch and the sampling terminal; the filtering capacitor being electrically connected between the filtering resistor and the ground.

6. The equalization and sampling interlock circuit according to claim 1, wherein The processing unit includes a current limiting resistor, the current limiting resistor being electrically connected to the equalization terminal.

7. The equalization and sampling interlock circuit according to claim 1, wherein The equalization and sampling interlock circuit includes a plurality of electromagnetic interference resistant capacitors, the electromagnetic interference resistant capacitors being electrically connected between the ground and a corresponding one of the battery cells.

8. The equalization and sampling interlock circuit according to claim 1, characterized in that The equalization switch includes an N-type metal oxide field effect transistor, and the sampling switch includes a P-type metal oxide field effect transistor.

9. The equalization and sampling interlock circuit according to claim 1, wherein When the controller outputs a low level, the equalization switch disconnects and the sampling switch conducts; When the controller outputs a high level, the equalization switch conducts and the sampling switch disconnects.

10. A battery management system, characterized in that, Includes the equalization and sampling interlock circuit according to claims 1-9.

11. An energy storage device, characterized in that, Includes a plurality of battery cells and the battery management system according to claim 10, the battery management system being electrically connected to the plurality of battery cells.

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