Alternating current and direct current power supply input identification wake-up circuit and EVCC
By designing the AC-DC power input recognition wake-up circuit, the problem of inaccurate power signal recognition in the charging system of electric vehicles is solved, and the accurate judgment of the power signal and low-power wake-up EVCC control chip is achieved, avoiding charging damage and increased power consumption.
Patent Information
- Application Number
- CN202422291551.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-09-19
AI Technical Summary
Existing electric vehicle charging systems are difficult to accurately identify AC and DC power signals, resulting in damage to the vehicle and increasing power consumption on the vehicle during charging.
An AC-DC power supply input recognition wake-up circuit is designed, including a PWM wave signal voltage amplitude stabilization circuit, a PWM wave signal duty cycle detection circuit, a D flip-flop module, an AND gate chip and an EVCC control chip. The power supply signal type is judged by detecting the duty cycle of the CP signal, and the EVCC control chip is awakened when the DC power supply signal is identified.
It realizes a complete and accurate judgment of the power signal, avoids damage to the vehicle by AC power, and reduces the power consumption of the charging base on the vehicle end.
Smart Images
Figure CN223157058U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electric vehicle charging, in particular to an AC / DC power input recognition and wake-up circuit and an EVCC. Background Art
[0002] Environmentally friendly vehicles such as electric vehicles (EVs) or plug-in hybrid electric vehicles (PHEVs) use an electric vehicle supply equipment (EVSE), that is, a charging pile, to charge the vehicle battery. At present, the charging of new energy electric vehicles produced in China uses a CAN communication channel, which does not match the charging piles using European standards, American standards, Japanese standards, etc. Therefore, an EVCC (Electric Vehicle Communication Controller) is usually set at the vehicle end to convert the CAN signal in the national standard charging into a PLC (Power line Carrier) signal in the CCS (Combined Charging System) charging mode, and control the charging process and data exchange.
[0003] Since an electric vehicle can be charged both by AC charging (the electric energy of an AC charging pile is converted into DC through an on-vehicle charger) and by DC charging (the electric energy of a DC charging pile is directly supplied to the power battery of the vehicle), it is necessary to make a complete and accurate judgment on the input power signal. And to meet the requirement of low power consumption at the vehicle end, usually each chip needs to be woken up when needed and go to sleep when not needed. Therefore, there is an urgent need to provide a circuit that can both identify the power signal and wake up the chip to solve the above problems. Summary of the Utility Model
[0004] Embodiments of the present disclosure provide an AC / DC power input recognition and wake-up circuit and an EVCC to at least partially solve the above technical problems.
[0005] On the one hand, an AC / DC power input recognition and wake-up circuit for an EVCC is proposed. The AC / DC power input recognition and wake-up circuit includes a PWM wave signal voltage amplitude stabilization circuit, a PWM wave signal duty cycle detection circuit, a D flip-flop module, an AND gate chip, a power supply module, and an EVCC control chip. An external CP input signal is connected to the input end of the PWM wave signal duty cycle detection circuit via the PWM wave signal voltage amplitude stabilization circuit. The output end of the PWM wave signal duty cycle detection circuit is connected to the first input pin of the AND gate chip; the CP input signal is connected to the signal input end of the D flip-flop module, the signal output end of the D flip-flop module is connected to the second input pin of the AND gate chip, the output pin of the AND gate chip is connected to the enable pin of the power supply module, and the output end of the power supply module is connected to the power input end of the EVCC control chip.
[0006] Preferably, the PWM wave signal voltage amplitude stabilizing circuit includes a first comparator. The inverting input terminal of the first comparator is connected to a first reference voltage, the non-inverting input terminal of the first comparator is connected to the CP input signal, and the output terminal of the first comparator is connected to the input terminal of the PWM wave signal duty cycle detection circuit.
[0007] Preferably, the PWM wave signal duty cycle detection circuit includes a second comparator. The output terminal of the first comparator is connected to the inverting input terminal of the second comparator, the non-inverting input terminal of the second comparator is connected to a second reference voltage, and the output terminal of the second comparator is connected to the first input pin.
[0008] Preferably, at least one set of RC filter circuits is further provided between the output terminal of the first comparator and the inverting input terminal of the second comparator.
[0009] Preferably, the D flip-flop module includes a pre-stage filter circuit and a D flip-flop. The CP input signal is connected to the clock signal input terminal of the D flip-flop via the pre-stage filter circuit, and the output terminal of the D flip-flop is connected to the second input pin.
[0010] Preferably, the reverse output pin of the D flip-flop is left floating, and the clear input terminal of the D flip-flop is connected to the signal output terminal of the EVCC control chip.
[0011] Preferably, the power supply module is a DCDC power supply.
[0012] On the other hand, an EVCC is provided, including
[0013] a box body;
[0014] a circuit board installed in the box body; and
[0015] the AC-DC power input recognition and wake-up circuit according to any one of the above embodiments, integrated on the circuit board.
[0016] According to the recognition and wake-up circuit of the present utility model, it can make a complete and accurate judgment on the input power signal by detecting the duty cycle of the CP signal; and when it recognizes that it is a DC power signal, it wakes up the EVCC control chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0018] Figure 1 It is a structural block diagram of an AC / DC power input recognition and wake-up circuit for the preferred embodiment of this article.
[0019] Figure 2 It is a circuit schematic diagram of an AC / DC power input recognition and wake-up circuit for the preferred embodiment of this article. Specific Embodiments
[0020] The preferred embodiments of the present disclosure will be described below in conjunction with the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only for the purpose of illustrating and explaining the present disclosure, and are not used to limit the present disclosure. And without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.
[0021] As Figure 1 shown, this article provides an AC / DC power input recognition and wake-up circuit for a preferred embodiment, which is used for EVCC. EVCC is usually set in the vehicle-side charging socket. In this embodiment, a charging pile with a NACS (North American Charging Standard) charging interface charges an electric vehicle with a CCS1 (Combined Charging System 1) standard interface. Since the NACS charging interface is an AC / DC integrated interface, before charging an electric vehicle with a CCS1 standard interface, EVCC needs to first identify whether the charging power is AC or DC. Therefore, the recognition and wake-up circuit of the present utility model is proposed. When a DC power signal is recognized, EVCC is woken up and a charging path is established; when an AC power signal is recognized, EVCC remains in a dormant state. This avoids charging an electric vehicle with a CCS1 standard interface with AC power, causing unnecessary damage, and also reduces the power consumption of the vehicle-side charging socket.
[0022] As Figure 1 shown, the AC / DC power input recognition and wake-up circuit includes a PWM wave signal voltage amplitude stabilization circuit, a PWM wave signal duty cycle detection circuit, a D flip-flop module, an AND gate chip U2, a power supply module, and an EVCC control chip. The external CP input signal (from the charging pile) is connected to the input ends of the PWM wave signal voltage amplitude stabilization circuit and the PWM wave signal duty cycle detection circuit. The output end of the PWM wave signal duty cycle detection circuit is connected to the first input pin A of the AND gate chip U2; the CP input signal is connected to the signal input end of the D flip-flop module, the signal output end of the D flip-flop module is connected to the second input pin B of the AND gate chip U2, the output pin Y of the AND gate chip U2 is connected to the enable pin of the power supply module, and the output end of the power supply module is connected to the power input end of the EVCC control chip. Preferably, the power supply module is a DCDC power supply.
[0023] Specifically, as Figure 2As shown in the figure, the PWM wave signal voltage amplitude stabilization circuit includes a first comparator U1A. The inverting input terminal of the first comparator U1A is connected to a first reference voltage, the non-inverting input terminal of the first comparator U1A is connected to a CP input signal (from a charging pile), and the output terminal of the first comparator U1A is connected to the input terminal of the PWM wave signal duty cycle detection circuit.
[0024] Specifically, as Figure 2 shown in the figure, the PWM wave signal duty cycle detection circuit includes a second comparator U1B. The output terminal of the first comparator U1A is connected to the inverting input terminal of the second comparator U1B, the non-inverting input terminal of the second comparator U1B is connected to a second reference voltage, and the output terminal of the second comparator U1B is connected to the first input pin A of the AND gate chip U2.
[0025] Preferably, as Figure 2 shown in the figure, at least one set of RC filter circuits is further provided between the output terminal of the first comparator U1A and the inverting input terminal of the second comparator U1B.
[0026] Specifically, as Figure 2 shown in the figure, the D flip-flop module includes a pre-stage filter circuit and a D flip-flop U3. The CP input signal (from a charging pile) is connected to the clock signal input terminal CP of the D flip-flop U3 via the pre-stage filter circuit, and the output terminal Q of the D flip-flop U3 is connected to the second input pin B of the AND gate chip U2. More specifically, the reverse output pin Q# of the D flip-flop U3 is left floating, and the clear input terminal CLR of the D flip-flop U3 is connected to the signal output terminal of the EVCC control chip.
[0027] Working principle:
[0028] As Figure 2 shown in the figure, the non-inverting input terminal of the first comparator U1A receives the CP input signal from the charging pile. The 5V power supply voltage is input to the inverting input terminal of the first comparator U1A after voltage division and filtering. In this embodiment, by setting the parameters of the components (resistor R1, capacitor C2, and resistor R2) for voltage division and filtering, the input voltage (the first reference voltage) of this inverting input terminal is close to 2V. Since the amplitudes of the CP input signal in the charging state and the non-charging state are different, it is necessary to use the first comparator U1A to stabilize the voltage amplitude of the CP input signal of the PWM wave, and convert it into a 5V PWM wave with a constant amplitude regardless of the amplitude of the CP input signal. Figure 2 The resistor R4 and the capacitor C46 in [[ ]] form a set of RC filter circuits to convert the 5V PWM wave into a voltage signal. It can be understood that in other embodiments, more sets of filter circuits can also be provided.
[0029] The second comparator U1B is used to detect the frequency of the CP input signal of the PWM wave (which can be analogized to duty cycle detection). The 5V power supply voltage is input to the non-inverting input terminal of the second comparator U1B after voltage division and filtering. In this embodiment, by setting the parameters of the components for voltage division and filtering (resistor R5, capacitor C48, and resistor R6), the input voltage (the second reference voltage) of this non-inverting input terminal is close to 0.4V. If the frequency of the CP input signal falls within the range of 3% - 7% of 1KHz (the inherent frequency of the CP input signal), then the input voltage of the inverting input terminal of the second comparator U1B is between 0.15V and 0.35V. At this time, the output terminal of the second comparator U1B is at a high level; if the frequency of the CP input signal falls within the range of 9% - 99% of 1KHz (the inherent frequency of the CP input signal), then the input voltage of the inverting input terminal of the second comparator U1B is between 0.45V and 4.95V. At this time, the output terminal of the second comparator U1B is at a low level.
[0030] It should be noted that the ranges of 3% - 7% and 9% - 99% mentioned above are the ranges set according to the IEC61851 standard. The standard stipulates that the frequency of the DC CP signal is within the range of 3% - 7% of the inherent frequency, and the frequency of the AC CP signal is within the range of 9% - 99% of the inherent frequency. Therefore, it can be understood that when the second comparator U1B outputs a high level, it indicates that the power supply signal is a DC power supply signal, and when the second comparator U1B outputs a low level, it indicates that the power supply signal is an AC power supply signal.
[0031] Continue to refer to Figure 2 , the CP input signal is input to the clock signal input terminal CP of the D flip-flop U3, and the output terminal Q of the D flip-flop U3 outputs a high level. At the same time, if the output terminal of the second comparator U1B also outputs a high level, then after being processed by the AND gate chip U2, the output pin Y of the AND gate chip U2 will output a high level to the enable pin of the power supply module. Therefore, the power supply module starts to supply power to EVCC, thereby waking up EVCC; if the output terminal of the second comparator U1B outputs a low level, then after being processed by the AND gate chip U2, the output pin Y of the AND gate chip U2 will output a low level, and the power supply module will not supply power to EVCC, so EVCC remains in a dormant state. Therefore, through this identification and wake-up circuit, it can be realized that when it is identified that it is a DC power supply signal, the EVCC control chip is woken up. It should be noted that the addition of the AND gate chip U2 in this circuit is to eliminate the situation where the second comparator U1B outputs a high level when the CP input signal is 0V. That is, when the CP input signal is 0V, even if the second comparator U1B outputs a high level, but at this time the D flip-flop U3 outputs a low level, and after being processed by the AND gate chip U2, it is still a low level, and it will not trigger the power supply module to supply power to EVCC. Therefore, EVCC will not be woken up.
[0032] In addition, the present disclosure also provides an EVCC, including:
[0033] A box body;
[0034] A circuit board installed in the box body; and
[0035] The AC / DC power input recognition and wake-up circuit according to any one of the above embodiments, integrated on the circuit board.
[0036] According to the recognition and wake-up circuit and EVCC of the present utility model, it is possible to make a complete and accurate judgment on the input power signal by detecting the duty cycle of the CP signal; and when it is recognized that the signal is a DC power signal, the EVCC control chip is woken up.
[0037] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.
[0038] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.
[0039] It should also be understood that in the embodiments herein, the term "and / or" is merely a description of the associated relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.
[0040] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this article.
[0041] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0042] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments in this article.
[0043] In addition, each functional unit in the various embodiments in this article can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.
[0044] Specific embodiments are used in this article to elaborate on the principles and implementation manners of this article. The description of the above embodiments is only used to help understand the method and its core idea in this article; at the same time, for those of ordinary skill in the art, according to the idea in this article, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this article.
Claims
1. An AC / DC power input recognition and wake-up circuit, characterized in that, For an EVCC, the AC / DC power input recognition and wake-up circuit includes a PWM wave signal voltage amplitude stabilization circuit, a PWM wave signal duty cycle detection circuit, a D flip-flop module, an AND gate chip, a power module, and an EVCC control chip. The external CP input signal is connected to the input ends of the PWM wave signal voltage amplitude stabilization circuit and the PWM wave signal duty cycle detection circuit via the PWM wave signal voltage amplitude stabilization circuit. The output end of the PWM wave signal duty cycle detection circuit is connected to the first input pin of the AND gate chip; the CP input signal is connected to the signal input end of the D flip-flop module. The signal output end of the D flip-flop module is connected to the second input pin of the AND gate chip. The output pin of the AND gate chip is connected to the enable pin of the power module. The output end of the power module is connected to the power input end of the EVCC control chip.
2. The AC / DC power input recognition and wake-up circuit according to claim 1, wherein The PWM wave signal voltage amplitude stabilization circuit includes a first comparator. The inverting input end of the first comparator is connected to a first reference voltage. The non-inverting input end of the first comparator is connected to the CP input signal. The output end of the first comparator is connected to the input end of the PWM wave signal duty cycle detection circuit.
3. The AC / DC power input recognition and wake-up circuit according to claim 2, wherein The PWM wave signal duty cycle detection circuit includes a second comparator. The output end of the first comparator is connected to the inverting input end of the second comparator. The non-inverting input end of the second comparator is connected to a second reference voltage. The output end of the second comparator is connected to the first input pin.
4. The AC / DC power input recognition and wake-up circuit according to claim 3, characterized in that, At least one set of RC filter circuits is further provided between the output end of the first comparator and the inverting input end of the second comparator.
5. The AC / DC power input recognition and wake-up circuit according to claim 1, characterized in that, The D flip-flop module includes a pre-stage filter circuit and a D flip-flop. The CP input signal is connected to the clock signal input end of the D flip-flop via the pre-stage filter circuit. The output end of the D flip-flop is connected to the second input pin.
6. The AC / DC power input recognition and wake-up circuit according to claim 5, wherein The reverse output pin of the D flip-flop is left floating. The clear input end of the D flip-flop is connected to the signal output end of the EVCC control chip.
7. The AC / DC power input recognition and wake-up circuit according to claim 1, wherein The power module is a DCDC power supply.
8. An EVCC, characterized in that, Comprising, A box body; A circuit board installed in the box body; And The AC / DC power input recognition and wake-up circuit according to any one of claims 1-7, integrated on the circuit board.