Laser scanning control system based on SoC FPGA chip

Abstract

The utility model provides a laser scanning control system based on an SoC FPGA chip. The laser scanning control system comprises a main control chip, a laser data module and a laser control module. Wherein the main control chip is at least formed by integrating an HPS assembly and an FPGA assembly, and the laser data module and the laser control module are both electrically connected with the main control chip. The chip at least formed by integrating the HPS assembly and the FPGA assembly is selected as the main control chip of the laser scanning control system, the miniaturization requirement of the system is met, the cost is reduced, the circuit design is simplified, high-bandwidth data communication is achieved, and the interactivity and reliability of the system are improved.

Description

Technical Field

[0001] The utility model relates to the field of laser scanning, and in particular, to a laser scanning control system based on an SoC FPGA chip. Background Art

[0002] Currently, in the prior art, to solve the problems of data storage, high-speed processing, and high-speed transmission, the design scheme of FPGA+ARM or FPGA+DSP is mostly adopted. Such a design scheme can combine the advantages of the logical processing of FPGA and the arithmetic processing of ARM or DSP to complete the function of high-speed data processing. This scheme adopts the board-level integration method, that is, a complex circuit is designed on a circuit board, and FPGA is connected to ARM or DSP through PCB board traces. The system designed in this way not only has a high design cost, but also is limited by the PCB traces and the performance of I / O pins, and cannot achieve high-bandwidth data communication; moreover, in this scheme, a reasonable high-speed data transmission channel needs to be designed between the ARM / DSP chip and the FPGA chip to facilitate the real-time interaction between the FPGA and the ARM / DSP. This design scheme requires the design of a complex communication bus, which will consume a large amount of resources of the ARM / DSP and FPGA chips and is difficult to meet the requirement of miniaturization. Summary of the Invention

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art or related technologies.

[0004] Therefore, a first aspect of the utility model provides a laser scanning control system based on an SoC FPGA chip.

[0005] In view of this, a first aspect of the utility model provides a laser scanning control system based on an SoC FPGA chip, including: a main control chip, which is at least integrated by an HPS component and an FPGA component; a laser data module, electrically connected to the main control chip, and the laser data module is used for laser data exchange; a laser control module, electrically connected to the main control chip, and the laser control module is used to control the laser and provide laser processing information; a first internal bus, one end of the first internal bus is connected to the HPS component, and the other end of the first internal bus is connected to the FPGA component, and the first internal bus can send the first data from the HPS component to the FPGA component; a second internal bus, one end of the second internal bus is connected to the HPS component, and the other end of the second internal bus is connected to the FPGA component, and the second internal bus can send the second data from the HPS component to the FPGA component.

[0006] In addition, the laser scanning control system based on the SoC FPGA chip in the above technical solution provided by the present utility model may further have the following additional technical features:

[0007] In some technical solutions of the present utility model, optionally, the laser data module includes: a CAN module, the first end of the CAN module is electrically connected to the HPS component, the second end of the CAN module is connected to the expansion device, and the CAN module is used for data exchange with the expansion device; a data channel module, the data channel module is electrically connected to the HPS component, and the data channel module is used for receiving the first data; a control information module, the control information module is electrically connected to the FPGA component, and the control information module is used for receiving the second data.

[0008] In some technical solutions of the present utility model, optionally, the data channel module includes: a LAN module, the first end of the LAN module is electrically connected to the HPS component, and the LAN module is electrically connected to the host computer; a USB module, the first end of the USB module is electrically connected to the HPS component, and the USB module is electrically connected to the host computer; wherein, both the LAN module and the USB module receive the to-be-processed data of the host computer, and both the LAN module and the USB module upload the control status of the laser, and the LAN module serves as the main data channel, and the USB module serves as the backup data channel.

[0009] In some technical solutions of the present utility model, optionally, the first laser is controlled by an analog signal, the second laser is controlled by a PWM duty cycle, and the laser control module includes: a first control module, the first end of the first control module is electrically connected to the HPS component, the second end of the first control module is electrically connected to the first laser, and the first control module can control the first output power; a second control module, the first end of the second control module is electrically connected to the FPGA component, the second end of the second control module is electrically connected to the second laser, and the second control module can control the second output power; wherein, the first control module is used for outputting an analog signal, and the second control module is used for outputting a PWM duty cycle.

[0010] In some technical solutions of the present utility model, optionally, the control information module includes: a scan head drive module, the first end of the scan head drive module is electrically connected to the FPGA component, the second end of the scan head drive module is electrically connected to the laser scan head, and the scan head drive module is used for providing a drive signal and receiving the status information fed back by the laser scan head; an encoder input interface, the encoder input interface is electrically connected to the FPGA component, and the encoder input interface is used for providing machining position information.

[0011] In some technical solutions of the present utility model, optionally, an ADC module, the ADC module is electrically connected to the HPS component, and is used for receiving the feedback data of the first output power.

[0012] In some technical solutions of the present utility model, optionally, an isolated IO interface is electrically connected to the FPGA component and is used to connect to peripheral devices.

[0013] In some technical solutions of the present utility model, optionally, a UART module is electrically connected to the HPS module, and the UART module is used to output debug information.

[0014] In some technical solutions of the present utility model, optionally, a running memory module is electrically connected to the HPS component; a storage memory module is electrically connected to the HPS component.

[0015] In some technical solutions of the present utility model, optionally, an RTC module is electrically connected to the HPS component, and the RTC module is used to record the current time.

[0016] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present utility model will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, wherein:

[0018] Figure 1 FIG. shows a schematic diagram of a laser scanning control system based on a SoC FPGA chip according to an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] In order to more clearly understand the above objects, features and advantages of the present utility model, the present utility model will be further described in detail below in conjunction with the drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0020] Many specific details are set forth in the following description in order to fully understand the present utility model. However, the present utility model may be implemented in other ways different from those described herein. Therefore, the protection scope of the present utility model is not limited by the specific embodiments disclosed below.

[0021] The following refers to Figure 1 Describe a laser scanning control system based on a SoC FPGA chip according to some embodiments of the present utility model.

[0022] In an embodiment of the present utility model, as Figure 1As shown in the figure, a laser scanning control system based on an SoC FPGA chip is proposed, including: a main control chip, which is at least integrated by an HPS component and an FPGA component; a laser data module, which is electrically connected to the main control chip and is used for laser data exchange; a laser control module, which is electrically connected to the main control chip and is used for controlling a laser and providing laser processing information.

[0023] The utility model proposes a laser scanning control system based on an SoC FPGA chip, including a main control chip, a laser data module and a laser control module. Among them, the main control chip is at least integrated by an HPS component and an FPGA component, and both the laser data module and the laser control module are electrically connected to the main control chip. By using a chip that is at least integrated by an HPS component and an FPGA component as the main control chip of the laser scanning control system, the miniaturization requirement of the system is realized, the cost is reduced, the circuit design is simplified, high-bandwidth data communication is achieved, and the interactivity and reliability of the system are improved.

[0024] It should be understood that SoC (System on Chip) is a systematic solution that integrates multiple functional components such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a digital signal processor (DSP), a RAM (Random Access Memory), a modem, a navigation and positioning module, and a multimedia module on a single chip. It contains a complete hardware system and the embedded software it carries, and is one of the important technologies in the field of integrated circuits.

[0025] It should be understood that FPGA (Field-Programmable Gate Array) is a further development product based on programmable devices such as PAL, GAL, and CPLD. It is a semi-custom circuit that not only solves the deficiencies of custom circuits but also overcomes the shortcomings of limited gate circuits in the original programmable devices. The FPGA internally contains rich flip-flops and I / O pins and can implement different logic functions through programming. It is one of the devices with the shortest design cycle, the lowest development cost, and the lowest risk in ASIC circuits.

[0026] It should be understood that HPS (Hard Processor System) is an important part of the SoC, providing powerful processor performance and being the high-performance processor part integrated in the SoC.

[0027] Preferably, the main control chip selects a chip of the 5CSEBA2U23 model of the Cyclone V series of Intel Corporation.

[0028] Further, in some embodiments of the present utility model, there is a first internal bus, one end of the first internal bus is connected to the HPS component, and the other end of the first internal bus is connected to the FPGA component. The first internal bus can send the first data from the HPS component to the FPGA component; there is a second internal bus, one end of the second internal bus is connected to the HPS component, and the other end of the second internal bus is connected to the FPGA component. The second internal bus can send the second data from the HPS component to the FPGA component.

[0029] In this embodiment, there are also a first internal bus and a second internal bus. Among them, one end of the first internal bus is connected to the HPS component, and the other end of the first internal bus is connected to the FPGA component. The first internal bus can send the first data from the HPS component to the FPGA component. One end of the second internal bus is connected to the HPS component, and the other end of the second internal bus is connected to the FPGA component. The second internal bus can send the second data from the HPS component to the FPGA component.

[0030] Through the first internal bus and the second internal bus, high-speed data transmission between the HPS component and the FPGA component is achieved, the performance of the entire system is improved, resource utilization is optimized, a higher data transmission bandwidth is provided, the latency of data transmission is significantly reduced, and the data interaction between the HPS and the FPGA becomes more real-time and efficient.

[0031] Specifically, the first data includes laser processing data, and the second data includes the status of the laser scanning head and the status feedback of the second laser.

[0032] Specifically, the HPS component and the FPGA component share a storage unit and perform data interaction through the DMA (Direct Memory Access) method.

[0033] Preferably, the first internal bus is the H2F_LW_AXI_Master internal bus of the 5CSEBA2U23 model chip, and the second internal bus is the F2H_AXI_Slave internal bus of the 5CSEBA2U23 model chip.

[0034] Further, in some embodiments of the present utility model, the laser data module includes: a CAN module, the first end of the CAN module is electrically connected to the HPS component, the second end of the CAN module is connected to the expansion device, and the CAN module is used for data exchange with the expansion device; a data channel module, the data channel module is electrically connected to the HPS component, and the data channel module is used for receiving the first data; a control information module, the control information module is electrically connected to the FPGA component, and the control information module is used for receiving the second data.

[0035] In this embodiment, the laser data module includes a CAN module, a data channel module, and a control information module. Among them, the HPS component is electrically connected to the CAN module and the data channel module respectively, the control information module is electrically connected to the FPGA component, the second end of the CAN module is connected to the expansion device, the CAN module is used to exchange data with the expansion device, the data channel module is used to receive the first data, and the control information module is used to receive the second data.

[0036] Through the laser data module, information from external devices is received and further processed based on the data, thereby providing more comprehensive and accurate information support for the system and improving the intelligence level of the system.

[0037] Specifically, the expansion device can be a motion controller for the processing platform to adjust the workpiece state; it can also be a separate servo or stepper motor driver for simple device linkage; or it can be a device status monitor to transmit the device status and processing information to the cloud.

[0038] It should be noted that the CAN module is Controller Area Network, that is, Controller Area Network.

[0039] Further, in some embodiments of the present invention, the data channel module includes: a LAN module, the first end of the LAN module is electrically connected to the HPS component, and the LAN module is electrically connected to the host computer; a USB module, the first end of the USB module is electrically connected to the HPS component, and the USB module is electrically connected to the host computer; wherein, both the LAN module and the USB module receive the data to be processed from the host computer, and both the LAN module and the USB module upload the control status of the laser, and the LAN module serves as the main data channel, and the USB module serves as the backup data channel.

[0040] In this embodiment, the data channel module includes a LAN module and a USB module. Both the LAN module and the USB module are electrically connected to the HPS component, and at the same time, both the LAN module and the USB module are electrically connected to the host computer. On this basis, both the USB module and the LAN module receive the data to be processed from the host computer and upload the control status. The LAN module serves as the main data channel, and the USB module serves as the backup data channel.

[0041] By setting the main data channel and the backup data channel, when the main data channel (LAN module) fails or is interrupted, the system can seamlessly switch to the backup data channel (USB module) to ensure the continuity and stability of data transmission, reduce the fault recovery time, reduce the impact on production, and thus improve the reliability of the entire system.

[0042] Preferably, the USB module uses a USB3300-EZK as the PHY chip to receive the data to be processed and upload the control status from the host computer through a USB2.0 interface.

[0043] Preferably, the LAN module uses a TL8211FDI as the PHY chip to receive the data to be processed and upload the control status from the host computer through a 10 / 100 / 1000M Ethernet interface.

[0044] Furthermore, in some embodiments of the present invention, the first laser is controlled by an analog signal, and the second laser is controlled by a PWM duty cycle. The laser control module includes: a first control module, the first end of the first control module is electrically connected to the HPS component, the second end of the first control module is electrically connected to the first laser, and the first control module can control the first output power; a second control module, the first end of the second control module is electrically connected to the FPGA component, the second end of the second control module is electrically connected to the second laser, and the second control module can control the second output power; wherein, the first control module is used to output an analog signal, and the second control module is used to output a PWM duty cycle.

[0045] In this embodiment, the laser control module includes a first control module and a second control module. Among them, the first end of the first control module is electrically connected to the HPS component, the first end of the second control module is electrically connected to the FPGA component, the second end of the first control module is electrically connected to the first laser, the second end of the second control module is electrically connected to the second laser, the first control module can control the first output power, the second control module can control the second output power, the first control module is used to output an analog signal, and the second control module is used to output a PWM duty cycle. By setting the first control module and the second control module, the connection module of the laser can be selected according to the specific control mode of the laser, which improves the flexibility and compatibility of the system.

[0046] Preferably, the first control module is a DAC (Digital-to-Analog Converter) module. The DAC module serves as an analog quantity output interface to control the laser output power. Among them, the DAC module uses a TLV5638 as the conversion chip.

[0047] Preferably, the second control module selects a laser PWM driver as the main laser power control interface. In order to eliminate interference signals, this interface uses an SI8645BA chip as a high-speed digital isolation device.

[0048] Further, in some embodiments of the present utility model, the control information module includes: a scanning head driving module, a first end of the scanning head driving module is electrically connected to the FPGA component, a second end of the scanning head driving module is electrically connected to the laser scanning head, and the scanning head driving module is used to provide a driving signal and receive the status information fed back by the laser scanning head; an encoder input interface, the encoder input interface is electrically connected to the FPGA component, and the encoder input interface is used to provide machining position information.

[0049] In this embodiment, the control information module includes a scanning head driving module and an encoder input interface. Among them, a first end of the scanning head driving module is electrically connected to the FPGA component, a second end of the scanning head driving module is electrically connected to the laser scanning head, the encoder input interface is electrically connected to the FPGA component, and the encoder input interface is used to provide machining position information. By receiving and sending data, the FPGA component can dynamically adjust the control strategy, ensure the stable operation of the system, improve the machining efficiency, and enhance the flexibility and stability of the system.

[0050] Specifically, the scanning head driving module will provide driving signals for the three motors of the scanning head according to the FPGA output signal, and receive the status information fed back from the scanning head.

[0051] Specifically, the encoder input interface is compatible with single-ended / differential TTL level input and provides position feedback information for flying machining.

[0052] Further, in some embodiments of the present utility model, an ADC module, the ADC module is electrically connected to the HPS component and is used to receive the feedback data of the first output power.

[0053] In this embodiment, an ADC module is further included. The ADC module is electrically connected to the HPS component and is used to receive the feedback data of the first output power. Through the feedback data, the system can be further adjusted, thereby improving the scanning accuracy, enhancing the stability of the system, and improving the working efficiency.

[0054] It should be understood that the ADC (Analog-to-Digital Converter) module, as an analog signal input interface, uses MCP3002 as the conversion chip.

[0055] Further, in some embodiments of the present utility model, an isolated IO interface, the isolated IO interface is electrically connected to the FPGA component and is used to connect peripheral devices.

[0056] In this embodiment, an isolated IO interface is further included. The isolated IO interface is electrically connected to the FPGA component and is used to connect peripheral devices. Through the isolated IO interface, the expandability of the system is improved, and new modules or interfaces can be easily expanded to meet the growing demands.

[0057] It should be noted that IO stands for Input / Output, that is, input and output.

[0058] Specifically, the peripheral devices include devices such as buttons, working lights, and stepper motors.

[0059] Specifically, the isolation IO interface serves as a digital input / output interface.

[0060] Furthermore, in some embodiments of the present invention, there is a UART module. The UART module is electrically connected to the HPS module, and the UART module is used to output debugging information.

[0061] In this embodiment, there is also a UART module. The UART module is electrically connected to the HPS module, and the UART module is used to output debugging information. Through the UART module, the debugging result can be understood according to the debugging information, improving the debugging efficiency and the speed of problem solving.

[0062] It should be understood that UART is Universal Asynchronous Receiver / Transmitter, that is, a universal asynchronous transceiver.

[0063] Specifically, the debugging information is LOG information, that is, identification information.

[0064] Furthermore, in some embodiments of the present invention, there is a running memory module. The running memory module is electrically connected to the HPS component; there is also a storage memory module. The storage memory module is electrically connected to the HPS component.

[0065] In this embodiment, there are also a running memory module and a storage memory module. The running memory module is electrically connected to the HPS component, and the storage memory module is electrically connected to the HPS component. Through the running memory module and the storage memory module, the system performance, stability, and security are improved.

[0066] Preferably, the running memory module is connected to the memory controller interface of the HPS component, and 1GB DDR3 RAM is constructed using 2 H5TQ4G63EFR-RDC memory chips as the system running memory.

[0067] Preferably, the storage memory module is connected to the EMMC control interface of the HPS component, and an SD card and a KLM8G1GEME-B041 chip are used to store data.

[0068] Furthermore, in some embodiments of the present invention, there is an RTC module. The RTC module is electrically connected to the HPS component, and the RTC module is used to record the current time.

[0069] In this embodiment, an RTC module is further included. The RTC module is electrically connected to the HPS component, and the RTC module is used to record the current time. By recording the current time through the RTC module, the user experience is optimized.

[0070] In the claims, the description, and the drawings of the present utility model, the term "a plurality of" means two or more, unless otherwise clearly defined. The orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings. It is only for more convenient description of the present utility model and to simplify the description process, rather than to indicate or imply that the device or element referred to must have the specific orientation, be constructed and operated in the specific orientation. Therefore, these descriptions should not be construed as limitations on the present utility model; terms such as "connection", "installation", "fixation", etc. should all be understood in a broad sense. For example, "connection" can be a fixed connection between multiple objects, a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects, or an indirect connection between multiple objects through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to the specific circumstances of the above data.

[0071] In the claims, the description, and the drawings of the present utility model, the description of terms such as "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In the claims, the description, and the drawings of the present utility model, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0072] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. A laser scanning control system based on an SoC FPGA chip, characterized in that, Including: A main control chip, which is at least integrated by an HPS component and an FPGA component; A laser data module, which is electrically connected to the main control chip and is used for laser data exchange; A laser control module, which is electrically connected to the main control chip and is used for controlling a laser and providing laser processing information; A first internal bus, one end of which is connected to the HPS component and the other end is connected to the FPGA component, and the first internal bus can send first data from the HPS component to the FPGA component; A second internal bus, one end of which is connected to the HPS component and the other end is connected to the FPGA component, and the second internal bus can send second data from the HPS component to the FPGA component.

2. The laser scanning control system based on the SoC FPGA chip according to claim 1, characterized in that, The laser data module includes: A CAN module, the first end of which is electrically connected to the HPS component and the second end is connected to an expansion device, and the CAN module is used for data exchange with the expansion device; A data channel module, which is electrically connected to the HPS component and is used for receiving the first data; A control information module, which is electrically connected to the FPGA component and is used for receiving the second data.

3. The laser scanning control system based on the SoC FPGA chip according to claim 2, characterized in that, The data channel module includes: A LAN module, the first end of which is electrically connected to the HPS component and is connected to a host computer; A USB module, the first end of which is electrically connected to the HPS component and is connected to the host computer; Wherein, both the LAN module and the USB module receive the to-be-processed data of the host computer, and both the LAN module and the USB module upload the control state of the laser, and the LAN module serves as the main data channel and the USB module serves as the backup data channel.

4. The laser scanning control system based on the SoC FPGA chip according to claim 1, wherein, The first laser is controlled by an analog signal, and the second laser is controlled by a PWM duty cycle. The laser control module includes: A first control module, the first end of which is electrically connected to the HPS component and the second end is connected to the first laser, and the first control module can control the first output power; A second control module, the first end of which is electrically connected to the FPGA component and the second end is connected to the second laser, and the second control module can control the second output power; Wherein, the first control module is used for outputting an analog signal, and the second control module is used for outputting a PWM duty cycle.

5. The laser scanning control system based on the SoC FPGA chip according to claim 2, wherein, The control information module includes: A scanning head driving module, the first end of the scanning head driving module is electrically connected to the FPGA component, the second end of the scanning head driving module is electrically connected to the laser scanning head, and the scanning head driving module is used to provide a driving signal and receive the status information fed back by the laser scanning head; An encoder input interface, the encoder input interface is electrically connected to the FPGA component, and the encoder input interface is used to provide machining position information.

6. The laser scanning control system based on the SoC FPGA chip according to claim 4, wherein An ADC module, the ADC module is electrically connected to the HPS component and is used to receive the feedback data of the first output power.

7. The laser scanning control system based on the SoC FPGA chip according to any one of claims 1 to 6, wherein An isolated IO interface, the isolated IO interface is electrically connected to the FPGA component and is used to connect peripheral devices.

8. The laser scanning control system based on the SoC FPGA chip according to any one of claims 1 to 6, wherein A UART module, the UART module is electrically connected to the HPS component, and the UART module is used to output debugging information.

9. The laser scanning control system based on the SoC FPGA chip according to any one of claims 1 to 6, wherein A running memory module, the running memory module is electrically connected to the HPS component; A storage memory module, the storage memory module is electrically connected to the HPS component.

10. The laser scanning control system based on the SoC FPGA chip according to any one of claims 1 to 6, wherein An RTC module, the RTC module is electrically connected to the HPS component, and the RTC module is used to record the current time.

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