Wiring packaging structure

Abstract

The utility model provides a routing packaging structure which comprises a frame and a chip, the chip is arranged on the frame, a passivation layer is arranged on the chip, a first opening area is arranged on the passivation layer, and a bonding pad on the chip is led out through the first opening area; a passivation layer is arranged on the chip, a polyimide layer is arranged on the passivation layer, a second opening area is arranged on the polyimide layer corresponding to the first opening area, and a bonding pad on the chip is led out through the second opening area; a bonding pad on the chip is connected with the frame through a conductive lead. The characteristics that the polyimide layer is relatively soft and has better mechanical performance are utilized, and the polyimide layer is arranged on the passivation layer as a stress buffer layer so as to relieve the stress influence on the passivation layer when reliability tests such as temperature circulation are carried out, so that the problem of cracks is avoided, and the service life of the passivation layer is prolonged. And the reliability of the routing type packaging structure is improved. In addition, the requirement for the thickness of the passivation layer is lowered, and the flexibility of thickness setting of the passivation layer is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and particularly relates to a wire bonding packaging structure. Background Art

[0002] Figure 1 As shown in the prior art, a commonly used wire bond packaging structure is provided. A chip 20 is disposed on a base island in a frame 10. A passivation layer 30 is deposited on the outermost layer of the chip 20 (i.e., the side away from the frame 10). Corresponding to the position of pads 40 on the chip 30, an opening area is provided on the passivation layer 30 to expose the pads 40. The exposed pads 40 are then connected to pins in the frame 10 through conductive leads 50. A plastic package 60 is provided on the outermost layer of the wire bond packaging structure. After the packaging is completed, corresponding reliability tests will be carried out on the wire bond packaging structure to verify whether the packaging structure is reliable. The temperature cycle test (i.e., placing the packaged chip in an environment where low temperature and high temperature alternate and cycling a certain number of times, such as 500 times, 1000 times, etc., to simulate the high temperature and low temperature environments that the packaged chip may encounter during actual use, and then evaluating its reliability in this environment) is one of the commonly used test methods to verify the packaging reliability. However, Figure 1 in this wire bond packaging structure during the temperature cycle test, due to the repeated action of temperature stress, near the opening area on the passivation layer 30, the problem of crack is likely to occur. As Figure 2 shown in, cracks 70 appear within the dashed box (where Figure 2 is just a schematic illustration of this crack phenomenon), and the appearance of cracks will affect the electrical performance and the like shown by this packaging structure, and even directly cause the electrical performance of this packaging structure to fail. Moreover, when the thickness of the passivation layer 30 is thinner, its mechanical properties are worse, and the risk of generating cracks is higher. Therefore, it is necessary to improve this type of wire bond packaging structure to solve the problems existing in the prior art. Summary of the Utility Model

[0003] In order to solve the above technical problems, the utility model provides a wire bond packaging structure, which avoids the occurrence of crack problems and improves the reliability of this type of wire bond packaging structure. Moreover, the requirement for the thickness of the passivation layer is reduced, and the flexibility of setting the thickness of the passivation layer is improved.

[0004] According to the first aspect of the utility model, a wire bond packaging structure is provided. The packaging structure includes a frame and a chip. It is characterized in that

[0005] the chip is disposed on the frame, a passivation layer is disposed on the chip, and a first opening area is disposed on the passivation layer to lead out pads on the chip through the first opening area;

[0006] A polyimide layer is provided on the passivation layer. At a position corresponding to the first opening region, a second opening region is provided on the polyimide layer, and the pads on the chip are led out through the second opening region;

[0007] The pads on the chip are connected to the frame through conductive leads.

[0008] Optionally, in the second opening region, the polyimide layer completely covers the passivation layer exposed in the first opening region.

[0009] Optionally, the encapsulation structure further includes a plastic package body, and the plastic package body is disposed on the outermost layer of the encapsulation structure.

[0010] Optionally, the frame includes a plurality of base islands, and a plurality of chips are correspondingly disposed on the plurality of base islands.

[0011] Optionally, the frame includes a plurality of pins, and the pads on the chip are connected to the corresponding pins through the conductive leads.

[0012] Optionally, the pins are flat pins or bent pins.

[0013] Optionally, the chip is connected to the base island in the frame through an adhesive.

[0014] Optionally, a part or all of the side of the base island away from the chip is exposed outside the encapsulation structure.

[0015] Optionally, the thickness of the polyimide layer is 10 microns.

[0016] Optionally, the thickness of the passivation layer is 1.4 microns.

[0017] The beneficial effects of the present utility model at least include:

[0018] A wire bonding packaging structure provided by the present utility model includes a frame and a chip. The chip is disposed on the frame, a passivation layer is provided on the chip, a first opening area is provided on the passivation layer, and the pads on the chip are led out through the first opening area; a polyimide layer is provided on the passivation layer, corresponding to the position of the first opening area, a second opening area is provided on the polyimide layer, and the pads on the chip are led out through the second opening area; the pads on the chip are connected to the frame through conductive leads. The present utility model utilizes the relatively soft and good mechanical properties of the polyimide layer, and sets it as a stress buffer layer on the passivation layer to relieve the stress on the passivation layer during reliability tests such as temperature cycling, thereby avoiding the problem of cracks and improving the reliability of this wire bonding type packaging structure. And it reduces the requirement for the thickness of the passivation layer and improves the flexibility of setting the thickness of the passivation layer.

[0019] Further, in the second opening area, the polyimide layer is provided to completely cover the passivation layer leaking out in the first opening area. By such setting, the present utility model covers the discontinuous passivation layer with poor mechanical properties with the polyimide layer with good stress performance in the opening area, reduces the influence of external temperature and other stresses on the passivation layer during reliability tests, and can further improve the reliability of this wire bonding packaging structure.

[0020] Further, on the basis of providing the polyimide layer, the present utility model can also pass corresponding reliability tests such as temperature cycling for a passivation layer with a relatively thin thickness, for example, a passivation layer of 1.4 microns.

[0021] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present utility model. Description of the Drawings

[0022] Figure 1 Shows a commonly used wire bonding packaging structure in the prior art;

[0023] Figure 2 Shows Figure 1 A schematic diagram of cracks occurring in the wire bonding packaging structure in

[0024] Figure 3 Shows a schematic diagram of the wire bonding packaging structure provided by the present utility model;

[0025] Figure 4 Shows Figure 3 The three-dimensional exploded view of the wire bonding packaging structure in

[0026] Figure 5 Shows Figure 3 The cross-sectional view of the wire bonding packaging structure in

[0027] Figure 6 Another cross-sectional schematic diagram of the wire bonding package structure provided by the present utility model is shown. Detailed implementation manners

[0028] To facilitate the understanding of the present utility model, the present utility model will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present utility model are shown in the drawings. However, the present utility model can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present utility model more thorough and comprehensive.

[0029] In view of the problems existing in the wire bonding type package structure in the prior art, the present utility model provides a new wire bonding package structure. Figure 3 A schematic diagram of a wire bonding package structure provided by the present utility model is shown. Figure 4 As shown corresponding to Figure 3 The three-dimensional exploded schematic diagram of the wire bonding package structure in Figure 5 As shown corresponding to Figure 3 The cross-sectional view along the cross-section AA' direction in Figures 3 - 5 The wire bonding package structure provided by the present utility model will be introduced below in conjunction with

[0030] The wire bonding package structure provided by the present utility model includes a frame 10 and a chip 20 (here, the chip refers to an unencapsulated chip, i.e., a die, also known as a bare chip). The chip 20 is disposed on the base island in the frame 10. A passivation layer 30 is provided on the chip 20. By providing the passivation layer 30, the surface of the chip can be protected, its performance can be improved, foreign impurities can be prevented from entering the interior of the chip, and at the same time, problems such as oxidation and corrosion on the surface of the chip can be avoided, thereby affecting the electrical performance of the chip and enhancing the reliability of the chip operation. A first opening area is provided on the passivation layer 30, and the bonding pads 40 on the chip 20 are led out through the first opening area. In the wire bonding package structure provided by the present utility model, a polyimide layer 80 is provided on the passivation layer 30. Corresponding to the position of the first opening area, a second opening area is provided on the polyimide layer 80, and the bonding pads 40 on the chip 20 are led out through the second opening area. The bonding pads 40 on the chip 20 are connected to the pins in the frame 10 through conductive leads 50. For the wire bonding type of package structure of the present utility model, a polyimide layer is provided on the passivation layer. By utilizing the relatively soft and good mechanical properties of the polyimide layer, it is set as a stress buffer layer on the passivation layer to relieve the stress on the passivation layer during reliability tests such as temperature cycling, thereby avoiding the problem of cracks and enhancing the reliability of the wire bonding type of package structure. In addition, in order to protect the chip, usually there are certain requirements for the thickness of the passivation layer. Based on the setting of the polyimide layer, the present utility model can also pass corresponding reliability tests such as temperature cycling for a passivation layer with a relatively thin thickness. For example, for a 1.4-micron passivation layer, that is, the requirement for the thickness of the passivation layer is reduced, and the flexibility of setting the thickness of the passivation layer is enhanced.

[0031] As Figure 5 shown, the wire bonding package structure further includes a plastic package 60. The plastic package 60 is disposed on the outermost layer of the package structure to cover the chip and the frame, which can protect the chip to a certain extent and prevent it from being affected by the external environment, such as humidity, temperature, dust, etc. Among them, for the sake of easy illustration, the plastic package 60 is not shown in Figure 3 , Figure 4 , but it does not affect those skilled in the art's understanding of this technical solution.

[0032] Furthermore, as Figure 5 shown, in the second opening area, a polyimide layer is provided to completely cover the passivation layer leaking out in the first opening area. Through the above settings, in the opening area, the polyimide layer with better stress performance covers the discontinuous passivation layer with relatively poor mechanical properties, reducing the influence of external temperature and other stresses on the passivation layer during reliability tests, and further enhancing the reliability of the wire bonding package structure.

[0033] Further, the chip 20 is connected to the base island in the frame 10 through an adhesive. The adhesive can be an existing adhesive in the prior art, which will not be introduced in detail here.

[0034] Figure 3 、 Figure 4 Only one chip 20 and its corresponding base island are schematically shown in, but the present invention is not limited thereto. The frame may also include multiple base islands, and multiple chips are correspondingly arranged on the multiple base islands.

[0035] Figure 3 、 Figure 4 shows that the frame 10 has 4 pins, and the pads on the chip are connected to the corresponding pins through conductive leads. It should be noted that the number of pins in the frame can also have other settings, and the specific number can be set according to the actual application scenario. In addition, some pins in the frame can also be connected to the base island according to needs.

[0036] Figure 5 The cross-sectional view shown in is also only an embodiment when the wire bonding package structure of the present invention is adopted Figure 3 in, as shown in Figure 6 is a cross-sectional view of another wire bonding package structure provided by the present invention. At this time, the wire bonding package structure is different from Figure 3 、 Figure 4 , and corresponding deformations can be made to it; in Figure 5 , the pins in the frame are flat pins, Figure 6 in, the pins in the frame are bent pins, and the specific type of pins to be adopted can be set according to the actual application scenario.

[0037] In the present invention, the thickness of the polyimide layer can be set to 10 microns. Of course, the thickness of the polyimide layer can also be set to other values according to needs.

[0038] As another embodiment of the present invention, a part or all of the surface of the base island away from the chip can be exposed outside the package structure; by such a setting, the heat generated by the packaged chip during operation can be transferred to the external PCB circuit board through the base island, improving the heat dissipation characteristics.

[0039] It should be noted that the figures provided herein are only schematic, mainly for facilitating the understanding of the technical solution of the present invention, and do not mean that the present invention is limited only to the structural forms shown in the figures. Corresponding transformation settings can be made according to the actual situation.

[0040] In summary, the wire bonding encapsulation structure provided by the present utility model includes a frame and a chip. The chip is disposed on the frame, a passivation layer is provided on the chip, and a first opening area is provided on the passivation layer to lead out the pads on the chip through the first opening area; a polyimide layer is provided on the passivation layer, and a second opening area is provided on the polyimide layer corresponding to the position of the first opening area to lead out the pads on the chip through the second opening area; the pads on the chip are connected to the frame through conductive leads. The present utility model utilizes the relatively soft and good mechanical properties of the polyimide layer, and sets it as a stress buffer layer on the passivation layer to relieve the influence of the stress on the passivation layer during reliability tests such as temperature cycling, thereby avoiding the problem of crack appearance and improving the reliability of the wire bonding type encapsulation structure. And it reduces the requirement for the thickness of the passivation layer and improves the flexibility of setting the thickness of the passivation layer.

[0041] Further, in the second opening area, the polyimide layer is provided to completely cover the passivation layer exposed in the first opening area. By such setting of the present utility model, in the opening area, the polyimide layer with better stress performance covers the discontinuous passivation layer with poorer mechanical properties, reducing the influence of external temperature and other stresses on the passivation layer during reliability tests, and can further improve the reliability of the wire bonding encapsulation structure.

[0042] Further, on the basis of providing the polyimide layer, the present utility model can also pass corresponding reliability tests such as temperature cycling for a passivation layer with a relatively thin thickness. For example, for a 1.4-micron passivation layer.

[0043] Finally, it should be noted that: Obviously, the above embodiments are merely examples for clearly illustrating the present utility model and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present utility model.

Claims

1. A wire bonding package structure, the package structure comprising a frame and a chip; characterized in that, The chip is disposed on the frame, a passivation layer is disposed on the chip, and a first opening region is disposed on the passivation layer, and the pads on the chip are led out through the first opening region; A polyimide layer is disposed on the passivation layer, and a second opening region is disposed on the polyimide layer corresponding to the position of the first opening region, and the pads on the chip are led out through the second opening region; The pads on the chip are connected to the frame through conductive leads.

2. The package structure according to claim 1, characterized in that, In the second opening region, the polyimide layer completely covers the passivation layer exposed in the first opening region.

3. The package structure according to claim 1, characterized in that, The package structure further includes a plastic package body, and the plastic package body is disposed on the outermost layer of the package structure.

4. The package structure according to claim 1, characterized in that, The frame includes a plurality of base islands, and a plurality of chips are correspondingly disposed on the plurality of base islands.

5. The package structure according to claim 1, characterized in that, The frame includes a plurality of pins, and the pads on the chip are connected to the corresponding pins through the conductive leads.

6. The package structure according to claim 5, characterized in that, The pins are flat pins or bent pins.

7. The package structure according to claim 1, characterized in that, The chip is connected to the base island in the frame through an adhesive.

8. The package structure according to claim 7, characterized in that, A part or all of the side of the base island away from the chip is exposed outside the package structure.

9. The package structure according to claim 1, characterized in that, The thickness of the polyimide layer is 10 microns.

10. The package structure according to claim 1, characterized in that, The thickness of the passivation layer is 1.4 microns.

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