Solar cell and cell module
By printing mark points at different steps in different doping of solar cells, the problem of mark point mask damage is solved, and the printing quality and screen reliability are improved.
Patent Information
- Application Number
- CN202422134067.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-08-30
AI Technical Summary
In the prior art, the mask at the mark point is easily damaged during repeated scraping of the scraper, resulting in damage to the screen plate and affecting printing quality and reliability.
The mark dot is printed in different doped regions in step by step, and is arranged in different doped regions when printing the first gate line and the second gate line respectively to avoid damage to the mask at the mark point.
Improve the reliability of the use of the screen, reduce mask damage during the printing process, and ensure printing quality and efficiency.
Smart Images
Figure CN223168617U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of photovoltaic technology, and particularly relates to a solar cell and a battery module. Background Art
[0002] In the prior art, when manufacturing a back-contact battery, screen printing is performed after various process treatments to form electrodes. The screen consists of warp and weft threads, and the warp and weft threads are perpendicularly crossed. To avoid printing defects at the intersection of the warp and weft threads, the weft threads of the p-region pattern or the n-region pattern are removed during the screen printing process to better complete the grid line printing. Usually, the grid lines of the P region or the n region and the Mark points are printed in the same process step. In this way, the Mark points and the grid lines of the p region or the n region are printed synchronously. During multiple repeated printing processes, the warp threads at the Mark point positions are prone to breakage. Without the support of the warp threads, the mask at the Mark point positions is quickly damaged during the repeated scraping process by the squeegee. The Mark point positions gradually expand, resulting in slurry leakage, and ultimately the screen plate is damaged and unusable. Summary of the Utility Model
[0003] This application provides a solar cell, aiming to solve the problem that in the prior art, the mask at the Mark point positions is quickly damaged during the repeated scraping process by the squeegee, the Mark point positions gradually expand, resulting in slurry leakage, and ultimately the screen plate is damaged and unusable.
[0004] This application is implemented as follows. A solar cell includes a silicon substrate, the silicon substrate includes a plurality of first doping regions and second doping regions that are alternately distributed along a first direction; the first doping regions and the second doping regions extend along a second direction, the first direction and the second direction intersect, a first grid line is arranged in the first doping region, and a second grid line is arranged in the second doping region; a plurality of Mark points, and some of the plurality of Mark points are arranged in the first doping region, and another part of the plurality of Mark points is arranged in the second doping region.
[0005] Optionally, at least part of the plurality of Mark points is arranged between the first grid line and the second grid line.
[0006] Optionally, some of the plurality of Mark points are arranged below the first grid line, and another part of the plurality of Mark points is arranged above the second grid line.
[0007] Optionally, the silicon substrate has a first central axis in the first direction and a second central axis in the second direction. The intersection of the first central axis and the second central axis divides the silicon substrate into a first region, a second region, a third region, and a fourth region. The plurality of mark points at least include a first mark point disposed in the first region, a second mark point disposed in the second region, a third mark point disposed in the third region, and a fourth mark point disposed in the fourth region. Among them, the first mark point, the second mark point, the third mark point, and the fourth mark point are sequentially connected to form a rectangle, and the center point of the rectangle is the positioning reference point.
[0008] Optionally, in the first doping region, the mark point has a first dimension along the first direction, and the first dimension is greater than the width of the first gate line and less than the width of the first doping region.
[0009] Optionally, the ratio of the first dimension to the width of the first doping region is greater than 1 / 5 and less than or equal to 1 / 3.
[0010] Optionally, in the second doping region, the mark point has a second dimension along the first direction, and the second dimension is greater than the width of the second gate line and less than the width of the second doping region.
[0011] Optionally, the ratio of the second dimension to the width of the second doping region is greater than 1 / 5 and less than or equal to 1 / 3.
[0012] Optionally, the silicon substrate further includes an isolation region disposed between the first doping region and the second doping region, and at least some of the plurality of mark points are disposed in the isolation region.
[0013] Optionally, in the isolation region, the mark point has a third dimension along the first direction, and the third dimension is less than the width of the isolation region.
[0014] Optionally, the ratio of the third dimension to the width of the isolation region is greater than or equal to 1 / 3 and less than 1.
[0015] Optionally, the plurality of first doping regions and the plurality of second doping regions are arranged in parallel at intervals along the first direction, and the plurality of first gate lines and the plurality of second gate lines are arranged in parallel at intervals along the first direction.
[0016] Optionally, the first gate line is disposed at the central position of the first doping region, and the second gate line is disposed at the central position of the second doping region.
[0017] Optionally, the ratio of the width of the first gate line to the width of the first doping region is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line to the width of the second doping region is greater than 1 / 10 and less than or equal to 1 / 5.
[0018] In the present application, by disposing some of the plurality of mark points in the first doping region and another part of the plurality of mark points in the second doping region, the mark points can be disposed in the second doping region when printing the first gate line, and the mark points can be disposed in the first doping region when printing the second gate line. The mark points and the gate lines are printed step by step, avoiding the problem that the mask at the mark point position is easily damaged and improving the reliability of the stencil.
[0019] A battery assembly includes the above-mentioned solar cell. The technical effects of the present application are the same as those of the above-mentioned solar cell and will not be elaborated herein. Description of the Drawings
[0020] Figure 1 is a schematic structural diagram of the solar cell provided by the present application;
[0021] Figure 2 is Figure 1 an enlarged schematic view of the structure at A of
[0022] Figure 3 is a schematic diagram of the mark point distribution structure of the solar cell provided by the present application Figure 1 ;
[0023] Figure 4 is a schematic diagram of the mark point distribution structure of the solar cell provided by the present application Figure 2 ;
[0024] Figure 5 is a schematic diagram of the mark point distribution structure of the solar cell provided by the present application Figure 3 ;
[0025] Figure 6 is a schematic diagram of the mark point distribution structure of the solar cell provided by the present application Figure 4 ;
[0026] Figure 7 is a schematic diagram of the mark point distribution structure of the solar cell provided by the present application Figure 5 。
[0027] Description of the Reference Numerals:
[0028] 10. Silicon substrate; 20. First gate line; 30. Second gate line; 40. Mark point; 50. First doping region; 60. Second doping region; 70. Isolation region. Detailed Embodiments
[0029] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as a limitation to the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0030] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.
[0031] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.
[0032] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a connection that allows mutual communication; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0033] In the present application, unless otherwise clearly specified and defined, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath" and "under" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.
[0034] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.
[0035] In an embodiment of the present application, as Figure 1 and Figure 2 shown, a solar cell includes a silicon substrate 10. The silicon substrate 10 can be a P-type silicon substrate 10 or an N-type silicon substrate 10; the silicon substrate 10 can be single-crystalline silicon or polycrystalline silicon. The specific type of the silicon substrate 10 is not limited herein. The silicon substrate 10 includes a plurality of first doping regions 50 and second doping regions 60 that are staggered in a first direction. In some embodiments, the shapes and sizes of the first region and the second region can be the same. For example, both the first region and the second region are rectangles, and the lengths and widths of the first region and the second region are the same. It can be understood that in other embodiments, the shapes of the first region and the second region can be different, and the sizes can also be different. The staggered distribution of the plurality of first doping regions 50 and the plurality of second doping regions 60 in the first direction means that a second region is formed between two adjacent first regions in the first direction, and a first region is formed between two adjacent second regions. The first doping region 50 and the second doping region 60 extend in a second direction, and the first direction and the second direction intersect. In an embodiment of the present application, the second direction intersects the first direction. Specifically, the second direction can be perpendicular to the first direction. Exemplarily, the first direction can be the length direction of the silicon substrate 10, and the second direction can be the width direction of the silicon substrate 10.
[0036] Exemplarily, the formation of the doping region can adopt methods such as ion implantation, diffusion, or vapor deposition to introduce impurity atoms (such as phosphorus, boron, etc.) into specific regions of the silicon substrate 10 to form a doping source region. These impurity atoms will change the conductive properties of the silicon substrate 10, thereby forming the first doping region 50 or the second doping region 60.
[0037] Further, a first gate line 20 is disposed in the first doping region 50, and a second gate line 30 is disposed in the second doping region 60. The first gate line 20 has the same polarity as the first doping region 50. In other words, the first gate line 20 is a P-type fine gate, and the first doping region 50 is a P-type doping region; the first gate line 20 is an N-type fine gate, and the first doping region 50 is an N-type doping region. The second gate line 30 has the same polarity as the second doping region 60. In other words, the second gate line 30 is a P-type fine gate, and the second doping region 60 is a P-type doping region; the second gate line 30 is an N-type fine gate, and the second doping region 60 is an N-type doping region. Additionally, the first gate line 20 can be disposed in the first doping region 50 and the second gate line 30 can be disposed in the second doping region 60 by using a screen printing process. The printing of the first gate line 20 and the second gate line 30 can be carried out sequentially or alternately. The comparison order in this application is not limited. In this way, the setting positions of the first gate line 20 and the second gate line 30 are more accurate, and the efficiency of setting the first gate line 20 and the second gate line 30 is higher. It can be understood that in other embodiments, a coating process can also be used to dispose the first gate line 20 in the first doping region 50 and the second gate line 30 in the second doping region 60, and this application is not limited.
[0038] In some embodiments, a plurality of first doping regions 50 and a plurality of second doping regions 60 are arranged at intervals and alternately in parallel along a first direction, and a plurality of first gate lines 20 and a plurality of second gate lines 30 are arranged at intervals and alternately in parallel along the first direction. The alternating arrangement of the first doping region 50 and the second doping region 60 helps to more effectively collect and separate photo-generated carriers. The alternating arrangement of the first gate line 20 and the second gate line 30 optimizes the current transmission path, reduces resistance loss, improves the current collection efficiency, helps to achieve uniform current distribution on the cell, and reduces the risk of local overheating or performance degradation. Further, the alternating arrangement of the doping region and the gate line helps to form a more stable battery structure and reduces performance degradation caused by material mismatch or stress concentration.
[0039] In the embodiments of this application, further, the first gate line 20 is disposed at the central position of the first doping region 50, and the second gate line 30 is disposed at the central position of the second doping region 60. When the gate line is located at the central position of the doping region, it can more effectively collect the photo-generated carriers generated by the doping region. This layout ensures that the carriers can be quickly and directly transmitted to the two poles of the battery through the gate line, reducing the recombination loss during the transmission process. Since the gate line is precisely placed at the central position of the doping region, this layout minimizes the occlusion of the incident light by the gate line. Compared with the layout where the gate line deviates from the center of the doping region, this design can capture more photons and convert them into electrical energy, thereby improving the photoelectric conversion efficiency.
[0040] In some embodiments, the ratio of the width of the first gate line 20 to the width of the first doped region 50 is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line 30 to the width of the second doped region 60 is greater than 1 / 10 and less than or equal to 1 / 5. Preferably, the ratio of the width of the first gate line 20 to the width of the first doped region 50 is greater than or equal to 1 / 8 and less than or equal to 1 / 6, and the ratio of the width of the second gate line 30 to the width of the second doped region 60 is greater than or equal to 1 / 8 and less than or equal to 1 / 6. In the embodiments of the present application, an appropriate increase in the width of the gate line helps to more effectively collect the photo-generated carriers generated in the doped region. When the ratio of the width of the gate line to the width of the doped region is within the above range, it can ensure that there is sufficient contact area between the gate line and the doped region, thereby reducing the recombination loss of carriers during the transmission process. Although the gate line will block part of the incident light, an appropriate ratio of the width of the gate line to the width of the doped region can balance the relationship between the light shielding loss and the current collection. Too narrow a gate line may result in insufficient current collection, while too wide a gate line will increase the light shielding loss. Within the above ratio range, a balance point can be found to minimize the light shielding loss while ensuring sufficient current collection.
[0041] In some embodiments, a solar cell includes a plurality of mark points 40, and a part of the plurality of mark points 40 is disposed in the first doped region 50, and another part of the plurality of mark points 40 is disposed in the second doped region 60. The mark points 40 serve as positioning references. By automatically identifying the mark points 40 through technologies such as machine vision, it is possible to ensure high-precision alignment in subsequent manufacturing processes (such as printing, coating, etc.).
[0042] In the present application, by disposing a part of the plurality of mark points 40 in the first doped region 50 and another part of the plurality of mark points 40 in the second doped region 60, the mark points 40 can be disposed in the second doped region 60 when printing the first gate line 20, and the mark points 40 can be disposed in the first doped region 50 when printing the second gate line 30. That is to say, when screen-printing the first gate line 20, the mark points 40 at the second doped region 60 are printed synchronously, and when printing the second gate line 30, the mark points 40 at the first doped region 50 are printed synchronously. Compared with the previous screen printing of the mark points 40 of the first gate line 20 and the first doped region 50 simultaneously, or screen printing of the mark points 40 of the second gate line 30 and the second doped region 60 simultaneously, it realizes the misaligned step-by-step printing of the gate line and the mark points 40 in the same region, avoiding the problem that the mask at the position of the mark points 40 in the same region of the printed gate line is easily damaged, and improving the use reliability of the screen.
[0043] Such as Figure 1As shown, further, the silicon substrate 10 has a first central axis L1 in the first direction, and the silicon substrate 10 has a second central axis L2 in the second direction. The intersection of the first central axis L1 and the second central axis L2 divides the silicon substrate 10 into a first region, a second region, a third region, and a fourth region. It can be understood that the first region, the second region, the third region, and the fourth region are of the same size, and the first region, the second region, the third region, and the fourth region respectively occupy the four corners of the silicon substrate 10. The plurality of mark points 40 at least include a first mark point disposed in the first region, a second mark point disposed in the second region, a third mark point disposed in the third region, and a fourth mark point disposed in the fourth region. Among them, the first mark point, the second mark point, the third mark point, and the fourth mark point are connected in sequence to form a rectangle, and the center point of the rectangle is the positioning reference point. Specifically, the number of mark points 40 can be 4, 6, or 8. Exemplarily, the four mark points 40 are arranged in a rectangle, and the sides of the rectangle are parallel to the edges of the silicon wafer. This distribution method can greatly simplify the calculation of the printing position offset and ensure the printing alignment accuracy at the same time. In this embodiment, the screen printing position coordinate information includes the coordinate information of the four mark points 40 after alignment, but is not limited thereto. Specifically, turn on the positioning system, perform image scanning on the solar cell in the laser device to obtain a scanned image; transmit the scanned image obtained by the positioning system to the image processing unit, identify the mark points 40 on the battery surface, calculate the positioning reference point according to the identified mark points 40, and calculate the positioning deviation from the center point of the silicon substrate 10 according to the positioning reference point; according to the positioning deviation and the size parameters of the silicon substrate 10, the adaptive spot control system automatically adjusts the position of the laser working head to the initial position and sets the size and shape of the initial laser spot.
[0044] As Figure 5 , Figure 6 and Figure 7 shown, in some embodiments, at least some of the plurality of mark points 40 are disposed between the first grid line 20 and the second grid line 30. That is to say, some of the plurality of mark points 40 are disposed in the first doping region 50 or the second doping region 60. Some of the plurality of mark points 40 do not contact the first grid line 20 of the first doping region 50, some of the plurality of mark points 40 do not contact the second grid line 30 of the second doping region 60, and some of the plurality of mark points 40 are disposed between the grid lines. Of course, in other embodiments, it may also be that some of the mark points 40 are disposed between the grid lines, and the other part of the mark points 40 are disposed on the grid lines. The setting positions of the mark points 40 can be flexibly arranged, and the present application does not limit this.
[0045] As Figure 3 and Figure 4As shown, in some embodiments, some of the multiple mark points 40 are disposed below the first gate line 20, and another part of the multiple mark points 40 is disposed above the second gate line 30. In the embodiments of the present application, all the mark points 40 are disposed on the gate lines. One part of the mark points 40 is disposed below the first gate line 20, and another part of the mark points 40 is disposed above the second gate line 30. That is to say, the mark points 40 and the gate lines in the same doping region are not on the same layer, and the gate lines and the mark points 40 are a superimposed structural design. In this way, the first gate line 20 in the first doping region 50 and the mark points 40 disposed in the first doping region 50 can be printed separately, and the second gate line 30 in the second doping region 60 and the mark points 40 disposed in the second doping region 60 can be printed separately. That is to say, the second gate line 30 and the mark points 40 in the first doping region 50 are printed synchronously first, and then the first gate line 20 and the mark points 40 at the second doping region 60 are printed synchronously. In this way, the mark points 40 in the first doping region 50 are disposed below the first gate line 20, and the mark points 40 in the second doping region 60 are disposed above the second gate line 30. By printing the first gate line 20 in the first doping region 50 and the mark points 40 disposed in the first doping region 50 separately, and printing the second gate line 30 in the second doping region 60 and the mark points 40 disposed in the second doping region 60 separately, the present application can dispose the mark points 40 in the second doping region 60 when printing the first doping region 50, and dispose the mark points 40 in the first doping region 50 when printing the second doping region 60, avoiding the problem that the mask at the position of the mark points 40 is easily damaged due to the synchronous printing of the mark points 40 and the gate lines in the p region or the n region.
[0046] In some embodiments, within the first doping region 50, the mark points 40 have a first dimension along a first direction, and the first dimension is greater than the width of the first gate line 20 and less than the width of the first doping region 50. The mark points 40 serve as a positioning reference in the manufacturing process, and the design of their dimensions directly affects the positioning accuracy. When the first dimension of the mark points 40 is greater than the width of the first gate line 20, it can be ensured that the mark points 40 can be clearly distinguished from the gate lines during visual recognition or machine positioning, avoiding misrecognition or positioning deviation. At the same time, this dimension is less than the width of the first doping region 50, which means that the mark points 40 do not occupy too much effective optoelectronic conversion region, thereby ensuring the overall performance and stability of the solar panel. Preferably, in the embodiments of the present application, the ratio of the first dimension to the width of the first doping region 50 is greater than 1 / 5 and less than or equal to 1 / 3.
[0047] In some embodiments, within the second doping region 60, the mark point 40 has a second dimension along the first direction, and the second dimension is greater than the width of the second gate line 30 and less than the width of the second doping region 60. The mark point 40 serves as a positioning reference during the manufacturing process, and the design of its dimensions directly affects the positioning accuracy. When the first dimension of the mark point 40 is greater than the width of the second gate line 30, it can ensure that the mark point 40 can be clearly distinguished from the gate line during visual recognition or machine positioning, avoiding misrecognition or positioning deviation. At the same time, this dimension is less than the width of the second doping region 60, meaning that the mark point 40 does not occupy too much effective optoelectronic conversion area, thus ensuring the overall performance and stability of the solar panel. Preferably, in the embodiments of the present application, the ratio of the second dimension to the width of the second doping region 60 is greater than 1 / 5 and less than or equal to 1 / 3.
[0048] In some embodiments, as Figure 6 shown, the silicon substrate 10 further includes an isolation region 70 disposed between the first doping region 50 and the second doping region 60, and multiple mark points 40 are disposed at least partially in the isolation region 70. The main function of the isolation region 70 is to form electrical insulation between the first doping region 50 and the second doping region 60, preventing direct current flow between the two, thereby avoiding the occurrence of short - circuit phenomena. Some of the multiple mark points 40 can be disposed in the isolation region 70, which can achieve effective utilization of the space in the isolation region 70 and also serve as a positioning identifier. Preferably, within the isolation region 70, the mark point 40 has a third dimension along the first direction, and the third dimension is less than the width of the isolation region 70. In the embodiments of the present application, by disposing the mark point 40 in the isolation region 70 and controlling its dimension to be less than the width of the isolation region 70, it is possible to prevent the mark point 40 in the isolation region 70 from causing the adjacent first doping region 50 and second doping region 60 to conduct, avoiding local short - circuit of the solar cell. Preferably, in the embodiments of the present application, the ratio of the third dimension to the width of the isolation region 70 is greater than or equal to 1 / 3 and less than 1. When the ratio of the third dimension to the width of the isolation region 70 is not less than 1 / 3, it can ensure that the mark point 40 has sufficient feature dimensions during the positioning process, thereby reducing the positioning error. Since the dimension of the mark point 40 does not reach the full width of the isolation region 70, the potential impact on the electrical performance and physical integrity of the isolation region 70 during the manufacturing process of the mark point 40 is relatively small. This helps to maintain the stability and reliability of the isolation region 70.
[0049] A battery assembly includes the above - mentioned solar cell. Based on the above - mentioned solar cell, those skilled in the art know that by using multiple such solar cells and / or other corresponding existing accessories, the corresponding battery assembly can be obtained.
[0050] In the description of this specification, the descriptions referring to terms such as "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0051] The above are only the preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.
Claims
1. A solar cell, characterized in that, It includes a silicon substrate, and the silicon substrate includes a plurality of first doping regions and second doping regions which are staggered and distributed in a first direction; the first doping regions and the second doping regions extend in a second direction, the first direction and the second direction intersect, a first gate line is arranged in the first doping regions, and a second gate line is arranged in the second doping regions; a plurality of mark points, and a part of the plurality of mark points are arranged in the first doping regions, and another part of the plurality of mark points are arranged in the second doping regions.
2. The solar cell according to claim 1, characterized in that, At least a part of the plurality of mark points are arranged between the first gate line and the second gate line.
3. The solar cell according to claim 1, characterized in that, A part of the plurality of mark points are arranged below the first gate line, and another part of the plurality of mark points are arranged above the second gate line.
4. The solar cell according to claim 1, characterized in that, The silicon substrate has a first central axis in the first direction, and the silicon substrate has a second central axis in the second direction. The intersection of the first central axis and the second central axis divides the silicon substrate into a first region, a second region, a third region and a fourth region. The plurality of mark points at least include a first mark point arranged in the first region, a second mark point arranged in the second region, a third mark point arranged in the third region and a fourth mark point arranged in the fourth region. Among them, the first mark point, the second mark point, the third mark point and the fourth mark point are connected in sequence to form a rectangle, and the center point of the rectangle is the positioning reference point.
5. The solar cell according to claim 1, characterized in that, In the first doping regions, the mark points have a first dimension in the first direction, and the first dimension is greater than the width of the first gate line and less than the width of the first doping regions.
6. The solar cell according to claim 5, characterized in that, The ratio of the first dimension to the width of the first doping regions is greater than 1 / 5 and less than or equal to 1 / 3.
7. The solar cell according to claim 1, wherein In the second doping regions, the mark points have a second dimension in the first direction, and the second dimension is greater than the width of the second gate line and less than the width of the second doping regions.
8. The solar cell according to claim 7, characterized in that, The ratio of the second dimension to the width of the second doping regions is greater than 1 / 5 and less than or equal to 1 / 3.
9. The solar cell according to claim 1, characterized in that, The silicon substrate further includes an isolation region arranged between the first doping regions and the second doping regions, and at least a part of the plurality of mark points are arranged in the isolation region.
10. The solar cell according to claim 9, characterized in that, In the isolation region, the mark points have a third dimension in the first direction, and the third dimension is less than the width of the isolation region.
11. The solar cell according to claim 10, characterized in that, The ratio of the third dimension to the width of the isolation region is greater than or equal to 1 / 3 and less than 1.
12. The solar cell according to claim 1, wherein The plurality of first doping regions and the plurality of second doping regions are arranged at intervals and alternately in parallel in the first direction, and the plurality of first gate lines and the plurality of second gate lines are arranged at intervals and alternately in parallel in the first direction.
13. The solar cell according to claim 12, wherein, The first gate line is arranged at the central position of the first doping regions, and the second gate line is arranged at the central position of the second doping regions.
14. The solar cell according to claim 1, characterized in that, The ratio of the width of the first gate line to the width of the first doping regions is greater than 1 / 10 and less than or equal to 1 / 5, and the ratio of the width of the second gate line to the width of the second doping regions is greater than 1 / 10 and less than or equal to 1 / 5.
15. A battery assembly, characterized in that, Comprising the solar cell according to any one of claims 1-14 above.