Display device

Abstract

A display device includes: a substrate having a first side surface adjacent to an upper surface, a second side surface adjacent to a lower surface, and an opening surrounded by the second side surface; a pad cladding surrounded by the first side surface of the substrate and including a pad contact hole; a pad disposed on the pad cladding and inserted into the pad contact hole; a fan-out line disposed on the pad and electrically connected to the pad; a transistor electrically connected to the fan-out line; and a flexible film disposed under the substrate and including a lead electrode inserted in the opening of the substrate and in contact with the pad.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the same. Background Art

[0002] With the development of an information society, various demands for display devices are continuously increasing. For example, display devices are being adopted by various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, a self-emitting display device includes a light emitting element that can emit light by itself, so that each pixel in the pixels of the display panel can emit light by itself. Therefore, the self-emitting display device can display an image without a backlight unit that supplies light to the display panel. Summary of the Invention

[0003] A feature of the present disclosure provides a display device and a method of manufacturing the same, in which a pad provided on a substrate and a flexible film provided under the substrate can be electrically connected.

[0004] A feature of the present disclosure also provides a display device and a method of manufacturing the same, which can save manufacturing time and cost by reducing a non-display area and simplifying a manufacturing process.

[0005] It should be noted that the features of the present disclosure are not limited to the above features; and other features of the present disclosure will be apparent to those skilled in the art from the following description.

[0006] In an embodiment of the present disclosure, a display device includes: a substrate including a first side surface adjacent to an upper surface and a second side surface adjacent to a lower surface, and an opening surrounded by the second side surface is defined in the substrate; a pad cladding surrounded by the first side surface of the substrate and including a pad contact hole; a pad provided on the pad cladding and inserted into the pad contact hole; a fan-out line provided on the pad and electrically connected to the pad; a transistor electrically connected to the fan-out line; and a flexible film provided under the substrate and including a lead electrode inserted into the opening of the substrate and contacting the pad.

[0007] In an embodiment, the display device may further include: a contact portion covering a lower surface of the lead electrode and a lower surface of the pad to electrically connect the lead electrode and the pad.

[0008] In an embodiment, the lead electrode may protrude from one side of the flexible film. The contact portion may cover the lower surface of the lead electrode protruding from the flexible film.

[0009] In an embodiment, an upper surface of the pad cladding may be flush with an upper surface of the substrate.

[0010] In one embodiment, the pad cladding may include at least one of polyimide (“PI”), silicon nitride (SiN x ), and silicon (Si).

[0011] In one embodiment, the pad may be exposed through an opening in the substrate.

[0012] In one embodiment, a first side surface of the substrate may be inclined at a first angle with respect to a plane that is the same as the plane of the upper surface of the substrate, and a second side surface of the substrate may be inclined at a second angle with respect to a plane that is the same as the lower surface of the substrate. The first angle may be less than the second angle.

[0013] In one embodiment, the vertical height of the first side surface may be less than the vertical height of the second side surface.

[0014] In one embodiment, the contact portion may be formed using a metal paste including silver (Ag) or copper (Cu) or consisting of silver (Ag) or copper (Cu).

[0015] In one embodiment, a display device may include a display area for displaying an image and a non-display area surrounding the display area. The pads and the flexible film may be disposed in the display area.

[0016] In one embodiment, a display device may further include a display area for displaying an image, a non-display area surrounding the display area, and a display driver disposed on the flexible film and applying a data voltage to a transistor. The pads and the fan-out lines may be disposed in the non-display area, and the display driver may be disposed in the display area.

[0017] In one embodiment, a display device may further include a transistor layer including transistors, a light-emitting element layer disposed on the transistor layer and including light-emitting elements, and a package layer covering the upper surface and side surfaces of the light-emitting element layer.

[0018] In one embodiment, a display device may further include: a transistor layer including transistors; a light-emitting element layer disposed on the transistor layer and including light-emitting elements; a package substrate disposed on the light-emitting element layer; and a sealing member disposed along the edges of both the substrate and the package substrate between the substrate and the package substrate to attach the substrate and the package substrate to each other.

[0019] In an embodiment of the present disclosure, a method of manufacturing a display device includes: providing a substrate, defining a groove in the substrate by performing a first etching process on an upper surface of the substrate, forming a pad cladding accommodated in the groove and including a pad contact hole, forming a pad disposed on the pad cladding and inserted into the pad contact hole, forming a transistor on the pad and forming fan-out lines electrically connecting the pad and the transistor, defining an opening exposing the pad by performing a secondary etching process on a lower surface of the substrate, and inserting one side of a flexible film into the opening to bring a lead electrode of the flexible film into contact with the pad.

[0020] In an embodiment, the method may further include: forming a contact portion electrically connecting the pad and the lead electrode by covering a part of the pad and a part of the lead electrode.

[0021] In an embodiment, forming the contact portion may include: printing a metal paste on the opening of the substrate and then sintering the metal paste.

[0022] In an embodiment, forming the contact portion may further include: separating the sintered metal paste into a plurality of contact portions via a laser patterning process.

[0023] In an embodiment, forming the pad cladding may include: setting an upper surface of the pad cladding such that the upper surface of the pad cladding is flush with the upper surface of the substrate.

[0024] In an embodiment, defining the groove in the substrate may include: forming a first side surface that is inclined at a first angle in a plane the same as a plane of the upper surface of the substrate. Defining the opening may include: forming a second side surface that is inclined at a second angle in a plane the same as a plane of the lower surface of the substrate. The first angle may be less than the second angle.

[0025] In an embodiment, a thickness of the pad cladding may be less than a depth of the opening.

[0026] In an embodiment of the present disclosure, the pad cladding may be formed in a groove of the substrate formed by a first etching process of the substrate, the pad may be inserted into the pad contact hole of the pad cladding, the lead electrode of the flexible film may be inserted into the opening of the substrate formed by a second etching process of the substrate such that the lead electrode may contact the pad, and the pad disposed on the substrate may be electrically connected to the flexible film disposed under the substrate.

[0027] In an embodiment of the present disclosure, a non-display area may be reduced by including a flexible film and a display driver disposed under the substrate. In a manner of fixing the lead electrode and the pad with a contact portion of a metal paste and making an electrical connection therebetween, the manufacturing process may be simplified without using ultrasonic bonding or thermocompression bonding, so that manufacturing time and cost may be saved.

[0028] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be obvious to those skilled in the art according to the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other advantages and features of the present disclosure will become more apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a plan view showing an embodiment of a display device according to the present disclosure.

[0031] Figure 2 is a cross-sectional view showing an embodiment of a display device according to the present disclosure.

[0032] Figure 3 is a cross-sectional view showing an embodiment of a display device according to the present disclosure.

[0033] Figure 4 is a cross-sectional view taken along the line I-I'. Figure 1 of

[0034] Figure 5 is an enlarged view of Figure 4 region A1 of

[0035] Figure 6 is a view showing the bottom of an embodiment of a display device according to the present disclosure.

[0036] Figure 7 is an enlarged view of an embodiment of a part of the bottom of a display device in an embodiment of the present disclosure.

[0037] Figure 8 is a view showing an embodiment of the bottom of a display device according to the present disclosure.

[0038] Figure 9 is a circuit diagram showing an embodiment of a pixel of a display device according to the present disclosure.

[0039] Figures 10 to 15 is a cross-sectional view showing an embodiment of a process operation for manufacturing a display device according to the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, and they are non-limiting embodiments of a device or method that employs one or more of the disclosures herein. However, it will be apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments. Further, the various embodiments may be different, but they do not have to be exclusive or limit the present disclosure. For example, without departing from the present disclosure, the specific shapes, configurations, and characteristics of one embodiment may be used or implemented in other embodiments.

[0041] Unless otherwise specified, the illustrated embodiments should be understood to provide features of different details of some ways in which the present disclosure may be implemented in practice. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or characteristics, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged in other ways without departing from the present disclosure.

[0042] The use of cross-hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Accordingly, the presence or absence of cross-hatching or shading does not convey or indicate a preference or requirement for a particular material, material properties, dimensions, ratios, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements, unless stated.

[0043] Further, in the accompanying drawings, for purposes of clarity and / or description, the sizes and relative sizes of the elements may be enlarged. When an embodiment can be implemented differently, the specific process order may be performed in a different order than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Also, the same reference numerals denote the same elements.

[0044] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. To this end, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0045] Further, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and thus are not limited to the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0046] For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, or ZZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0048] Spatial relative terms, such as "beneath", "below", "lower", "under", "above", "upper", "on top of", "higher", and "side" (e.g., as in "sidewall") etc. may be used herein for descriptive purposes to describe the relationship of one element to another as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations in use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element or feature described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can include both an above and a below orientation. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0049] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. Additionally, the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and thus are used to account for the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0050] Various embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein are not necessarily to be construed as limited to a particular illustrated region shape, but include, for example, shape deviations resulting from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shape of the regions of the device and are therefore not necessarily intended to be limiting.

[0051] In accordance with the convention in the art, some embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, parts, and / or modules. Those skilled in the art will understand that these blocks, units, parts, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, parts, and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, part, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Additionally, without departing from the scope of the present disclosure, each block, unit, part, and / or module of some embodiments may be physically divided into two or more interacting and discrete blocks, units, parts, and / or modules. Further, without departing from the scope of the present disclosure, the blocks, units, parts, and / or modules of some embodiments may be physically combined into more complex blocks, units, parts, and / or modules.

[0052] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the relevant art and the context of this disclosure, and should not be interpreted in an ideal or overly formal sense unless expressly so defined herein.

[0053] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0054] Figure 1 FIG. [X] is a plan view showing an embodiment of a display device according to the present disclosure.

[0055] See Figure 1, the display device 10 can be adopted by portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), mobile communication terminals, electronic notebooks, e-books, portable multimedia players ("PMPs"), navigation devices, and ultra-mobile PCs ("UMPCs"). In another embodiment, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things ("IoT") device. In another embodiment, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted display ("HMD") devices.

[0056] When viewed from the top, the display device 10 can have a shape similar to a quadrilateral shape. In one embodiment, for example, the corners where the sides in the x-axis direction and the sides in the y-axis direction intersect each other can be rounded to have a predetermined curvature or can be formed at right angles, for example. When viewed from the top, the shape of the display device 10 is not limited to a quadrilateral shape, but can be formed into a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0057] The display device 10 can include a display area DA and a non-display area NDA. The display area DA can include a plurality of pixels to display an image. Each of the plurality of pixels can include an organic light-emitting diode ("LED") including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, or a micro-LED. In the following description, each of the pixels includes an organic LED. However, it should be understood that the present disclosure is not limited thereto.

[0058] The pixels can be arranged in rows and columns in the display area DA. Each of the pixels can include an emission area EA defined by a pixel defining film or a bank, and can emit light having a predetermined peak wavelength through the emission area EA. In the emission area EA, the light generated by the light-emitting elements of the display device 10 is emitted from the display device 10.

[0059] The display area DA of the display device 10 can include a light-blocking area BA surrounding the plurality of emission areas EA. The light-blocking area BA can prevent color mixing of the light output from the emission areas EA.

[0060] A non-display area NDA can be set around a display area DA to surround the display area DA and may not display an image. The non-display area NDA can include a scan driver SIC that provides a scan signal to the display area DA. The scan driver SIC can be set on the left and right sides of the non-display area NDA. The scan driver SIC can generate a scan signal based on a scan control signal. The scan control signal can include, but is not limited to, a start signal, a clock signal, and a power supply voltage. The scan driver SIC can provide the scan signal to the scan lines of the display area DA in a predetermined order.

[0061] Figure 2 FIG. is a cross-sectional view showing an embodiment of a display device according to the present disclosure.

[0062] See Figure 2 , the display panel 100 can include a display unit DU, a touch sensing unit TSU, and a polarizing film POL. The display unit DU can include a substrate SUB, a transistor layer TRL, a light-emitting element layer EML, and a packaging layer TFEL.

[0063] The substrate SUB can be a base substrate or a base member. In one embodiment, the substrate SUB can be, but is not limited to, for example, a rigid substrate including a glass material or a metal material. In another embodiment, the substrate SUB can be a flexible substrate including a polymer resin, such as polyimide (“PI”).

[0064] The transistor layer TRL can be set on the substrate SUB. The transistor layer TRL can include a plurality of transistors forming a pixel circuit of a pixel. The transistor layer TRL can include scan lines, data lines, and power lines connected to the pixel. Each of the transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In one embodiment, when the scan driver SIC is formed on one side of the non-display area NDA of the display panel 100, the scan driver SIC can include, for example, a transistor.

[0065] The transistor layer TRL can be set in the display area DA and the non-display area NDA. The transistors, scan lines, data lines, and power lines in the transistor layer TRL for the pixel can be set in the display area DA. The transistors of the scan driver SIC can be set in the non-display area NDA.

[0066] The light-emitting element layer EML can be set on the transistor layer TRL. The light-emitting element layer EML can include a plurality of light-emitting elements and a pixel defining film for defining a pixel. In each of the plurality of light-emitting elements, a pixel electrode, an emission layer, and a common electrode are stacked on each other in sequence to emit light. The plurality of light-emitting elements in the light-emitting element layer EML can be set in the display area DA.

[0067] In one embodiment, for example, the emission layer may be an organic light-emitting layer including or consisting of an organic material. The emission layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage through a transistor in the transistor layer TRL and the common electrode receives a cathode voltage through the transistor, holes may move through the hole transport layer to the organic light-emitting layer, and electrons may move through the electron transport layer to the organic light-emitting layer, such that they combine in the organic light-emitting layer to emit light. In one embodiment, for example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode. However, it should be understood that the present disclosure is not limited thereto.

[0068] In another embodiment, the light-emitting element may include quantum dot LEDs each including a quantum dot emission layer, inorganic LEDs each including an inorganic semiconductor, or micro LEDs.

[0069] The encapsulation layer TFEL may cover the upper surface and side surfaces of the light-emitting element layer EML and may protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer EML.

[0070] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing a user touch through capacitance sensing and a touch line for providing a touch driving signal to the plurality of touch electrodes. In one embodiment, for example, the touch sensing unit TSU may sense a user touch through mutual capacitance sensing or self-capacitance sensing.

[0071] The plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping with the display area DA. The touch line of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping with the non-display area NDA.

[0072] The polarizing film POL may be disposed on the touch sensing unit TSU. The polarizing film POL may be attached to the touch sensing unit TSU through an optically clear adhesive (“OCA”) film or an optically clear resin (“OCR”). In one embodiment, for example, the polarizing film POL may include a linear polarizer and a retardation film. The retardation film may be a λ / 4 plate (quarter-wave plate). The retardation film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The polarizing film POL may reduce reflection of external light to prevent color distortion caused by reflection of external light.

[0073] The opening SOP can be defined in the substrate SUB. The opening SOP of the substrate SUB can be etched so as to penetrate from the lower surface of the substrate SUB to the upper surface of the substrate SUB. In one embodiment, for example, the width of the bottom of the opening SOP can be greater than the width of the top of the opening SOP. During the process of manufacturing the display device 10, the pads provided in the transistor layer TRL can be exposed through the opening SOP of the substrate SUB. The pads can be electrically connected to the display driver DIC through the flexible film FPCB inserted into the opening SOP.

[0074] The flexible film FPCB can be provided under the substrate SUB. A part of the flexible film FPCB can be inserted into the opening SOP of the substrate SUB and electrically connected to the pads. Another part of the flexible film FPCB can be attached to the lower surface of the substrate SUB. The flexible film FPCB can support the display driver DIC. The flexible film FPCB can transmit signals and voltages from the display driver DIC to the transistor layer TRL. The flexible film FPCB can supply a scan control signal to the scan driver SIC.

[0075] The display driver DIC can be provided (e.g., mounted) on the flexible film FPCB. The display driver DIC can be an integrated circuit (“IC”). The display driver DIC can convert digital video data into an analog data voltage based on a data control signal from a timing controller (not shown), and can supply the analog data voltage to the data lines in the display area DA through the flexible film FPCB. The display driver DIC can supply a power voltage received from a power supply unit (not shown) to the power lines in the display area DA through the flexible film FPCB. Since the display device 10 includes the flexible film FPCB and the display driver DIC provided in the display area DA and under the substrate SUB, the non-display area NDA can be reduced.

[0076] Figure 3 FIG. is a cross-sectional view showing an embodiment of a display device according to the present disclosure.

[0077] Referring to Figure 3 , the display panel 100 can include a first substrate SUB1, a transistor layer TRL, a light-emitting element layer EML, a sealing member SEAL, and a second substrate SUB2.

[0078] The first substrate SUB1 can be a base substrate or a base member. In one embodiment, the first substrate SUB1 can be, but is not limited to, for example, a rigid substrate including a glass material or a metal material. In another embodiment, the first substrate SUB1 can be a flexible substrate including a polymer resin, such as PI.

[0079] The transistor layer TRL can be disposed in the display area DA and on the first substrate SUB1. The transistor layer TRL can include a plurality of transistors forming a pixel circuit of a pixel. The transistor layer TRL can include scan lines, data lines, and power lines connected to the pixel. Each of the transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode.

[0080] The light-emitting element layer EML can be disposed on the transistor layer TRL. The light-emitting element layer EML can include a plurality of light-emitting elements and a pixel defining film for defining a pixel. In each of the plurality of light-emitting elements, a pixel electrode, an emission layer, and a common electrode are sequentially stacked on each other to emit light. The plurality of light-emitting elements in the light-emitting element layer EML can be disposed in the display area DA.

[0081] The sealing member SEAL can be disposed between the first substrate SUB1 and the second substrate SUB2. The sealing member SEAL can be disposed along the edge of the non-display area NDA and can attach the first substrate SUB1 and the second substrate SUB2 together. The sealing member SEAL can protect the side surface of the display panel 100.

[0082] The second substrate SUB2 can be disposed on the first substrate SUB1 to protect the transistor layer TRL and the light-emitting element layer EML. The second substrate SUB2 can be a packaging substrate for packaging the transistor layer TRL and the light-emitting element layer EML. In one embodiment, for example, the second substrate SUB2 can include, but is not limited to, a glass material or a metal material.

[0083] An opening SOP can be defined in the first substrate SUB1. The opening SOP of the first substrate SUB1 can be etched to penetrate from the lower surface of the first substrate SUB1 to the upper surface of the first substrate SUB1. In one embodiment, for example, the width of the bottom of the opening SOP can be greater than the width of the top of the opening SOP. During the process of manufacturing the display device 10, pads disposed in the transistor layer TRL can be exposed through the opening SOP of the first substrate SUB1. The pads can be electrically connected to the display driver DIC through a flexible film FPCB inserted into the opening SOP.

[0084] The flexible film FPCB can be disposed under the first substrate SUB1. A part of the flexible film FPCB can be inserted into the opening SOP of the first substrate SUB1 and electrically connected to the pads. Another part of the flexible film FPCB can be attached to the lower surface of the first substrate SUB1. The flexible film FPCB can support the display driver DIC. The flexible film FPCB can transmit signals and voltages from the display driver DIC to the transistor layer TRL.

[0085] The display driver DIC can be disposed (e.g., mounted) on the flexible film FPCB. The display driver DIC can be an IC. The display driver DIC can convert digital video data into analog data voltage based on a data control signal from a timing controller (not shown), and can supply the analog data voltage to data lines in the display area DA through the flexible film FPCB. The display driver DIC can supply a power voltage received from a power supply unit (not shown) to power lines in the display area DA through the flexible film FPCB. Since the display device 10 includes the flexible film FPCB and the display driver DIC disposed below the first substrate SUB1, the non-display area NDA can be reduced.

[0086] Figure 4 For a cross-sectional view taken along Figure 1 the center line I-I'. Figure 5 is Figure 4 an enlarged view of region A1 of

[0087] See Figure 4 and Figure 5 , the display area DA of the display device 10 can include a plurality of emission regions EA. In each of the emission regions EA, light generated by the light-emitting element ED exits the display device 10.

[0088] The display device 10 can include a substrate SUB, a transistor layer TRL, a light-emitting element layer EML, a packaging layer TFEL, a touch sensing unit TSU, a polarizing film POL, a flexible film FPCB, and a display driver DIC.

[0089] The substrate SUB can support the display device 10. The substrate SUB can be a base substrate or a base member. In one embodiment, the substrate SUB can be, but is not limited to, for example, a rigid substrate including a glass material or a metal material. In another embodiment, the substrate SUB can be a flexible substrate including a polymer resin such as PI.

[0090] An opening SOP can be defined in the substrate SUB. The opening SOP of the substrate SUB can be etched to penetrate from the lower surface of the substrate SUB to the upper surface of the substrate SUB. In one embodiment, for example, the width of the bottom of the opening SOP can be greater than the width of the top of the opening SOP. During the process of manufacturing the display device 10, the pad PAD can be exposed through the opening SOP of the substrate SUB. The pad PAD can be electrically connected to the display driver DIC through the flexible film FPCB inserted into the opening SOP.

[0091] In Figure 5In this case, the first side surface SUBa of the substrate SUB can be formed via a first etching process of the substrate SUB, and the second side surface SUBb of the substrate SUB can be formed via a second etching process of the substrate SUB. The first side surface SUBa of the substrate SUB can surround the pad cladding PCL, and the second side surface SUBb of the substrate SUB can surround the opening SOP. The first side surface SUBa of the substrate SUB can be formed by etching from the upper surface of the substrate SUB, and the second side surface SUBb of the substrate SUB can be formed by etching from the lower surface of the substrate SUB. The first side surface SUBa of the substrate SUB can be adjacent to the upper surface of the substrate SUB, and the second side surface SUBb of the substrate SUB can be adjacent to the lower surface of the substrate SUB. The second side surface SUBb of the substrate SUB can be disposed between the first side surface SUBa and the lower surface of the substrate SUB. The first side surface SUBa of the substrate SUB can be inclined at a first angle θ1 with respect to a plane identical to the plane of the upper surface of the substrate SUB. The second side surface SUBb of the substrate SUB can be inclined at a second angle θ2 with respect to a plane identical to the plane of the lower surface of the substrate SUB. The first angle θ1 of the first side surface SUBa can be smaller than the second angle θ2 of the second side surface SUBb. The vertical height T1 of the first side surface SUBa can be smaller than the vertical height T2 of the second side surface SUBb. The vertical height T1 of the first side surface SUBa can be equal to the thickness of the pad cladding PCL, and the vertical height T2 of the second side surface SUBb can be equal to the depth of the opening SOP. The sum of the vertical height T1 of the first side surface SUBa and the vertical height T2 of the second side surface SUBb can be equal to the thickness of the substrate SUB. In one embodiment, for example, the vertical height T1 of the first side surface SUBa can be approximately 1 micrometer (μm) to approximately 10 μm, and the vertical height T2 of the second side surface SUBb can be 180 μm or more, but the respective thicknesses are not limited thereto.

[0092] The pad cladding PCL can be surrounded by the first side surface SUBa of the substrate SUB. The pad cladding PCL can be accommodated in a groove defined in the first etching process of the substrate SUB. The upper surface of the pad cladding PCL can be flush with the upper surface of the substrate SUB, but the present disclosure is not limited thereto. The pad cladding PCL can include a pad contact hole PCT that overlaps with the opening SOP of the substrate SUB. In the second etching process of the substrate SUB, the pad cladding PCL can protect a part of the pad PAD that is not inserted into the pad contact hole PCT. After the second etching process of the substrate SUB is completed, the pad contact hole PCT of the pad cladding PCL can expose another part of the pad PAD that is inserted into the pad contact hole PCT. Since the display device 10 can include the pad cladding PCL, the transistor layer TRL including the pad PAD can be protected in the second etching process of the substrate SUB. In one embodiment, for example, the pad cladding PCL can include, but is not limited to, a polymer resin such as PI or an insulating material such as silicon nitride (SiN x ) and silicon (Si).

[0093] The transistor layer TRL can be disposed on the substrate SUB and the pad cladding PCL. The transistor layer TRL can include a first metal layer MTL1, a buffer layer BF, an active layer ACTL, a gate insulator GI, a second metal layer MTL2, an interlayer dielectric layer ILD, a third metal layer MTL3, a passivation layer PAS, and a via layer VIA.

[0094] The first metal layer MTL1 can be disposed on the substrate SUB and the pad cladding PCL. The first metal layer MTL1 can include the pad PAD and a light blocking layer BML. The first metal layer MTL1 can include a single layer or multiple layers or be composed of a single layer or multiple layers, and the single layer or multiple layers include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), platinum (Pt), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), tungsten (W), and copper (Cu).

[0095] The pad PAD can be disposed on the pad cladding PCL and inserted into the pad contact hole PCT formed in the pad cladding PCL. The pad PAD can electrically connect the flexible film FPCB to the fan-out line FOL. The pad PAD can be exposed through the opening SOP of the substrate SUB. A part of the pad PAD can contact the lead electrode LDE of the flexible film FPCB, and another part of the pad PAD can be electrically connected to the lead electrode LDE of the flexible film FPCB through the contact part CTP.

[0096] The light blocking layer BML can be disposed on the substrate SUB. The light blocking layer BML can overlap with the semiconductor region ACT of the transistor TR. The light blocking layer BML can block light incident from below the transistor TR.

[0097] The buffer layer BF may be disposed on the first metal layer MTL1, the substrate SUB, and the pad cladding PCL. The buffer layer BF may include an inorganic material that can prevent the penetration of air or moisture. For example, in one embodiment, the buffer layer BF may include a plurality of inorganic films stacked alternately on each other. The buffer layer BF may define contact holes through which the fan-out line FOL passes.

[0098] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include a semiconductor region ACT, a drain electrode DE, and a source electrode SE of the transistor TR. The semiconductor region ACT may overlap the gate electrode GE in the thickness direction (z-axis direction) and may be insulated from the gate electrode GE by the gate insulator GI. The drain electrode DE and the source electrode SE may be formed by making the material of the semiconductor region ACT conductive. The transistor TR may form the pixel circuit of each pixel in the plurality of pixels.

[0099] The gate insulator GI may be disposed on the active layer ACTL and the buffer layer BF. The gate insulator GI may insulate between the semiconductor region ACT of the transistor TR and the gate electrode GE. The gate insulator GI may define contact holes through which the fan-out line FOL and the connection electrode CNE pass.

[0100] The second metal layer MTL2 may be disposed on the gate insulator GI. The second metal layer MTL2 may include the gate electrode GE of the transistor TR. The gate electrode GE may overlap the semiconductor region ACT, with the gate insulator GI therebetween. The gate electrode GE may receive a scan signal from the scan line. In one embodiment, for example, the second metal layer MTL2 may include a single layer or multiple layers or be composed of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0101] The interlayer dielectric layer ILD may be disposed on the second metal layer MTL2. The interlayer dielectric layer ILD may insulate between the second metal layer MTL2 and the third metal layer MTL3. The interlayer dielectric layer ILD may define contact holes through which the fan-out line FOL and the connection electrode CNE pass.

[0102] The third metal layer MTL3 can be disposed on the interlayer dielectric layer ILD. The third metal layer MTL3 can include fan-out lines FOL, connection electrodes CNE, data lines DL, and voltage lines VL. The fan-out lines FOL, connection electrodes CNE, data lines DL, and voltage lines VL can include the same material or be composed of the same material in the same layer. In one embodiment, for example, the third metal layer MTL3 can include a single layer or multiple layers or be composed of a single layer or multiple layers, and the single layer or multiple layers include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0103] The fan-out lines FOL can be inserted into the contact holes penetrating the interlayer dielectric layer ILD, the gate insulator GI, and the buffer layer BF to be connected to the pads PAD. The fan-out lines FOL can overlap with at least one emission region EA. The fan-out lines FOL can be electrically connected to the data lines DL or the voltage lines VL in the display region DA, or the scan driver SIC in the non-display region NDA. In one embodiment, for example, the fan-out lines FOL can be electrically connected to the data lines DL to supply a data voltage to the transistor TR. The fan-out lines FOL can be electrically connected to the voltage lines VL to supply a power voltage to the transistor TR. The fan-out lines FOL can be electrically connected to the scan driver SIC to supply a scan control signal to the scan driver SIC. The data lines DL and the voltage lines VL in the display region DA can be electrically connected to the transistor TR, and the scan driver SIC can generate a scan signal. Therefore, the fan-out lines FOL can apply the data voltage or the power voltage received from the display driver DIC on the flexible film FPCB to the transistor TR of the pixel, and can supply it to the scan driver SIC through the scan control signal received from the flexible film FPCB. Since the display device 10 includes the fan-out lines FOL disposed in the display region DA, the non-display region NDA can be reduced.

[0104] The connection electrodes CNE can electrically connect the source electrode SE of the transistor TR to the pixel electrode AE of the light-emitting element ED. The connection electrodes CNE can be inserted into the contact holes penetrating the interlayer dielectric layer ILD and the gate insulator GI to be connected to the source electrode SE of the transistor TR. The connection electrodes CNE can supply the drive current received from the pixel circuit to the light-emitting element ED.

[0105] The data lines DL can extend in the y-axis direction in the display region DA. The data lines DL can be electrically connected to the drain electrode DE or the gate electrode GE of the transistor TR. Therefore, the data lines DL can apply a data voltage to the transistor TR.

[0106] The voltage line VL may extend in the y-axis direction in the display area DA. The voltage line VL may be electrically connected to the transistor TR or the light-emitting element ED. In one embodiment, for example, the voltage line VL may be, but is not limited to, a high-level line, a low-level line, or a sensing line. The voltage line VL may apply a power supply voltage to the transistor TR or the light-emitting element ED.

[0107] The passivation layer PAS may be disposed on the third metal layer MTL3 and the interlayer dielectric layer ILD. The passivation layer PAS may protect the transistor TR. The passivation layer PAS may define a contact hole through which the pixel electrode AE passes.

[0108] The via layer VIA may be disposed on the passivation layer PAS. The via layer VIA may provide a flat surface throughout the transistor layer TRL. The via layer VIA may include an organic insulating material such as PI. The via layer VIA may define a contact hole through which the pixel electrode AE passes.

[0109] The light-emitting element layer EML may be disposed on the transistor layer TRL. The light-emitting element layer EML may include the light-emitting element ED and the pixel defining layer PDL.

[0110] The light-emitting element ED may be disposed in the emission area EA and on the via layer VIA. The light-emitting element ED of each pixel may include a pixel electrode (or anode electrode) AE, an emission layer EL, and a common electrode (or cathode electrode) CE. The pixel electrode AE may be disposed on the via layer VIA. The pixel electrode AE may overlap with one of the plurality of emission areas EA defined by the pixel defining layer PDL. The pixel electrode AE may be inserted into a contact hole penetrating the via layer VIA and the passivation layer PAS and connected to the connection electrode CNE. In one embodiment, for example, the pixel electrode AE may receive a driving current from the pixel circuit through the connection electrode CNE.

[0111] The emission layer EL may be disposed on the pixel electrode AE. In one embodiment, for example, the emission layer EL may be, but is not limited to, an organic emission layer including an organic material. When the emission layer EL is an organic light-emitting layer, when the pixel circuit of the pixel applies a predetermined voltage to the pixel electrode AE and the common electrode CE receives a common voltage or a cathode voltage, holes may move to the emission layer EL through the hole transport layer, electrons may move to the emission layer EL through the hole transport layer, and they combine in the emission layer EL to emit light.

[0112] The common electrode CE may be disposed on the emission layer EL. In one embodiment, for example, the common electrode CE may be implemented as an electrode common to all pixels, rather than being disposed as a separate electrode for each of the pixels. The common electrode CE may be disposed on the emission layer EL in the emission area EA, and may be disposed on the pixel defining layer PDL in other areas different from the emission area EA.

[0113] The pixel definition layer PDL can be disposed in the light blocking region BA and on the via layer VIA. The pixel definition layer PDL can define a plurality of emission regions EA or a plurality of openings. The pixel definition layer PDL can separate and insulate the pixel electrodes AE of the pixels from each other.

[0114] The encapsulation layer TFEL can be disposed on the common electrode CE to cover the light emitting element ED. The encapsulation layer TFEL can include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element ED. The encapsulation layer TFEL can include at least one organic film to protect the light emitting element from particles such as dust.

[0115] The touch sensing unit TSU can be disposed on the encapsulation layer TFEL. The touch sensing unit TSU can include a touch electrode TE, a first insulating layer IL1, a bridge electrode BRG, and a second insulating layer IL2.

[0116] The touch electrode TE can be disposed in the light blocking region BA and on the encapsulation layer TFEL. The touch electrode TE can detect a user touch by capacitance sensing. In one embodiment, for example, the touch sensing unit TSU can sense a user touch by mutual capacitance sensing performed at points between a plurality of touch electrodes TE or by self-capacitance sensing performed on each of the plurality of touch electrodes TE. The touch electrode TE can include a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (“ITO”) or be composed of the single layer, or can include or be composed of the following: a stacked structure of titanium and aluminum (Ti / Al / Ti), a stacked structure of aluminum and ITO (“ITO / Al / ITO”), an aluminum polymer composite (“APC”) alloy, or a stacked structure of an APC alloy and ITO (“ITO / APC / ITO”).

[0117] The first insulating layer IL1 can be disposed on the touch electrode TE and the encapsulation layer TFEL. The first insulating layer IL1 can have insulating and optical functions. In one embodiment, for example, the first insulating layer IL1 can be an inorganic layer including at least one selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. In another embodiment, the first insulating layer IL1 can include an organic film.

[0118] The bridge electrode BRG can be disposed on the first insulating layer IL1. The bridge electrode BRG can be disposed in a layer different from the touch electrode TE to electrically connect between adjacent touch electrodes TE.

[0119] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the first insulating layer IL1. The second insulating layer IL2 may have insulating and optical functions. The second insulating layer IL2 may include one of the above materials as the material of the first insulating layer IL1 or be composed of one of the above materials as the material of the first insulating layer IL1.

[0120] The polarizing film POL may be disposed on the second insulating layer IL2. The polarizing film POL may be attached to the touch sensing unit TSU through an OCA film or an OCR. In one embodiment, for example, the polarizing film POL may include a linear polarizer and a retardation film. The retardation film may be a λ / 4 plate (quarter-wave plate). The retardation film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The polarizing film POL may reduce the reflection of external light to prevent color distortion caused by the reflection of external light.

[0121] The flexible film FPCB may be disposed under the substrate SUB. A part of the flexible film FPCB may be inserted into the opening SOP of the substrate SUB and electrically connected to the pad PAD. Another part of the flexible film FPCB may be attached to the lower surface of the substrate SUB using an adhesive member ADM. The flexible film FPCB may include a lead electrode LDE disposed on one side of the upper surface and inserted into the opening SOP. The lead electrode LDE may protrude from one side of the flexible film FPCB, and a part of the lead electrode LDE may not overlap with the flexible film FPCB. The upper surface of the lead electrode LDE may contact a part of the pad PAD. A part of the lower surface of the lead electrode LDE may be electrically connected to another part of the pad PAD through a contact portion CTP. The flexible film FPCB may support the display driver DIC disposed on the lower surface on the side opposite to the above-mentioned one side. The lead electrode LDE may be electrically connected to the display driver DIC through a lead (not shown) disposed on the lower surface of the flexible film FPCB. The side of the flexible film FPCB opposite to the above-mentioned one side may be connected to a source circuit board (not shown) under the substrate SUB. The flexible film FPCB may transmit signals and voltages from the display driver DIC to the display area DA. The flexible film FPCB may supply a scan control signal to the scan driver SIC.

[0122] The contact portion CTP can cover the lower surface of the lead electrode LDE protruding from the flexible film FPCB and the lower surface of the pad PAD exposed through the opening SOP. The contact portion CTP can supplement the electrical connection between the lead electrode LDE and the pad PAD, and can stably fix the lead electrode LDE to the lower surface of the pad PAD. The contact portion CTP can include metal powder and a polymer. In one embodiment, for example, the metal powder can include metal particles such as silver (Ag) and copper (Cu) or be composed of the metal particles, and the polymer can include an acrylic resin or an epoxy resin. However, it should be understood that the present disclosure is not limited thereto. Since the contact portion CTP can include or be composed of metal powder, it can have conductivity and can include a polymer as a binder for connecting the metal particles.

[0123] The contact portion CTP can be formed by printing a metal paste including metal particles, monomers, and a solvent or composed of metal particles, monomers, and a solvent in the opening SOP of the substrate SUB using a silicon pad, and then sintering it using a laser. During the sintering process, the monomers react to form a polymer by the heat from the laser, so that the metal particles are in close contact with each other and aggregate, reducing the predetermined resistance of the contact portion CTP.

[0124] The display driver DIC can be disposed (e.g., mounted) on the flexible film FPCB. The display driver DIC can be an IC. The display driver DIC can convert digital video data into an analog data voltage based on a data control signal from a timing controller (not shown), and the analog data voltage can be applied to the data lines DL in the display area DA through the flexible film FPCB. The display driver DIC can supply a power voltage received from a power supply unit (not shown) to the power lines VL in the display area DA through the flexible film FPCB. Since the display device 10 includes the fan-out line FOL disposed on the substrate SUB, the flexible film FPCB disposed under the substrate SUB, and the display driver DIC, the non-display area NDA can be reduced.

[0125] Figure 6 A view showing an embodiment of the bottom of the display device according to the present disclosure. Figure 7 An enlarged view showing an embodiment of a part of the bottom of the display device in an embodiment of the present disclosure.

[0126] See Figure 6 and Figure 7 , the flexible film FPCB, the display driver DIC, the pad PAD, and the fan-out line FOL can be disposed in the display area DA.

[0127] The fan-out line FOL can be connected to the pad PAD. The fan-out line FOL can extend from the pad PAD to the edge of the display area DA. For example, in one embodiment, the fan-out line FOL can extend from the pad PAD toward the lower edge of the display area DA. The fan-out line FOL can be electrically connected to the data line DL and the voltage line VL in the display area DA, or the scan driver SIC in the non-display area NDA.

[0128] The flexible film FPCB can be disposed under the substrate SUB. The flexible film FPCB can be disposed at the edge of the lower surface of the display device 10. The flexible film FPCB can supply but is not limited to data voltage, power voltage, and scan control signals. The display driver DIC can be disposed (e.g., mounted) on the flexible film FPCB. The display driver DIC can supply the data voltage and the power voltage to the display panel 100 through the flexible film FPCB.

[0129] A part of the flexible film FPCB can be inserted into the opening SOP of the substrate SUB and electrically connected to the pad PAD. Another part of the flexible film FPCB can be attached to the lower surface of the substrate SUB. The flexible film FPCB can include a lead electrode LDE inserted into the opening SOP. The lead electrode LDE can protrude from one side of the flexible film FPCB. One surface of the lead electrode LDE can contact a part of the pad PAD. A part of the surface of the lead electrode LDE opposite to the above one surface can be electrically connected to another part of the pad PAD through the contact part CTP. A plurality of pads PAD can be respectively associated with a plurality of lead electrodes LDE.

[0130] The contact part CTP can cover the lower surface of the lead electrode LDE and the lower surface of the pad PAD. The contact part CTP can supplement the electrical connection between the lead electrode LDE and the pad PAD and can stably fix the lead electrode LDE to the lower surface of the pad PAD. The contact part CTP can include metal powder and polymer. In one embodiment, for example, the metal powder can include metal particles such as silver (Ag) and copper (Cu) or be composed of the metal particles, and the polymer can include acrylic resin or epoxy resin. However, it should be understood that the present disclosure is not limited thereto. Since the contact part CTP can include or be composed of metal powder, it can have conductivity and can include a polymer as a binder for connecting the metal particles.

[0131] The contact part CTP can be formed by printing a metal paste including metal particles, monomers, and solvents or composed of metal particles, monomers, and solvents in the opening SOP of the substrate SUB using a silicon pad and then sintering it using a laser. During the sintering process, the monomers react to form a polymer by the heat from the laser, so that the metal particles are in close contact with each other and aggregate, reducing the predetermined resistance of the contact part CTP.

[0132] The sintered metal paste can cover a plurality of pads PAD and insert a plurality of lead electrodes LDE into an opening SOP. A plurality of cuts CUT formed during the laser patterning process can separate a plurality of contact portions CTP. The contact portion CTP can be separated from an adjacent contact portion by the cut CUT, and one contact portion CTP can electrically connect one pad PAD to one lead electrode LDE.

[0133] Figure 8 A view showing an embodiment of the bottom of a display device according to the present disclosure.

[0134] See Figure 8 , the fan-out line FOL and the pad PAD can be disposed in the non-display area NDA. The fan-out line FOL can be connected to the pad PAD. The fan-out line FOL can extend from the pad PAD to the edge of the display area DA. For example, in one embodiment, the fan-out line FOL can extend from the pad PAD toward the lower edge of the display area DA. The fan-out line FOL can be electrically connected to the data line DL and the voltage line VL in the display area DA, or the scan driver SIC in the non-display area NDA.

[0135] The flexible film FPCB can be disposed in the display area DA and the non-display area NDA, and the display driver DIC can be disposed in the display area DA. The flexible film FPCB can be disposed under the substrate SUB. The flexible film FPCB can be disposed at the edge of the lower surface of the display device 10. The flexible film FPCB can supply, but is not limited to, data voltage, power voltage, and scan control signals. The display driver DIC can be disposed (e.g., mounted) on the flexible film FPCB. The display driver DIC can supply the data voltage and the power voltage to the display panel 100 through the flexible film FPCB.

[0136] Figure 9 A circuit diagram showing an embodiment of a pixel of a display device according to the present disclosure.

[0137] See Figure 9 , the pixel SP can include a pixel circuit and a light-emitting element ED. The pixel circuit can include a first transistor to a third transistor ST1, ST2, and ST3 and a first capacitor C1.

[0138] The first transistor ST1 can include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 can be connected to the first node N1, its drain electrode can be connected to the high-level line VDL, and its source electrode can be connected to the second node N2. The high-level line VDL can supply a high-level voltage to the first transistor ST1. The first transistor ST1 can control the drain-source current (or drive current) based on the data voltage applied to the gate electrode.

[0139] The pixel SP may include at least one light-emitting element ED. When the pixel SP includes a plurality of light-emitting elements ED, the plurality of light-emitting elements ED may be connected in series or in parallel. The light-emitting element ED may emit light by receiving a driving current from the first transistor ST1. The amount or brightness of the light emitted from the light-emitting element ED may be proportional to the magnitude of the driving current. The light-emitting element ED may include an organic LED including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0140] The first electrode of the light-emitting element ED may be connected to the second node N2, and the second electrode of the light-emitting element ED may be connected to the low-level voltage line VSL. The first electrode of the light-emitting element ED may be connected to the source electrode of the first transistor ST1, the drain electrode of the third transistor ST3, and the second capacitor electrode of the first capacitor C1 through the second node N2. The low-level voltage line VSL may supply a low-level voltage to the second electrode of the light-emitting element ED.

[0141] The second transistor ST2 may be turned on by a first scan signal of the first scan line GL1 to electrically connect the data line DL to the first node N1, which is the gate electrode of the first transistor ST1. The second transistor ST2 may be turned on in response to the first scan signal to apply a data voltage to the first node N1. The gate electrode of the second transistor ST2 may be connected to the first scan line GL1, its drain electrode may be connected to the data line DL, and its source electrode may be connected to the first node N1.

[0142] The third transistor ST3 may be turned on by a second scan signal of the second scan line GL2 to electrically connect the initialization voltage line VIL to the second node N2, which is the source electrode of the first transistor ST1. The third transistor ST3 may be turned on in response to the second scan signal to apply an initialization voltage to the second node N2 and supply a sensing signal to the initialization voltage line VIL. The gate electrode of the third transistor ST3 may be connected to the second scan line GL2, the drain electrode may be connected to the second node N2, and the source electrode may be connected to the initialization voltage line VIL.

[0143] The first capacitor C1 may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the first capacitor C1 may be connected to the first node N1, and the second capacitor electrode of the first capacitor C1 may be connected to the second node N2. Thus, the first capacitor C1 may maintain the potential difference between the gate electrode and the source electrode of the first transistor ST1.

[0144] Figures 10 to 15A cross-sectional view showing an embodiment of a process operation for manufacturing a display device according to the present disclosure. In the following description, elements identical to the above elements will be briefly described or omitted.

[0145] During Figure 10 the process of manufacturing the display device 10, the carrier substrate CG can support the display device 10. In one embodiment, for example, the carrier substrate CG can be, but is not limited to, a glass carrier plate.

[0146] The substrate SUB can be disposed on the carrier substrate CG. The substrate SUB can be a base substrate or a base member. In one embodiment, for example, the substrate SUB can be, but is not limited to, a rigid substrate including a glass material or a metal material. In another embodiment, the substrate SUB can be a flexible substrate including a polymer resin, such as PI.

[0147] A groove can be defined in the substrate SUB via a first etching process. The first side surface SUBa of the substrate SUB can surround the groove of the substrate SUB. The first etching process of the substrate SUB can include at least one of a wet etching process, a dry etching process, a plasma etching process, and a laser etching process. The first side surface SUBa of the substrate SUB can be formed by etching from the upper surface of the substrate SUB and can be adjacent to the upper surface of the substrate SUB. The first side surface SUBa of the substrate SUB can be inclined at a first angle θ1 with respect to a plane identical to the plane of the upper surface of the substrate SUB.

[0148] During Figure 11 the pad cladding PCL is received in the groove of the substrate SUB, so that it can be surrounded by the first side surface SUBa of the substrate SUB. The upper surface of the pad cladding PCL can be flush with the upper surface of the substrate SUB, but the present disclosure is not limited thereto. The pad cladding PCL can include a pad contact hole PCT into which the pad PAD is inserted. In one embodiment, the pad cladding PCL can include, but is not limited to, a polymer resin such as PI or an insulating material such as silicon nitride (SiN x ) and silicon (Si).

[0149] The first metal layer MTL1 can be disposed on the substrate SUB and the pad cladding PCL. The first metal layer MTL1 can include the pad PAD and the light blocking layer BML.

[0150] The pad PAD can be disposed on the pad cladding PCL and inserted into the pad contact hole PCT formed in the pad cladding PCL. The pad PAD can be inserted into the pad contact hole PCT and temporarily contact one surface of the substrate SUB.

[0151] During Figure 12Among them, a buffer layer BF, an active layer ACTL, a gate insulator GI, a second metal layer MTL2, an interlayer dielectric layer ILD, a third metal layer MTL3, a passivation layer PAS, and a via layer VIA may be sequentially stacked on a first metal layer MTL1.

[0152] A light-emitting element layer EML may be disposed on a transistor layer TRL. The light-emitting element layer EML may include a light-emitting element ED and a pixel defining layer PDL.

[0153] A packaging layer TFEL may be disposed on a common electrode CE to cover the light-emitting element ED.

[0154] A touch sensing unit TSU may be disposed on the packaging layer TFEL and include a plurality of touch electrodes and a plurality of touch lines.

[0155] A polarizing film POL may be disposed on the touch sensing unit TSU. The polarizing film POL may be attached to the touch sensing unit TSU through an OCA film or an OCR.

[0156] In Figure 13 Among them, the display device 10 under manufacturing may be vertically inverted to attach a flexible film FPCB. A carrier substrate CG may be removed from a substrate SUB. In one embodiment, for example, the carrier substrate CG may be removed from the lower surface of the substrate SUB using a sacrificial layer (not shown) disposed between the carrier substrate CG and the substrate SUB, but the present disclosure is not limited thereto.

[0157] An opening SOP of the substrate SUB may be defined via a second etching process of the substrate SUB, and a second side surface SUBb of the substrate SUB may surround the opening SOP. The second etching process of the substrate SUB may include at least one of a wet etching process, a dry etching process, a plasma etching process, and a laser etching process. The opening SOP may be defined in the substrate SUB to expose a pad cladding PCL and a pad PAD. During the second etching process of the substrate SUB, the pad cladding PCL may protect the transistor layer TRL except for the pad PAD.

[0158] In Figure 14 Among them, a flexible film FPCB may be disposed on one surface of the substrate SUB. The flexible film FPCB and a lead electrode LDE may be aligned on the pad PAD through an alignment process. A part of the flexible film FPCB may be inserted into the opening SOP of the substrate SUB and electrically connected to the pad PAD. Another part of the flexible film FPCB may be attached to the lower surface of the substrate SUB using an adhesive member ADM. The lead electrode LDE may protrude from one side of the flexible film FPCB. One surface of the lead electrode LDE may contact a part of the pad PAD.

[0159] In Figure 15In this case, the contact portion CTP may cover a part of the lead electrode LDE and a part of the pad PAD. A part of the surface of the lead electrode LDE opposite to the above-mentioned one surface may be electrically connected to another part of the pad PAD through the contact portion CTP. The contact portion CTP may supplement the electrical connection between the lead electrode LDE and the pad PAD, and may stably fix the lead electrode LDE to one surface of the pad PAD. The contact portion CTP may include metal powder and polymer. In one embodiment, for example, the metal powder may include metal particles such as silver (Ag) and copper (Cu) or be composed of the metal particles, and the polymer may include an acrylic resin or an epoxy resin. However, it should be understood that the present disclosure is not limited thereto. Since the contact portion CTP may include or be composed of metal powder, it may have conductivity and may include a polymer as a binder for connecting metal particles.

[0160] The contact portion CTP may be formed by printing a metal paste including metal particles, monomers, and solvents or composed of metal particles, monomers, and solvents in the opening SOP of the substrate SUB using a silicon pad, and then sintering it using a laser. During the sintering process, the monomers react to form a polymer by the heat from the laser, so that the metal particles are in close contact with each other and aggregated, and the predetermined resistance of the contact portion CTP can be reduced.

[0161] The sintered metal paste may cover a plurality of pads PAD and a plurality of lead electrodes LDE inserted into one opening SOP. A plurality of cuts CUT formed during the laser patterning process may separate the plurality of contact portions CTP. The contact portion CTP may be separated from an adjacent contact portion by the cut CUT, and one contact portion CTP may electrically connect one pad PAD to one lead electrode LDE.

[0162] Therefore, in the display device 10, the lead electrode LDE and the pad PAD are fixed by the contact portion CTP, so that the lead electrode LDE of the flexible film FPCB can be electrically connected to the pad PAD without using ultrasonic bonding or thermocompression bonding. The contact portion CTP may supplement the electrical connection between the lead electrode LDE and the pad PAD, and may easily connect the lead electrode LDE to the pad PAD. In addition, by simplifying the manufacturing process of the display device 10, manufacturing time and cost can be saved.

[0163] In summarizing the detailed description, those skilled in the art will realize that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present utility model. Therefore, the disclosed preferred embodiments of the present utility model are for general and descriptive purposes only and are not for the purpose of limitation.

Claims

1. A display device, characterized in that, Comprising: A substrate, the substrate including a first side surface adjacent to an upper surface and a second side surface adjacent to a lower surface, and an opening surrounded by the second side surface being defined in the substrate; A pad cladding, surrounded by the first side surface of the substrate and including a pad contact hole; A pad, disposed on the pad cladding and inserted into the pad contact hole; Fan-out lines, disposed on the pad and electrically connected to the pad; A transistor, electrically connected to the fan-out lines; And A flexible film, disposed below the substrate and including a lead electrode inserted into the opening of the substrate and contacting the pad.

2. The display device according to claim 1, wherein, The display device further includes: A contact portion, covering a lower surface of the lead electrode and a lower surface of the pad to electrically connect the lead electrode to the pad.

3. The display device according to claim 2, characterized in that, The lead electrode protrudes from one side of the flexible film, and the contact portion covers the lower surface of the lead electrode protruding from the flexible film.

4. The display device according to claim 1, characterized in that, An upper surface of the pad cladding is flush with the upper surface of the substrate.

5. The display device according to claim 1, wherein The material of the pad cladding is one of polyimide, silicon nitride, and silicon.

6. The display device according to claim 1, wherein The pad is exposed through the opening of the substrate.

7. The display device according to claim 1, wherein The first side surface of the substrate is inclined at a first angle with respect to a plane the same as the plane of the upper surface of the substrate, the second side surface of the substrate is inclined at a second angle with respect to a plane the same as the plane of the lower surface of the substrate, and the first angle is less than the second angle.

8. The display device according to claim 7, characterized in that, A vertical height of the first side surface is less than a vertical height of the second side surface.

9. The display device according to claim 2, wherein The contact portion is formed using a metal paste including silver or copper.

10. The display device according to claim 1, characterized in that, The display device includes: a display area for displaying an image; and A non-display area surrounding the display area, wherein the pad and the flexible film are disposed in the display area.

Images