Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer which are arranged on a substrate, the driving structure layer comprises a plurality of circuit units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; the circuit unit at least comprises a first circuit unit and a second circuit unit, the first circuit unit and the second circuit unit respectively comprise a pixel driving circuit, and the pixel driving circuit of the first circuit unit is connected with the first light-emitting device. The pixel driving circuit of the second circuit unit is not connected with the first light-emitting device; the at least one second circuit unit further comprises at least one transverse connecting line extending in the first direction and at least one vertical connecting line extending in the second direction, the transverse connecting lines and the vertical connecting lines are connected to form a net-shaped communication structure, and the first direction intersects with the second direction.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Currently, the preparation of existing OLED display devices has problems such as static electricity accumulation. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device to solve the problems such as static electricity accumulation in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a first display area and a second display area, the first display area at least partially surrounding the second display area, the first display area being configured to display images, and the second display area being configured to display images and transmit light; the first display area including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, the driving structure layer including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the light-emitting structure layer including a plurality of first light-emitting devices; the circuit unit including at least a first circuit unit and a second circuit unit, the first circuit unit and the second circuit unit both including a pixel driving circuit, the pixel driving circuit of the first circuit unit being connected to the first light-emitting device, and the pixel driving circuit of the second circuit unit being not connected to the first light-emitting device; at least one second circuit unit also including at least one horizontal connecting line extending along a first direction and at least one vertical connecting line extending along a second direction, the horizontal connecting line being connected to the vertical connecting line to form a mesh connection structure, and the first direction and the second direction intersecting.

[0007] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit at least includes a storage capacitor, a first reset transistor, a second reset transistor, and a first light-emitting control transistor. A first pole of the first reset transistor is connected to a first initial signal line through a fifth connection electrode. A second pole of the first reset transistor is connected to a first plate of the storage capacitor through a first connection electrode. A first pole of the first light-emitting control transistor is connected to a second plate of the storage capacitor through a third connection electrode. A first pole of the second reset transistor is connected to a second initial signal line through a sixth connection electrode. The third connection electrode is connected to a first power supply line. The second plates in a plurality of unit rows in at least one unit row form a horizontal power supply signal line. In at least one second circuit unit, the vertical connection line includes the first connection electrode, the third connection electrode, and the fifth connection electrode. The first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode. The third connection electrode is connected to the horizontal connection line of the current unit row. The fifth connection electrode is connected to the horizontal connection line of the previous unit row.

[0008] In an exemplary embodiment, at least one second circuit unit further includes an eleventh connection electrode, a twelfth connection electrode, a thirteenth connection electrode, and a fourteenth connection electrode. The eleventh connection electrode is disposed between the first connection electrode and the third connection electrode and is respectively connected to the first connection electrode and the third connection electrode. The twelfth connection electrode is disposed between the first connection electrode and the fifth connection electrode and is respectively connected to the first connection electrode and the fifth connection electrode. The thirteenth connection electrode is disposed between the third connection electrode and the horizontal connection line of the current unit row and is respectively connected to the third connection electrode and the horizontal connection line of the current unit row. The fourteenth connection electrode is disposed between the fifth connection electrode and the horizontal connection line of the previous unit row and is respectively connected to the fifth connection electrode and the horizontal connection line of the previous unit row.

[0009] In an exemplary embodiment, the horizontal connection line includes a first horizontal connection line, and the vertical connection line includes a first vertical connection line. The fifth connection electrode in the first vertical connection line is connected to the first initial signal line. The first initial signal line and the first horizontal connection line form a horizontal double-line structure for transmitting a first initial signal.

[0010] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line. The second connection electrode is connected to a first pole of the data writing transistor. The data connection electrode is connected to the second connection electrode. The data signal line is connected to the data connection electrode. In at least one second circuit unit, it further includes a first data connection block, and the first data connection block is respectively connected to the second connection electrode and the first initial signal line.

[0011] In an exemplary embodiment, in at least one second circuit unit, it further includes a first vertical trace and a second vertical trace. The first vertical trace is connected to the data connection electrode. The second vertical trace is connected to the first vertical trace. The first vertical connection line, the first vertical trace, and the second vertical trace form a vertical three-line structure for transmitting a first initial signal. The horizontal two-line structure and the vertical three-line structure form a plurality of first mesh connection structures.

[0012] In an exemplary embodiment, in at least one second circuit unit, the third connection electrode is not connected to the first power supply line.

[0013] In an exemplary embodiment, the horizontal connection line includes a second horizontal connection line, and the vertical connection line includes a second vertical connection line. In at least one second circuit unit, it further includes a fifteenth connection electrode. The fifteenth connection electrode is disposed between the fifth connection electrode and the sixth connection electrode and is respectively connected to the fifth connection electrode and the sixth connection electrode. The second initial signal line and the second horizontal connection line form a horizontal two-line structure for transmitting a second initial signal.

[0014] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, a second data connection block, and a data signal line. The second connection electrode is connected to a first pole of the data writing transistor. The data connection electrode is connected to the second connection electrode. The data signal line is connected to the data connection electrode. The second data connection block is connected to the sixth connection electrode. In at least one second circuit unit, it further includes a third data connection block, and the third data connection block is respectively connected to the second data connection block and the data connection electrode.

[0015] In an exemplary embodiment, at least one second circuit unit further includes a first vertical trace and a second vertical trace. The first vertical trace is connected to the data connection electrode, the second vertical trace is connected to the first vertical trace, and the second vertical connection line, the first vertical trace, and the second vertical trace form a vertical three-line structure for transmitting a second initial signal. The horizontal two-line structure and the vertical three-line structure form a plurality of second mesh connection structures.

[0016] In an exemplary embodiment, in at least one second circuit unit, the third connection electrode is not connected to the first power supply line, and the fifth connection electrode is not connected to the first initial signal line.

[0017] In an exemplary embodiment, the horizontal connection line includes a third horizontal connection line, and the vertical connection line includes a third vertical connection line. The third connection electrode in the third vertical connection line is connected to the first power supply line, and the horizontal power supply signal line and the third horizontal connection line form a horizontal two-line structure for transmitting a first power supply signal.

[0018] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line. The second connection electrode is connected to the first pole of the data writing transistor, the data connection electrode is connected to the second connection electrode, and the data signal line is connected to the data connection electrode; at least one second circuit unit further includes a power supply connection block, and the power supply connection block is respectively connected to the data connection electrode and the first power supply line.

[0019] In an exemplary embodiment, at least one second circuit unit further includes a first vertical trace and a second vertical trace. The first vertical trace is connected to the data connection electrode, the second vertical trace is connected to the first vertical trace, and the first power supply line, the third vertical connection line, the first vertical trace, and the second vertical trace form a vertical four-line structure for transmitting a first power supply signal. The horizontal two-line structure and the vertical four-line structure form a plurality of third mesh connection structures.

[0020] In an exemplary embodiment, in at least one second circuit unit, the fifth connection electrode is not connected to the first initial signal line.

[0021] In an exemplary embodiment, the horizontal connection line includes a first horizontal connection line, a second horizontal connection line, and / or a third horizontal connection line, the vertical connection line includes a first vertical connection line, a second vertical connection line, and / or a third vertical connection line, and the mesh connection structure includes a first mesh connection structure, a second mesh connection structure, and / or a third mesh connection structure.

[0022] On the other hand, the present disclosure also provides a display device, including the aforementioned display substrate.

[0023] The present disclosure provides a display substrate and a display device. By forming a mesh communication structure, the electrostatic accumulation generated in the process can be effectively eliminated, the damage and short circuit of transistors in the pixel driving circuit can be effectively avoided, and the product quality is improved.

[0024] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0025] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0026] Figure 1 It is a schematic structural diagram of a display device;

[0027] Figure 2 It is a schematic structural diagram of a display substrate;

[0028] Figure 3 It is a schematic plan view of a display area in a display substrate;

[0029] Figure 4 It is a schematic cross-sectional view of a display area in a display substrate;

[0030] Figure 5 It is an equivalent circuit diagram of a pixel driving circuit;

[0031] Figure 6 It is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 It is a schematic diagram showing the connection between a pixel driving circuit and a light-emitting device according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 It is a schematic structural diagram of a first display area according to an exemplary embodiment of the present disclosure;

[0034] Figure 9A and Figure 9B It is a schematic structural diagram of a first mesh communication structure according to an exemplary embodiment of the present disclosure;

[0035] Figure 10 It is a schematic diagram of a display substrate of the present disclosure after forming a semiconductor layer pattern;

[0036] Figure 11A and Figure 11BSchematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0037] Figure 12A and Figure 12B Schematic diagram of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0038] Figure 13 Schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0039] Figure 14A and Figure 14B Schematic diagram of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0040] Figure 15 Schematic diagram of a display substrate after forming a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0041] Figure 16A and Figure 16B Schematic diagram of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0042] Figure 17 Schematic diagram of a display substrate after forming a second planarization layer pattern according to the present disclosure;

[0043] Figure 18A and Figure 18B Schematic diagram of a display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0044] Figure 19 Schematic diagram of another structure of a first display area according to an exemplary embodiment of the present disclosure;

[0045] Figure 20A and Figure 20B Schematic diagram of a structure of a second mesh connection structure according to an exemplary embodiment of the present disclosure;

[0046] Figure 21 Schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0047] Figure 22A and Figure 22B Schematic diagram of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0048] Figure 23 Schematic diagram of another display substrate after forming a fifth insulating layer and a first planarization layer pattern according to the present disclosure;

[0049] Figure 24A and Figure 24B Schematic diagram of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0050] Figure 25 Schematic diagram of another structure of the first display area according to an exemplary embodiment of the present disclosure;

[0051] Figure 26A and Figure 26B Schematic diagram of the structure of a third mesh connection structure according to an exemplary embodiment of the present disclosure;

[0052] Figure 27A and Figure 27B Schematic diagram of another display substrate after forming a third conductive layer pattern;

[0053] Figure 28 Schematic diagram of another display substrate after forming a fifth insulating layer and a first planarization layer pattern;

[0054] Figure 29A and Figure 29B Schematic diagram of another display substrate after forming a fourth conductive layer pattern;

[0055] Figure 30 Schematic diagram of another structure of the first display area according to an exemplary embodiment of the present disclosure;

[0056] Figure 31 Schematic diagram of another structure of the first display area according to an exemplary embodiment of the present disclosure;

[0057] Figure 32 Schematic diagram of another structure of the first display area according to an exemplary embodiment of the present disclosure;

[0058] Figure 33 Schematic diagram of another structure of the first display area according to an exemplary embodiment of the present disclosure.

[0059] Description of reference numerals:

[0060] 11 - First active layer; 12 - Second active layer; 13 - Third active layer;

[0061] 14 - Fourth active layer; 15 - Fifth active layer; 16 - Sixth active layer;

[0062] 17 - Seventh active layer; 21 - First scan signal line; 22 - Second scan signal line;

[0063] 23 - Light-emitting signal line; 31 - First electrode plate; 32 - Second electrode plate;

[0064] 33 - Opening; 34 - Electrode plate connection bar; 41 - First initial signal line;

[0065] 42 - Second initial signal line; 43 - First shielding electrode; 44 - Second shielding electrode;

[0066] 51 - The first connection electrode; 52 - The second connection electrode; 53 - The third connection electrode;

[0067] 54 - The fourth connection electrode; 55 - The fifth connection electrode; 56 - The sixth connection electrode;

[0068] 61 - The eleventh connection electrode; 62 - The twelfth connection electrode; 63 - The thirteenth connection electrode;

[0069] 64 - The fourteenth connection electrode; 65 - The fifteenth connection electrode; 66 - The first data connection block;

[0070] 67 - The second data connection block; 68 - The third data connection block; 71 - The first power line;

[0071] 72 - The second power line; 73 - The data signal line; 74 - The data connection electrode;

[0072] 75 - The first anode connection electrode; 76 - The second anode connection electrode; 81 - The first horizontal connection line;

[0073] 82 - The second horizontal connection line; 83 - The third horizontal connection line; 91 - The first vertical connection line;

[0074] 92 - The second vertical connection line; 93 - The third vertical connection line; 100 - The display area;

[0075] 101 - The substrate; 102 - The driving structure layer; 103 - The light-emitting structure layer;

[0076] 104 - The encapsulation structure layer; 110 - The first vertical trace; 120 - The second vertical trace;

[0077] 200 - The bonding area; 300 - The border area. Detailed implementation manners

[0078] To make the objectives, technical solutions, and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and the features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0079] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in this disclosure are only schematic diagrams of the structure, and one embodiment of this disclosure is not limited to the shapes or values shown in the drawings.

[0080] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit the quantity.

[0081] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of components with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the situation.

[0082] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0083] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0084] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other, and the "source terminal" and "drain terminal" can be interchanged with each other.

[0085] In this specification, "electrically connected" includes cases where constituent elements are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0086] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0087] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0088] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations due to tolerances, chamfers, rounded edges, and deformations. "About" in this disclosure means not strictly limiting the boundary and allowing values within the process and measurement errors.

[0089] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the light-emitting signal line, and the data signal line. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having a conductive level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having a cut-off level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0090] Figure 2 is a schematic structural diagram of a display substrate. As Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic pictures or still images. The display area 100 may be referred to as an active area (AA for short). In an exemplary embodiment, the display substrate may adopt a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0091] In an exemplary embodiment, the bonding area 200 may include a lead-out wire area, a bending area, a driving chip area, and a bonding pin area that are sequentially arranged along the direction away from the display area. The lead-out wire area is connected to the display area 100 and includes at least data lead-out wires. The bending area is connected to the lead-out wire area and may at least include a composite insulating layer provided with grooves. The grooves are configured to bend the bonding area to the back of the display area. The driving chip area may include an integrated circuit (IC for short), and the integrated circuit is configured to be connected to a plurality of data lead-out wires. The bonding pin area may include bonding pads, and the bonding pads are configured to be bonded and connected to an external flexible printed circuit (FPC for short).

[0092] In an exemplary embodiment, the border area 300 may include a circuit area, a power supply line area, a crack dam area, and a cutting area that are sequentially arranged along the direction away from the display area 100. The circuit area is connected to the display area 100 and may at least include a gate driving circuit. The gate driving circuit is connected to scan signal lines and light-emitting signal lines in the display area 100. The power supply line area is connected to the circuit area and may at least include border power supply leads. The border power supply leads extend along a direction parallel to the edge of the display area and are connected to cathodes in the display area 100. The crack dam area is connected to the power supply line area and may at least include a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured to be cut by a cutting device along the cutting grooves respectively after all the film layers of the display substrate are prepared.

[0093] In an exemplary embodiment, isolation dams may be provided in the lead-out wire area in the bonding area 200 and the power supply line area in the border area 300. The isolation dams may extend along a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of the display area on the side of the bonding area or the border area.

[0094] Figure 3It is a schematic plan view of a display area in a display substrate. As Figure 3 shown, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.

[0095] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, the third sub-pixel P3 may be a first green sub-pixel (G1) that emits green light, and the fourth sub-pixel P4 may be a second green sub-pixel (G2) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

[0096] In other exemplary embodiments, the pixel unit P may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal side-by-side or vertical side-by-side manner, etc. The present disclosure does not limit this here.

[0097] Figure 4 It is a schematic cross-sectional view of a display area in a display substrate. As Figure 4 shown, in a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 provided on a substrate 101, a light-emitting structure layer 103 provided on a side of the driving structure layer 102 away from the substrate 101, and a packaging structure layer 104 provided on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the first display area may include other film layers, such as a touch control structure layer, etc. The present disclosure does not limit this here.

[0098] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, and each circuit unit may at least include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, and each light-emitting unit may include a light-emitting device. The light-emitting device may at least include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits corresponding color light under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a stacked first encapsulation layer, second encapsulation layer, and third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0099] Figure 5 It is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As Figure 5 shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C. The pixel driving circuit is respectively connected to seven signal lines (a first scan signal line S1, a second scan signal line S2, a light-emitting signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line DATA, and a first power supply line VDD).

[0100] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. Among them, the first node N1 is respectively connected to the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C. The second node N2 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5. The third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6. The fourth node N4 is respectively connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7.

[0101] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power supply line VDD.

[0102] In an exemplary embodiment, a gate electrode of a first transistor T1 is connected to a second scan signal line S2, a first pole of the first transistor T1 is connected to a first initial signal line INIT1, and a second pole of the first transistor T1 is connected to a first node N1.

[0103] In an exemplary embodiment, a gate electrode of a second transistor T2 is connected to a first scan signal line S1, a first pole of the second transistor T2 is connected to the first node N1, and a second pole of the second transistor T2 is connected to a third node N3.

[0104] In an exemplary embodiment, a gate electrode of a third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to a second node N2, and a second pole of the third transistor T3 is connected to the third node N3.

[0105] In an exemplary embodiment, a gate electrode of a fourth transistor T4 is connected to the first scan signal line S1, a first pole of the fourth transistor T4 is connected to a data signal line DATA, and a second pole of the fourth transistor T4 is connected to the second node N2.

[0106] In an exemplary embodiment, a gate electrode of a fifth transistor T5 is connected to a light emission signal line EM, a first pole of the fifth transistor T5 is connected to a first power supply line VDD, and a second pole of the fifth transistor T5 is connected to the second node N2.

[0107] In an exemplary embodiment, a gate electrode of a sixth transistor T6 is connected to the light emission signal line EM, a first pole of the sixth transistor T6 is connected to the third node N3, and a second pole of the sixth transistor T6 is connected to a fourth node N4.

[0108] In an exemplary embodiment, a gate electrode of a seventh transistor T7 is connected to the first scan signal line S1, a first pole of the seventh transistor T7 is connected to a second initial signal line INIT2, and a second pole of the seventh transistor T7 is connected to the fourth node N4.

[0109] In an exemplary embodiment, a first pole of a light emitting device EL is connected to the fourth node N4, and a second pole of the light emitting device EL is connected to a second power supply line VSS. The light emitting device EL may be an OLED, including a stacked first pole (anode), an organic light emitting layer, and a second pole (cathode), or may be a QLED, including a stacked first pole (anode), a quantum dot light emitting layer, and a second pole (cathode).

[0110] In an exemplary embodiment, the first power supply line VDD is configured to provide a constant first power signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second power signal to the light-emitting device, the first power signal is a high-level signal, and the second power signal is a low-level signal. The first initial voltage signal and the second initial voltage signal may be constant voltage signals, which are not limited in the present disclosure.

[0111] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit may be P-type transistors or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0112] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may adopt low-temperature polysilicon thin-film transistors, or may adopt oxide thin-film transistors, or may adopt low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0113] For products such as smart terminals, it is usually necessary to set up hardware such as a front camera, a fingerprint sensor, or a light sensor. To increase the screen-to-body ratio, the display device usually adopts the method of opening holes in the display substrate, using the holes to form an under-display camera area (abbreviated as UDC), and placing sensors such as cameras in the under-display camera area of the display substrate to implement the full display with camera (abbreviated as FDC) technology. The under-display camera area not only has a certain transmittance but also has a display function.

[0114] The exemplary embodiments of the present disclosure provide a display substrate, including a first display area and a second display area, wherein at least part of the first display area surrounds the second display area. The first display area is configured to perform image display, and the second display area is configured to perform image display and transmit light. The first display area includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. The driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and the light-emitting structure layer includes a plurality of first light-emitting devices. The circuit units at least include a first circuit unit and a second circuit unit. The pixel driving circuits of both the first circuit unit and the second circuit unit include pixel driving circuits. The pixel driving circuit of the first circuit unit is connected to the first light-emitting device, and the pixel driving circuit of the second circuit unit is not connected to the first light-emitting device. At least one second circuit unit further includes at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction. The horizontal connection line is connected to the vertical connection line to form a mesh communication structure, and the first direction and the second direction intersect.

[0115] In an exemplary embodiment, in at least one first circuit unit, the pixel driving circuit at least includes a storage capacitor, a first reset transistor, a second reset transistor, and a first light-emitting control transistor. A first pole of the first reset transistor is connected to a first initial signal line through a fifth connection electrode. A second pole of the first reset transistor is connected to a first plate of the storage capacitor through a first connection electrode. A first pole of the first light-emitting control transistor is connected to a second plate of the storage capacitor through a third connection electrode. A first pole of the second reset transistor is connected to a second initial signal line through a sixth connection electrode. The third connection electrode is connected to a first power supply line. The second plates of a plurality of the unit rows in at least one unit row form a horizontal power supply signal line. In at least one second circuit unit, the vertical connection line includes the first connection electrode, the third connection electrode, and the fifth connection electrode. The first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode. The third connection electrode is connected to the horizontal connection line of the present unit row, and the fifth connection electrode is connected to the horizontal connection line of the previous unit row.

[0116] In an exemplary embodiment, the horizontal connection line includes a first horizontal connection line, and the vertical connection line includes a first vertical connection line. The fifth connection electrode in the first vertical connection line is connected to the first initial signal line. The first initial signal line and the first horizontal connection line form a horizontal double-line structure for transmitting a first initial signal.

[0117] In an exemplary embodiment, the horizontal connection line includes a second horizontal connection line, and the vertical connection line includes a second vertical connection line; at least one second circuit unit further includes a fifteenth connection electrode, which is disposed between the fifth connection electrode and the sixth connection electrode and is respectively connected to the fifth connection electrode and the sixth connection electrode; the second initial signal line and the second horizontal connection line form a horizontal double-line structure for transmitting a second initial signal.

[0118] In an exemplary embodiment, the horizontal connection line includes a third horizontal connection line, and the vertical connection line includes a third vertical connection line. The third connection electrode in the third vertical connection line is connected to the first power supply line. The horizontal power supply signal line and the third horizontal connection line form a horizontal double-line structure for transmitting a first power supply signal.

[0119] In an exemplary embodiment, the horizontal connection line includes a first horizontal connection line, a second horizontal connection line, and / or a third horizontal connection line, the vertical connection line includes a first vertical connection line, a second vertical connection line, and / or a third vertical connection line, and the mesh connection structure includes a first mesh connection structure, a second mesh connection structure, and / or a third mesh connection structure.

[0120] Figure 6 This is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. As Figure 6 shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. The display area 100 may at least include a first display area 100A and a second display area 100B. The first display area 100A may at least partially surround the second display area 100B. The first display area 100A is configured to perform image display and may be referred to as a normal display area. The second display area 100B is configured to perform image display and transmit light, and the transmitted light is received by an optical device. It may be referred to as an under-screen camera display area or a light-transmitting display area. The position of the second display area 100B may correspond to the position of the optical device. In a direction perpendicular to the display substrate, the display area may at least include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate.

[0121] In an exemplary embodiment, the driving structure layer of the first display area 100A may include a plurality of circuit repeating units. The circuit repeating unit is the basic unit that constitutes the driving structure layer of the first display area 100A. By repeatedly and continuously arranging the circuit repeating units along the first direction X and the second direction Y, the driving structure layer of the first display area 100A can be formed. A plurality of circuit repeating units arranged in sequence along the first direction X may be referred to as a repeating row, and a plurality of circuit repeating units arranged in sequence along the second direction Y may be referred to as a repeating column. The first direction X and the second direction Y intersect. The light-emitting structure layer of the first display area 100A may include a plurality of light-emitting repeating units. The light-emitting repeating unit is the basic unit that constitutes the light-emitting structure layer of the first display area 100A. By repeatedly and continuously arranging the light-emitting repeating units along the first direction X and the second direction Y, the light-emitting structure layer of the first display area 100A can be formed.

[0122] In an exemplary embodiment, in the first display area 100A, the positions of the plurality of circuit repeating units and the plurality of light-emitting repeating units may be substantially corresponding. The positive projection of at least one circuit repeating unit on the substrate has a first area, and the positive projection of at least one light-emitting repeating unit on the substrate has a second area. The ratio of the first area to the second area may be about 0.95 to 1.05, that is, the area of the positive projection of the circuit repeating unit on the substrate and the area of the positive projection of the light-emitting repeating unit on the substrate may be substantially the same.

[0123] In an exemplary embodiment, the driving structure layer of the first display area 100A may arrange circuit units in a compressed manner, while the light-emitting structure layer of the first display area 100A may arrange first light-emitting units in a normal (non-compressed) manner. For example, in the normal manner, M circuit units may be arranged in one circuit repeating unit, and M first light-emitting units may be arranged in one light-emitting repeating unit. In the compressed manner, by adopting lateral compression, the number of circuit units arranged in the circuit repeating unit can be increased. One circuit unit is inserted into the area where M circuit units were previously arranged, so that one circuit repeating unit may include M + 1 circuit units arranged in sequence along the first direction X. Since the light-emitting structure layer adopts the normal manner, the light-emitting repeating unit still includes M first light-emitting devices arranged in sequence along the first direction X. The area occupied by M + 1 circuit units is substantially the same as the area occupied by M first light-emitting units. In an exemplary embodiment, M may be a positive integer greater than or equal to 2. For example, M may be 2, 4, or 7.

[0124] In an exemplary embodiment, for the pixel arrangement of RGBG in the embodiments of the present disclosure, M is equal to 4, that is, the display substrate in the embodiments of the present disclosure adopts a 4-in-1 structure.

[0125] In an exemplary embodiment, at least one circuit unit may at least include a pixel driving circuit, at least one first light-emitting unit may at least include a first light-emitting device, and the area of the orthographic projection of M+1 pixel driving circuits in a circuit repeating unit on the substrate may be substantially the same as the area of the orthographic projection of M first light-emitting devices in a light-emitting repeating unit on the substrate.

[0126] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to the area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to the area divided according to the light-emitting device. In an exemplary embodiment, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0127] In an exemplary embodiment, a plurality of circuit units arranged in sequence along the first direction X may be referred to as a unit row, and a plurality of circuit units arranged in sequence along the second direction Y may be referred to as a unit column, and a plurality of unit rows and a plurality of unit columns form an array-arranged circuit unit array.

[0128] In an exemplary embodiment, in at least one circuit repeating unit, the sizes of a plurality of pixel driving circuits may be substantially the same. In at least one light-emitting repeating unit, the sizes of a plurality of first light-emitting devices may be substantially the same. In the present disclosure, the size of the pixel driving circuit refers to the size of the orthographic projection of the pixel driving circuit on the substrate, and the size of the light-emitting device refers to the size of the orthographic projection of the light-emitting device on the substrate. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are rectangles, the size may include any one or more of the following: the length in the first direction X of the orthographic projection, the length in the second direction Y of the orthographic projection, and the area of the orthographic projection. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are circles or ellipses, the size may include any one or more of the following: the radius of the orthographic projection, the major axis and minor axis of the orthographic projection, and the area of the orthographic projection.

[0129] In an exemplary embodiment, the driving structure layer of the second display area 100B may include a plurality of insulating layers, the light-emitting structure layer of the second display area 100B may include a plurality of second light-emitting units, and the second light-emitting units may at least include second light-emitting devices, that is, the pixel driving circuit is not provided in the second display area 100B, and only the light-emitting devices are provided. Since the pixel driving circuit is not provided in the second display area 100B, the second light-emitting devices in the second display area 100B need to be connected to the pixel driving circuit in the first display area 100A through an anode connection line.

[0130] In an exemplary embodiment, the size of the second light-emitting devices in the second display area 100B may be substantially the same as the size of the first light-emitting devices in the first display area 100A, and the arrangement of the plurality of second light-emitting devices in the second display area 100B may be substantially the same as the arrangement of the plurality of first light-emitting devices in the first display area 100A.

[0131] In an exemplary embodiment, in at least one circuit repeating unit, M + 1 circuit units may include M first circuit units and 1 second circuit unit, or may include M first circuit units and 1 third circuit unit. Among them, the pixel driving circuit in the first circuit unit is configured to provide a driving signal to the first light-emitting devices in the first display area 100A, the pixel driving circuit in the second circuit unit serves as a dummy pixel circuit, and the pixel driving circuit in the third circuit unit is configured to provide a driving signal to the second light-emitting devices in the second display area 100B.

[0132] Figure 7 It is a schematic diagram of the connection between a pixel driving circuit and a light-emitting device according to an exemplary embodiment of the present disclosure. As Figure 7 shown, the driving structure layer of the first display area 100A may include a plurality of pixel driving circuits, and the driving structure layer of the second display area 100B is not provided with pixel driving circuits. The light-emitting structure layer of the first display area 100A may include a plurality of first light-emitting devices F1, and the light-emitting structure layer of the second display area 100B may include a plurality of second light-emitting devices F2.

[0133] In an exemplary embodiment, the circuit repeating unit in the area of the first display area 100A far from the second display area 100B may include 4 first circuit units Q1 and 1 second circuit unit Q2 arranged in sequence along the first direction X, and the circuit repeating unit in the area of the first display area 100A close to the second display area 100B may include 4 first circuit units Q1 and 1 third circuit unit Q3 arranged in sequence along the first direction X. The first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 all include pixel driving circuits, and the sizes of the pixel driving circuits in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same.

[0134] In an exemplary embodiment, a pixel driving circuit in at least one first circuit unit Q1 is directly connected to at least one first light-emitting unit F1 in the first display area 100A. A positive projection of the pixel driving circuit in at least one first circuit unit Q1 on the substrate at least partially overlaps with a positive projection of at least one first light-emitting device F1 on the substrate. The pixel driving circuit in the first circuit unit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light. In some examples, the pixel driving circuits in multiple first circuit units Q1 and the multiple first light-emitting devices F1 may have a one-to-one relationship, or a one-to-many relationship, or a many-to-one relationship, which is not limited in this disclosure.

[0135] In an exemplary embodiment, a pixel driving circuit in at least one third circuit unit Q3 is connected to at least one second light-emitting device F2 in the second display area 100B through an anode connection line AL. A positive projection of the pixel driving circuit in at least one third circuit unit Q3 on the substrate does not overlap with a positive projection of at least one second light-emitting device F2 on the substrate. The pixel driving circuit in the third circuit unit Q3 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light. In some examples, the pixel driving circuits in multiple third circuit units Q3 and the multiple second light-emitting devices F2 may have a one-to-one relationship, or a one-to-many relationship, or a many-to-one relationship, which is not limited in this disclosure.

[0136] In an exemplary embodiment, a pixel driving circuit in at least one second circuit unit Q2 is neither connected to the first light-emitting unit F1 in the first display area 100A nor connected to the second light-emitting device F2 in the second display area 100B.

[0137] In an exemplary embodiment, the first circuit unit Q1 may be referred to as a normal circuit unit, and the second circuit unit Q2 and the third circuit unit Q3 may be referred to as insertion circuit units. The pixel driving circuit in the first circuit unit Q1 providing a driving signal to the first light-emitting device F1 in the first display area may be referred to as a normal pixel circuit. The pixel driving circuit in the second circuit unit Q2 being neither connected to the first light-emitting device F1 nor connected to the second light-emitting device F2 may be referred to as a dummy pixel circuit. The pixel driving circuit in the third circuit unit Q3 providing a driving signal to the second light-emitting device F2 in the second display area may be referred to as an insertion pixel circuit.

[0138] In an exemplary embodiment, a plurality of first circuit units arranged in sequence along the second direction Y may be referred to as a normal unit column, and a plurality of second circuit units (or a plurality of second circuit units and at least one third circuit unit) arranged in sequence along the second direction Y may be referred to as an insertion unit column. Four normal unit columns may be provided between two adjacent insertion unit columns in the first direction X to form a 4-in-1 structure.

[0139] In an exemplary embodiment, a plurality of third circuit units may be provided at a position in the first display area close to the second display area, and a plurality of second circuit units may be provided at a position in the first display area far from the second display area. The present disclosure does not make any limitation in this regard.

[0140] In an exemplary embodiment, the position of the second display area 100B in the first display area 100A is not limited. It may be located in the upper area or the lower area of the first display area 100A, or may be located at the edge of the first display area 100A. The resolution of the first display area 100A and the second display area 100B may be the same or different. The present disclosure does not make any limitation in this regard.

[0141] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the second display area 100B may be any one or more of the following: rectangle, polygon, circle, and ellipse. The optical device may be an optical sensor such as a fingerprint recognition device, a camera device, or 3D imaging. When the shape of the second display area 100B is a circle, the diameter of the circle may be about 3 mm to 5 mm. When the shape of the second display area 100B is a rectangle, the side length of the rectangle may be about 3 mm to 5 mm. The present disclosure does not make any limitation in this regard.

[0142] Figure 8 FIG. is a schematic structural diagram of a first display area according to an exemplary embodiment of the present disclosure, showing the structure of 16 circuit units in 2 unit rows (the Mth unit row and the M + 1th unit row) and 8 unit columns (the Nth unit column to the N + 7th unit column) in the first display area. Among them, the Nth unit column, the N + 2th unit column to the N + 5th unit column, and the N + 7th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units. The N + 1th unit column and the N + 6th unit column are insertion unit columns, and the circuit units in these unit columns are second circuit units. As Figure 8 shown, in a plane parallel to the display substrate, the driving structure layer of the first display area may include a plurality of first circuit units and a plurality of second circuit units, and at least one first circuit unit or at least one second circuit unit may include a pixel driving circuit.

[0143] In an exemplary embodiment, the pixel driving circuit of at least one first circuit unit may be connected to a first scan signal line 21, a second scan signal line 22, a light emitting signal line 23, a first initial signal line 41, a second initial signal line 42, a first power supply line 71, and a data signal line 73, respectively. The first scan signal line 21, the second scan signal line 22, and the light emitting signal line 23 are configured to provide a first scan signal, a second scan signal, and a light emission control signal to the pixel driving circuit, respectively. The first initial signal line 41 and the second initial signal line 42 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively. The first power supply line 71 is configured to provide a first power supply signal to the pixel driving circuit. The data signal line 73 is configured to provide a data signal to the pixel driving circuit. Among them, multiple signal lines connected to the pixel driving circuit may be located in corresponding circuit units.

[0144] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the light emitting signal line 23, the first initial signal line 41, and the second initial signal line 42 may be linear or zigzag with the main body extending along the first direction X, and the shapes of the first power supply line 71 and the data signal line 73 may be linear or zigzag with the main body extending along the second direction Y.

[0145] In the present disclosure, A extending along the B direction means that A may include a main part and a secondary part connected to the main part. The main part is in the shape of a line, a line segment, or a strip, and the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. The statement "A extends along the B direction" in the following description all means that "the main body part of A extends along the B direction". In an exemplary embodiment, the first direction X may be the unit row direction, and the second direction Y may be the unit column direction.

[0146] In an exemplary embodiment, the pixel driving circuit of at least one first circuit unit may at least include a storage capacitor and multiple transistors. The storage capacitor may include a first electrode plate and a second electrode plate stacked on each other. The multiple transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, and a seventh transistor T7 as a second reset transistor.

[0147] In an exemplary embodiment, a gate electrode of a first transistor T1 is connected to a second scan signal line 22, a first pole of the first transistor T1 is connected to a first initial signal line 41, and a second pole of the first transistor T1 is connected to a first pole of a second transistor T2 and a first plate of a storage capacitor (which is also a gate electrode of a third transistor T3). A gate electrode of the second transistor T2 is connected to a first scan signal line 21, and a second pole of the second transistor T2 is connected to a second pole of the third transistor T3 and a first pole of a sixth transistor T6. A gate electrode of a fourth transistor T4 is connected to the first scan signal line 21, a first pole of the fourth transistor T4 is connected to a data signal line 73, and a second pole of the fourth transistor T4 is connected to a first pole of the third transistor T3 and a second pole of a fifth transistor T5. A gate electrode of the fifth transistor T5 is connected to a light-emitting signal line 23, and a first pole of the fifth transistor T5 is connected to a first power supply line 71. A gate electrode of the sixth transistor T6 is connected to the light-emitting signal line 23, and a second pole of the sixth transistor T6 is connected to a second pole of a seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scan signal line 21, and a first pole of the seventh transistor T7 is connected to a second initial signal line 42.

[0148] In an exemplary embodiment, at least one first circuit unit may further include a second power supply line 72. The second power supply line 72 may be in a straight line shape or a broken line shape with a main body portion extending along a second direction Y, and the second power supply line 72 is configured to be connected to a cathode in a light-emitting device.

[0149] In an exemplary embodiment, a driving structure layer of a first display area may further include at least one first horizontal connection line 81 and at least one first vertical connection line 91. The first initial signal line 41 and the first vertical connection line 91 form a first mesh connection structure on a display substrate, and the first horizontal connection line 81 and the first vertical connection line 91 form another first mesh connection structure on the display substrate.

[0150] Figure 9A and Figure 9B is a schematic structural diagram of a first mesh connection structure according to an exemplary embodiment of the present disclosure. As Figure 8 and Figure 9A shown, the first vertical connection line 91 may be in a broken line shape extending along the second direction Y and may be disposed in a plurality of second circuit units of at least one insertion unit column. For example, the first vertical connection line 91 may be respectively disposed in the (N + 1)th unit column and the (N + 6)th unit column.

[0151] In an exemplary embodiment, the first circuit unit and the second circuit unit may further include a first lateral connection line 81. The shape of the first lateral connection line 81 may be a straight line or a broken line extending along the first direction X. In at least one unit row, the first lateral connection line 81 may be continuously provided in a plurality of first circuit units and a plurality of second circuit units.

[0152] In an exemplary embodiment, the pixel driving circuit in the first circuit unit and the second circuit unit may further include a first connection electrode 51, a third connection electrode 53, and a fifth connection electrode 55. One end of the first connection electrode 51 is connected to the second pole of the first transistor T1 and the first pole of the second transistor T2, and the other end of the first connection electrode 51 is connected to the first electrode plate of the storage capacitor. That is, the second pole of the first transistor T1 and the first pole of the second transistor T2 are connected to the first electrode plate of the storage capacitor through the first connection electrode 51. One end of the third connection electrode 53 is connected to the first pole of the fifth transistor T5, and the other end of the third connection electrode 53 is connected to the second electrode plate of the storage capacitor. That is, the first pole of the fifth transistor T5 is connected to the second electrode plate of the storage capacitor through the third connection electrode 53. One end of the fifth connection electrode 55 is connected to the first pole of the first transistor T1, and the other end of the fifth connection electrode 55 is connected to the first initial signal line 41. That is, the first pole of the first transistor T1 is connected to the first initial signal line 41 through the fifth connection electrode 55.

[0153] In an exemplary embodiment, in at least one first circuit unit, the first connection electrode 51, the third connection electrode 53, and the fifth connection electrode 55 are isolated. In at least one second circuit unit, the first vertical connection line 91 may include the first connection electrode 51, the third connection electrode 53, and the fifth connection electrode 55. The first connection electrode 51 is respectively connected to the third connection electrode 53 and the fifth connection electrode 55. The third connection electrode 53 is connected to the first lateral connection line 81 of this unit row, and the fifth connection electrode 55 is connected to the first lateral connection line 81 of the previous unit row.

[0154] In an exemplary embodiment, at least one second circuit unit may further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The eleventh connection electrode 61 may be disposed between the first connection electrode 51 and the third connection electrode 53 and connected to the first connection electrode 51 and the third connection electrode 53 respectively. The twelfth connection electrode 62 may be disposed between the first connection electrode 51 and the fifth connection electrode 55 and connected to the first connection electrode 51 and the fifth connection electrode 55 respectively. The thirteenth connection electrode 63 may be disposed between the third connection electrode 53 and the first horizontal connection line 81 of this unit row and connected to the third connection electrode 53 and the first horizontal connection line 81 of this unit row respectively. The fourteenth connection electrode 64 may be disposed between the fifth connection electrode 55 and the first horizontal connection line 81 of the previous unit row and connected to the fifth connection electrode 55 and the first horizontal connection line 81 of the previous unit row respectively.

[0155] In an exemplary embodiment, since the first connection electrode 51 and the third connection electrode 53 are interconnected through the eleventh connection electrode 61, the third connection electrode 53 is connected to the thirteenth connection electrode 63, the first connection electrode 51 and the fifth connection electrode 55 are interconnected through the twelfth connection electrode 62, and the fifth connection electrode 55 is connected to the fourteenth connection electrode 64, a first vertical connection line 91 extending along the second direction Y is formed in the second circuit unit.

[0156] In an exemplary embodiment, in at least one second circuit unit, the fourteenth connection electrode 64, the fifth connection electrode 55, the twelfth connection electrode 62, the first connection electrode 51, the eleventh connection electrode 61, the third connection electrode 53, and the thirteenth connection electrode 63 may be an integrally connected structure.

[0157] In an exemplary embodiment, since the thirteenth connection electrode 63 of this unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same first horizontal connection line 81, not only the mutual connection of multiple first vertical connection lines 91 in one unit column is achieved, but also a first mesh connection structure is formed by the first horizontal connection line 81 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the first initial signal line 41, another first mesh connection structure is formed by the first initial signal line 41 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y.

[0158] In an exemplary embodiment, the shape of the first power line 71 may be a straight line or a broken line with the main body extending along the second direction Y, and it may be disposed in the first circuit unit and the second circuit unit. In at least one first circuit unit, the first power line 71 may be connected to the third connection electrode 53. In at least one second circuit unit, the first power line 71 is not connected to the third connection electrode 53.

[0159] As Figure 8 and Figure 9B shown, in an exemplary embodiment, at least one first circuit unit or at least one second circuit unit may further include a second connection electrode 52 and a data connection electrode 74. The second connection electrode 52 is connected to the first pole of the fourth transistor T4, and the data connection electrode 74 is connected to the second connection electrode 52.

[0160] In an exemplary embodiment, in at least one first circuit unit, the data signal line 73 is connected to the data connection electrode 74.

[0161] In an exemplary embodiment, at least one second circuit unit may further include a first data connection block 66. On the one hand, the first data connection block 66 is connected to the second connection electrode 52, and on the other hand, it is connected to the first initial signal line 41.

[0162] In an exemplary embodiment, at least one second circuit unit may further include a first vertical trace 110 and a second vertical trace 120. The shapes of the first vertical trace 110 and the second vertical trace 120 may be a straight line or a broken line with the main body extending along the second direction Y.

[0163] In an exemplary embodiment, in at least one second circuit unit, the first vertical trace 110 is connected to the data connection electrode 74. Since the data connection electrode 74 is connected to the second connection electrode 52, and the second connection electrode 52 is connected to the first initial signal line 41 through the first data connection block 66, the first vertical trace 110 and the first initial signal line 41 have the same potential.

[0164] In an exemplary embodiment, in at least one second circuit unit, the second vertical trace 120 may be connected to the first vertical trace 110 through at least one trace connection line 120-1, so the second vertical trace 120 and the first vertical trace 110 have the same potential.

[0165] In an exemplary embodiment, a first initial signal line 41 extending along a first direction X and a first lateral connection line 81 form a lateral double-line structure for transmitting a first initial signal, and a first vertical connection line 91, a first vertical trace 110, and a second vertical trace 120 extending along a second direction Y form a vertical triple-line structure for transmitting the first initial signal. The lateral double-line structure and the vertical triple-line structure form a plurality of first mesh connection structures in a mesh shape for transmitting the first initial signal.

[0166] In an exemplary embodiment, the position and shape of the first vertical trace 110 in the second circuit unit may be substantially the same as the position and shape of the data signal line 73 in the first circuit unit. The difference is that the data signal line 73 is connected to a data lead-out line for transmitting a data signal after extending to the bonding area, while the first vertical trace 110 is only provided in the display area.

[0167] In an exemplary embodiment, the position and shape of the second vertical trace 120 in the second circuit unit may be substantially the same as the position and shape of the second power supply line 72 in the first circuit unit. The difference is that the second power supply line 72 may be connected to a power supply lead for transmitting a second power supply signal after extending to the bonding area or the upper border area, while the second vertical trace 120 is only provided in the display area.

[0168] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving structure layer of the first area may include a plurality of conductive layers. The plurality of conductive layers may at least include a first gate metal layer (first conductive layer), a second gate metal layer (second conductive layer) provided on a side of the first gate metal layer away from the substrate, a first source-drain metal layer (third conductive layer) provided on a side of the second gate metal layer away from the substrate, a second source-drain metal layer (fourth conductive layer) provided on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer (fifth conductive layer) provided on a side of the second source-drain metal layer away from the substrate. The first scan signal line 21, the second scan signal line 22, the light-emitting signal line 23, and the first electrode plate of the storage capacitor may be provided in the first gate metal layer. The first initial signal line 41, the second initial signal line 42, and the second electrode plate of the storage capacitor may be provided in the second gate metal layer. The first lateral connection line 81 and the first vertical connection line 91 may be provided in the first source-drain metal layer. The first power supply line 71 may be provided in the second source-drain metal layer. The second power supply line 72, the data signal line 73, the first vertical trace 110, and the second vertical trace 120 may be provided in the third source-drain metal layer.

[0169] The preparation process of the substrate is exemplarily described below through this exemplary embodiment. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials or transparent conductive materials, includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" as mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0170] In the exemplary embodiment, taking 16 circuit units in 2 unit rows (the Mth unit row and the (M + 1)th unit row) and 8 unit columns (the Nth unit column to the (N + 7)th unit column) as an example, the preparation process of the display substrate in this embodiment may include the following operations. Among them, the Nth unit column, the (N + 2)th unit column to the (N + 5)th unit column, and the (N + 7)th unit column are normal unit columns, and the circuit units in these unit columns are the first circuit units. The (N + 1)th unit column and the (N + 6)th unit column are inserted unit columns, and the circuit units in these unit columns are the second circuit units.

[0171] (11) Form a semiconductor layer pattern. In the exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate, and patterning the semiconductor thin film through a patterning process to form a first insulating layer disposed on the substrate and a semiconductor layer pattern disposed on the first insulating layer, as Figure 10 shown.

[0172] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the first display area (i.e., each first circuit unit and each second circuit unit, the same hereinafter) may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integrally connected structure.

[0173] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on one side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the third active layer 13 in the second direction Y.

[0174] In an exemplary embodiment, the shape of the third active layer 13 may be in an "Ω" shape, the shape of the first active layer 11 may be in an "n" shape, the shapes of the second active layer 12, the fifth active layer 15, and the sixth active layer 16 may be in an "L" shape, and the shapes of the fourth active layer 14 and the seventh active layer 17 may be in an "I" shape.

[0175] In an exemplary embodiment, the first active layer 11 to the seventh active layer 17 may each include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may simultaneously serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first regions 11-1 of the first active layer, 14-1 of the fourth active layer, 15-1 of the fifth active layer, and 17-1 of the seventh active layer may be separately provided.

[0176] In an exemplary embodiment, the first region 17-1 of the seventh active layer in this circuit unit may be disposed in the circuit unit of the next unit row. For example, the first region 17-1 of the seventh active layer in the circuit unit of the (M-1)-th unit row may be disposed in the circuit unit of the M-th unit row. For another example, the first region 17-1 of the seventh active layer in the circuit unit of the M-th unit row may be disposed in the circuit unit of the (M + 1)-th unit row.

[0177] In an exemplary embodiment, the positions and shapes of the semiconductor layers in multiple circuit units in one unit row may be substantially the same, and the positions and shapes of the semiconductor layers in multiple circuit units in one unit column may be substantially the same.

[0178] In an exemplary embodiment, in this process, the semiconductor layer in the second display region is etched away to form a first insulating layer disposed on the substrate.

[0179] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the semiconductor thin film through a patterning process may include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing a dehydrogenation treatment on the amorphous silicon thin film, performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, patterning the polycrystalline silicon thin film to form a semiconductor layer pattern.

[0180] (12) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the foregoing patterns are formed, patterning the first conductive thin film through a patterning process to form a second insulating layer covering the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, as Figure 11A and Figure 11B shown, Figure 11B is Figure 11A a plan view of the first conductive layer in. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0181] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the first display region may at least include a first scan signal line 21, a second scan signal line 22, a light-emitting signal line 23, and a first electrode plate 31 of a storage capacitor.

[0182] In an exemplary embodiment, the shape of the first electrode plate 31 of the storage capacitor may be rectangular, and chamfers or grooves may be provided at the corners of the rectangular shape. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first electrode plate 31 can serve as both the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0183] In an exemplary embodiment, the shape of the first scan signal line 21 may be linear or polygonal extending along the first direction X, and it may be disposed on one side opposite to the second direction Y of the first electrode plate 31. The region where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, thereby enabling the first scan signal line 21 to control the conduction or disconnection of the fourth transistor T4.

[0184] In an exemplary embodiment, a gate block 21-1 is provided on the first scan signal line 21 of each circuit unit. The shape of the gate block 21-1 may be strip-shaped extending along the second direction Y. The first end of the gate block 21-1 is connected to the side of the first scan signal line 21 close to the first electrode plate 31, and the second end of the gate block 21-1 extends in the direction close to the first electrode plate 31. The region where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2 with a double-gate structure, thereby enabling the first scan signal line 21 to control the conduction or disconnection of the second transistor T2.

[0185] In an exemplary embodiment, in at least one unit row, the first scan signal line 21 and the gate blocks 21-1 of multiple circuit units may be an integrally connected structure.

[0186] In an exemplary embodiment, the shape of the second scan signal line 22 may be linear or polygonal extending along the first direction X, and it may be disposed on the side of the first scan signal line 21 away from the first electrode plate 31. The region where the second scan signal line 22 overlaps with the first active layer in this circuit unit can serve as the gate electrode of the first transistor T1 with a double-gate structure in this circuit unit, thereby enabling the second scan signal line 22 to control the conduction or disconnection of the first transistor T1 in this circuit unit. The region where the second scan signal line 22 overlaps with the seventh active layer of the circuit unit in the previous unit row can serve as the gate electrode of the seventh transistor T7 of the circuit unit in the previous unit row, thereby enabling the second scan signal line 22 to control the conduction or disconnection of the seventh transistor T7 of the circuit unit in the previous unit row.

[0187] In an exemplary embodiment, the first transistor T1 of the present cell row and the seventh transistor T7 in the previous cell row are controlled by the second scan signal line in the same cell row. In an exemplary embodiment, in terms of timing control, the second scan signal line in the present cell row can be equivalent to the first scan signal line in the previous cell row. By arranging the second scan signal line in the present cell row to control both the first transistor T1 in the present cell row and the seventh transistor T7 in the previous cell row, the present disclosure can effectively reduce the number of scan signal lines, which is beneficial to reducing the size of the circuit unit and improving the display resolution.

[0188] In an exemplary embodiment, the shape of the light-emitting signal line 23 can be a straight line or a broken line extending along the first direction X, and it can be disposed on one side of the first electrode plate 31 in the second direction Y. The region where the light-emitting signal line 23 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the region where the light-emitting signal line 23 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6, thereby realizing that the light-emitting signal line 23 can control the conduction or disconnection of the fifth transistor T5 and the sixth transistor T6.

[0189] In an exemplary embodiment, the positions and shapes of the first conductive layers in multiple circuit units in one cell row can be substantially the same, and the positions and shapes of the first conductive layers in multiple circuit units in one cell column can be substantially the same.

[0190] In an exemplary embodiment, in this process, the first conductive layer in the second display area is etched away to form a second insulating layer disposed on the first insulating layer.

[0191] (13) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing patterns are formed, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, as Figure 12A and Figure 12B shown, Figure 12B is Figure 12A a schematic plan view of the second conductive layer in. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0192] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the first display area at least includes: a second electrode plate 32 of a storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43, and a second shielding electrode 44.

[0193] In an exemplary embodiment, the contour of the second electrode plate 32 of the storage capacitor may be rectangular, and chamfers or grooves may be provided at the corners of the rectangular shape. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 may serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 form the storage capacitor.

[0194] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. The shape of the opening 33 may be rectangular and may be located in the middle region of the second electrode plate 32, such that the second electrode plate 32 forms an annular shape. The opening 33 exposes a third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a subsequently formed seventh via hole. The seventh via hole is located within the opening 33 and exposes the first electrode plate 31, enabling a subsequently formed first connection electrode to be connected to the first electrode plate 31.

[0195] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection strip 34. The shape of the plate connection strip 34 may be strip-shaped extending along the first direction X. The plate connection strip 34 may be provided on one side of the second electrode plate 32 in the first direction X or on the opposite side of the first direction X. The first end of the plate connection strip 34 is connected to the second electrode plate 32 in the present circuit unit, and the second end of the plate connection strip 34 is connected to the second electrode plate 32 in an adjacent circuit unit in the first direction X.

[0196] In an exemplary embodiment, the second electrode plates 32 and the plate connection strips 34 in two adjacent circuit units in a unit row may be an integrally connected structure. For example, the second electrode plate 32 in the Nth unit column and the second electrode plate 32 in the (N + 1)th unit column are connected to each other through the plate connection strip 34 to form an integrally connected structure. Since the second electrode plate 32 in each circuit unit is connected to a subsequently formed first power supply line, by forming the second electrode plates 32 of adjacent circuit units into an integrally connected structure, the second electrode plates of the integrally connected structure can be reused as horizontal power supply signal lines, which can ensure that the second electrode plates in a unit row have the same potential, is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0197] In an exemplary embodiment, the shape of the first initial signal line 41 may be linear or polyline-shaped extending along the first direction X, and may be disposed between the first scan signal line 21 and the second scan signal line 22. A first initial connection block 41-1 may be provided on the first initial signal line 41. The shape of the first initial connection block 41-1 may be block-shaped (such as rectangular). The first end of the first initial connection block 41-1 is connected to the side of the first initial signal line 41 away from the second electrode plate 32, and the second end of the first initial connection block 41-1 extends in a direction away from the second electrode plate 32. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a fifth connection electrode formed subsequently.

[0198] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41 and the first initial connection block 41-1 may be an integrally connected structure.

[0199] In an exemplary embodiment, the shape of the second initial signal line 42 may be linear or polyline-shaped extending along the first direction X, and may be disposed on the side of the second scan signal line 22 away from the first scan signal line 21. A second initial connection block 42-1 may be provided on the second initial signal line 42. The shape of the second initial connection block 42-1 may be block-shaped (such as rectangular) and is connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through a sixth connection electrode formed subsequently.

[0200] In an exemplary embodiment, the positive projection of the second initial signal line 42 on the substrate at least partially overlaps with the positive projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The second initial signal line 42 can shield the node between the two gate electrodes in the first transistor T1, avoid the influence of data voltage jump on the first transistor T1, reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0201] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 42 and the second initial connection block 42-1 may be an integrally connected structure.

[0202] In an exemplary embodiment, the shape of the first shielding electrode 43 may be a block shape (such as a rectangle), and it may be disposed on the side of the second electrode plate 32 close to the first scanning signal line 21. The first end of the first shielding electrode 43 is connected to the side of the second electrode plate 32 close to the first scanning signal line 21, and the second end of the first shielding electrode 43 extends in the direction close to the first scanning signal line 21. The orthographic projection of the first shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 43 is configured to shield the node between the two gate electrodes in the second transistor T2, avoid the influence of data voltage jump on the second transistor T2, reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0203] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 32 and the first shielding electrode 43 may be an integrally connected structure.

[0204] In an exemplary embodiment, the shape of the second shielding electrode 44 may be a strip shape extending along the second direction Y, and it may be disposed on the side of the first initial signal line 41 close to the first scanning signal line 21. The first end of the second shielding electrode 44 is connected to the side of the first initial signal line 41 close to the first scanning signal line 21, and the second end of the second shielding electrode 44 extends in the direction close to the first scanning signal line 21. In the first direction X, the second shielding electrode 44 may be located between the first region of the second active layer (which is also the second region of the first active layer) and the first region of the fourth active layer. In an exemplary embodiment, the second shielding electrode 44 is configured to be a shielding structure between the first node and the data writing via, block the influence of data voltage jump on the first node of the pixel driving circuit, reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0205] In an exemplary embodiment, in at least one circuit unit, the first initial signal line 41 and the second shielding electrode 44 may be an integrally connected structure.

[0206] In an exemplary embodiment, the positions and shapes of the second conductive layers in multiple circuit units in one unit row may be substantially the same, and the positions and shapes of the second conductive layers in multiple circuit units in one unit column may be substantially the same.

[0207] In an exemplary embodiment, in this process, the second conductive layer in the second display area is etched away to form a third insulating layer disposed on the second insulating layer.

[0208] (14)Form a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating thin film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating thin film using a patterning process to form a fourth insulating layer covering the second conductive layer, and a plurality of vias are provided on the fourth insulating layer, as Figure 13 shown.

[0209] In an exemplary embodiment, the plurality of vias of each circuit unit in the first display area may at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0210] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer in the first via V1 are etched away to expose the surface of the first region of the first active layer. The first via V1 is configured to enable a fifth connection electrode formed subsequently to be connected to the first region of the first active layer through this via.

[0211] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer in the second via V2 are etched away to expose the surface of the second region of the first active layer (which is also the first region of the second active layer). The second via V2 is configured to enable a first connection electrode formed subsequently to be connected to the second region of the first active layer (which is also the first region of the second active layer) through this via.

[0212] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the first region of the fourth active layer on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer in the third via V3 are etched away to expose the surface of the first region of the fourth active layer. The third via V3 is configured to enable a second connection electrode formed subsequently to be connected to the first region of the fourth active layer through this via. In an exemplary embodiment, the third via V3 serves as the data writing via of the present disclosure.

[0213] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first region of the fifth active layer on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer in the fourth via V4 are etched away to expose the surface of the first region of the fifth active layer. The fourth via V4 is configured to enable a third connection electrode formed subsequently to be connected to the first region of the fifth active layer through this via.

[0214] In an exemplary embodiment, the positive projection of the fifth via V5 on the substrate is within the range of the positive projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer within the fifth via V5 are etched away to expose the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fifth via V5 is configured to enable the fourth connection electrode formed subsequently to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through this via.

[0215] In an exemplary embodiment, the positive projection of the sixth via V6 on the substrate is within the range of the positive projection of the first region of the seventh active layer on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer within the sixth via V6 are etched away to expose the surface of the first region of the seventh active layer. The sixth via V6 is configured to enable the sixth connection electrode formed subsequently to be connected to the first region of the seventh active layer through this via.

[0216] In an exemplary embodiment, the positive projection of the seventh via V7 on the substrate is within the range of the positive projection of the opening 33 on the substrate. The third insulating layer and the fourth insulating layer within the seventh via V7 are etched away to expose the surface of the first electrode plate 31. The seventh via V7 is configured to enable the first connection electrode formed subsequently to be connected to the first electrode plate 31 through this via.

[0217] In an exemplary embodiment, the positive projection of the eighth via V8 on the substrate is within the range of the positive projection of the second electrode plate 32 on the substrate. The fourth insulating layer within the eighth via V8 is etched away to expose the surface of the second electrode plate 32. The eighth via V8 is configured to enable the third connection electrode formed subsequently to be connected to the second electrode plate 32 through this via.

[0218] In an exemplary embodiment, the positive projection of the ninth via V9 on the substrate is within the range of the positive projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate. The fourth insulating layer within the ninth via V9 is etched away to expose the surface of the first initial connection block 41-1. The ninth via V9 is configured to enable the fifth connection electrode formed subsequently to be connected to the first initial connection block 41-1 through this via.

[0219] In an exemplary embodiment, the positive projection of the tenth via V10 on the substrate is within the range of the positive projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate. The fourth insulating layer within the tenth via V10 is etched away to expose the surface of the second initial connection block 42-1. The tenth via V10 is configured to enable the sixth connection electrode formed subsequently to be connected to the second initial connection block 42-1 through this via.

[0220] In an exemplary embodiment, at least one second circuit unit may further include an eleventh via V11. The orthographic projection of the eleventh via V11 on the substrate is within the range of the orthographic projection of the first initial signal line 41 on the substrate. The fourth insulating layer within the eleventh via V11 is etched away to expose the surface of the first initial signal line 41. The eleventh via V11 is configured to enable an initial connection electrode formed subsequently to be connected to the first initial signal line 41 through this via.

[0221] In an exemplary embodiment, in this process, a fourth insulating layer is formed on the third insulating layer in the second display area.

[0222] (15) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as Figure 14A and Figure 14B shown, Figure 14B is Figure 14A a plan view of the third conductive layer in

[0223] In an exemplary embodiment, the third conductive layer of each circuit unit in the first display area includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a first lateral connection line 81.

[0224] In an exemplary embodiment, the shape of the first connection electrode 51 may be a strip shape with a main body portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the second region of the first active layer (which is also the first region of the second active layer) through a second via V2, and the second end of the first connection electrode 51 is connected to the first electrode plate 31 through a seventh via V7. Since the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the mutual connection between the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit.

[0225] In an exemplary embodiment, the shape of the second connection electrode 52 may be a block shape (such as a rectangle). The second connection electrode 52 is connected to the first region of the fourth active layer through a third via V3, and the second connection electrode 52 is configured to be connected to a data connection electrode formed subsequently.

[0226] In an exemplary embodiment, the shape of the third connection electrode 53 may be a strip shape extending along the second direction Y. The first end of the third connection electrode 53 is connected to the first region of the fifth active layer through the fourth via V4, and the second end of the third connection electrode 53 is connected to the second plate 32 through the eighth via V8. The third connection electrode 53 is configured to be connected to a first power supply line formed subsequently. In the exemplary embodiment, the third connection electrode 53 realizes the connection between the first pole of the fifth transistor T5 and the second plate 32 of the storage capacitor, and the first pole of the fifth transistor T5 and the second plate 32 of the storage capacitor have the same potential.

[0227] In an exemplary embodiment, the shape of the fourth connection electrode 54 may be a block shape (such as a rectangle). The fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fifth via V5. The fourth connection electrode 54 is configured to be connected to a first anode connection electrode formed subsequently.

[0228] In an exemplary embodiment, the shape of the fifth connection electrode 55 may be an annular structure (such as a rectangular ring). The annular structure may at least include a first side and a third side extending along the first direction X, and a second side and a fourth side extending along the second direction Y. The first side may be disposed on one side of the third side in the second direction Y, and the second side may be disposed on one side of the fourth side in the first direction X, and the first side, the second side, the third side, and the fourth side are connected in sequence. One end of the first side is connected to the first region of the first active layer through the first via V1, and the other end of the first side is connected to the first initial connection block 41-1 through the ninth via V9. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the fifth connection electrode 55 realizes the first initial signal line 41 writing the first initial signal into the first pole of the first transistor T1.

[0229] In an exemplary embodiment, the shape of the sixth connection electrode 56 may be a strip shape extending along the second direction Y. The first end of the sixth connection electrode 56 is connected to the first region of the seventh active layer through the sixth via V6, and the second end of the sixth connection electrode 56 is connected to the second initial connection block 42-1 through the tenth via V10. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the sixth connection electrode 56 realizes the second initial signal line 42 writing the second initial signal into the first pole of the seventh transistor T7.

[0230] In an exemplary embodiment, the shape of the first horizontal connection line 81 may be a straight line shape or a broken line shape extending along the first direction X, and may be located between the light-emitting signal line 23 of the current unit row and the second initial signal line 42 of the next unit row.

[0231] In an exemplary embodiment, the third conductive layer of at least one second circuit unit may further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64.

[0232] In an exemplary embodiment, the eleventh connection electrode 61 may be in a strip shape extending along the first direction X, may be disposed between the first connection electrode 51 and the third connection electrode 53, a first end of the eleventh connection electrode 61 is connected to the first connection electrode 51, and a second end of the eleventh connection electrode 61 is connected to the third connection electrode 53.

[0233] In an exemplary embodiment, the twelfth connection electrode 62 may be in a strip shape extending along the second direction Y, may be disposed between the first connection electrode 51 and the fifth connection electrode 55, a first end of the twelfth connection electrode 62 is connected to the first connection electrode 51, and a second end of the twelfth connection electrode 62 is connected to the fifth connection electrode 55.

[0234] In an exemplary embodiment, the thirteenth connection electrode 63 may be in a strip shape extending along the second direction Y, may be disposed between the third connection electrode 53 and the first horizontal connection line 81 of this unit row, a first end of the thirteenth connection electrode 63 is connected to the third connection electrode 53, and a second end of the thirteenth connection electrode 63 is connected to the first horizontal connection line 81 of this unit row. In an exemplary embodiment, the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the first horizontal connection line 81.

[0235] In an exemplary embodiment, the fourteenth connection electrode 64 may be in a strip shape extending along the second direction Y, may be disposed between a third side of the fifth connection electrode 55 of this unit row and the first horizontal connection line 81 of the previous unit row, a first end of the fourteenth connection electrode 64 is connected to the third side of the fifth connection electrode 55 of this unit row, and a second end of the fourteenth connection electrode 64 is connected to the first horizontal connection line 81 of the previous unit row, thereby realizing the connection between the fifth connection electrode 55 of this unit row and the first horizontal connection line 81 of the previous unit row.

[0236] In an exemplary embodiment, since the first connection electrode 51 and the third connection electrode 53 are connected to each other through the eleventh connection electrode 61, the third connection electrode 53 is connected to the thirteenth connection electrode 63, the first connection electrode 51 and the fifth connection electrode 55 are connected to each other through the twelfth connection electrode 62, and the fifth connection electrode 55 is connected to the fourteenth connection electrode 64, a first vertical connection line 91 extending along the second direction Y is formed in the second circuit unit, and the first vertical connection line 91 is connected to a first node N1 of a pixel driving circuit in the second circuit unit.

[0237] In an exemplary embodiment, in at least one second circuit unit, the fourteenth connection electrode 64, the fifth connection electrode 55, the twelfth connection electrode 62, the first connection electrode 51, the eleventh connection electrode 61, the third connection electrode 53, and the thirteenth connection electrode 63 may be an integrally connected structure.

[0238] In an exemplary embodiment, since the thirteenth connection electrode 63 of this unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same first horizontal connection line 81, not only the mutual connection of multiple first vertical connection lines 91 in one unit column is achieved, but also a first mesh communication structure is formed by the first horizontal connection line 81 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y. This first mesh communication structure is formed by the third conductive layer. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the first initial signal line 41, another first mesh communication structure is formed by the first initial signal line 41 extending along the first direction X and the first vertical connection line 91 extending along the second direction Y. This first mesh communication structure is formed by the second conductive layer and the third conductive layer respectively. In this way, both of the two first mesh communication structures are mesh structures for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0239] In an exemplary embodiment, in the first display area, the circuit units are arranged in a compressed manner, and the wiring density of the pixel driving circuit is large. The static electricity generated in the process of the manufacturing process is likely to accumulate, resulting in damage and short circuit of the transistors in the pixel driving circuit. For example, the first scan signal line, the second scan signal line, and the light emitting signal line are all relatively long signal lines in the first conductive layer, and the first initial signal line and the second initial signal line are all relatively long signal lines in the second conductive layer. If there is no way to transfer other signal lines, static electricity is likely to accumulate on these relatively long signal lines. The present disclosure forms two first mesh communication structures for transmitting the first initial signal in the second conductive layer and the third conductive layer, which can transfer the static electricity on the relatively long signal lines in the first conductive layer and the second conductive layer to the third conductive layer and release it from the third conductive layer, effectively eliminating the static electricity accumulation generated in the manufacturing process, effectively avoiding the damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality.

[0240] In an exemplary embodiment, the first initial signal line 41 extending along the first direction X and the first horizontal connection line 81 form a horizontal double-line structure for transmitting the first initial signal, which can further reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal.

[0241] In an exemplary embodiment, the third conductive layer of at least one second circuit unit may further include a first data connection block 66. The shape of the first data connection block 66 may be block-shaped (such as rectangular), and may be disposed on a side of the second connection electrode 52 close to the first initial signal line 41 and connected to the second connection electrode 52. The first data connection block 66 is connected to the first initial signal line 41 through an eleventh via V11.

[0242] In an exemplary embodiment, in at least one second circuit unit, the second connection electrode 52 and the first data connection block 66 may be an integrally connected structure.

[0243] In some other embodiments, for a display substrate with a fanout in panel (FIP) structure, the unit row may further include a first data connection line. The first end of the first data connection line is connected to a data signal line, and the second end of the first data connection line is connected to a second data connection line. The first data connection line and the first horizontal connection line may be disposed on the same layer and formed synchronously through the same patterning process. A first break may be provided between the first data connection line and the first horizontal connection line disposed in the same unit row, and the first break is configured to achieve mutual insulation between the first data connection line and the first horizontal connection line.

[0244] In an exemplary embodiment, in this process, the third conductive layer in the second display area is etched away.

[0245] (16) Form a fifth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planarization layer pattern may include: on the substrate on which the foregoing patterns are formed, first deposit a fifth insulating thin film, then coat a first planarizing thin film, and perform patterning on the fifth insulating thin film and the first planarizing thin film by a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planarization layer disposed on the fifth insulating layer. A plurality of vias are provided on the fifth insulating layer and the first planarization layer, as Figure 15 shown.

[0246] In an exemplary embodiment, the plurality of vias in each circuit unit in the first display area at least include: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0247] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the second connection electrode 52 on the substrate. The fifth insulating layer and the first planarization layer in the twenty-first via V21 are removed, exposing the surface of the second connection electrode 52. The twenty-first via V21 is configured to enable a data connection electrode formed subsequently to be connected to the second connection electrode 52 through this via.

[0248] In an exemplary embodiment, the positive projection of the twenty-second via V22 on the substrate is located within the range of the positive projection of the third connection electrode 53 on the substrate. The fifth insulating layer and the first planarization layer within the twenty-second via V22 are removed to expose the surface of the third connection electrode 53. The twenty-second via V22 is configured to enable the first power line formed subsequently to be connected to the third connection electrode 53 through this via.

[0249] In an exemplary embodiment, the twenty-second via V22 may be provided only in the first circuit unit. Since the third connection electrodes 53 in the second circuit unit form the first vertical connection line and are connected to the first horizontal connection line, the twenty-second via V22 is not provided in the second circuit unit, that is, the first power line formed subsequently is not connected to the third connection electrode 53 in the second circuit unit.

[0250] In an exemplary embodiment, the positive projection of the twenty-third via V23 on the substrate is located within the range of the positive projection of the fourth connection electrode 54 on the substrate. The fifth insulating layer and the first planarization layer within the twenty-third via V23 are removed to expose the surface of the fourth connection electrode 54. The twenty-third via V23 is configured to enable the first anode connection electrode formed subsequently to be connected to the fourth connection electrode 54 through this via.

[0251] In an exemplary embodiment, in this process, a fifth insulating layer provided on the fourth insulating layer and a first planarization layer provided on the fifth insulating layer are formed in the second display region.

[0252] In some other embodiments, the display substrate may not be provided with the fifth insulating layer, and the present disclosure does not limit this here.

[0253] (17) Form a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer provided on the first planarization layer, as Figure 16A and Figure 16B shown, Figure 16B is Figure 16A a plan view of the fourth conductive layer in

[0254] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the first display region at least includes: a first power line 71, a data connection electrode 74, and a first anode connection electrode 75.

[0255] In an exemplary embodiment, the shape of the first power line 71 may be a straight line or a broken line with the main body portion extending along the second direction Y. In the first circuit unit, the first power line 71 is connected to the third connection electrode 53 through the twenty-second via V22. Since the third connection electrode 53 is connected to the first region of the fifth active layer and the second electrode plate 32 through vias respectively, the first power line 71 can write the first power signal into the second electrode plate 32 of the storage capacitor and the first pole of the fifth transistor T5 respectively. Since the second circuit unit is formed with a first vertical connection line, the first power line 71 in the second circuit unit is not connected to the third connection electrode 53 in the second circuit unit.

[0256] In an exemplary embodiment, multiple first power lines 71 may extend to the bonding region or the upper border region and be connected to the power leads for transmitting the first power signal.

[0257] In an exemplary embodiment, the first power line 71 may be a broken line with variable width, and the positive projection of the first power line 71 on the substrate at least partially overlaps with the positive projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71 with a constant potential can shield the first node N1, avoid the influence of data voltage jump on the first node N1, improve the working stability of the pixel driving circuit, and improve the display effect.

[0258] In an exemplary embodiment, the positive projection of the first power line 71 on the substrate may include the positive projection of the first connection electrode 51 on the substrate.

[0259] In an exemplary embodiment, the shape of the data connection electrode 74 may be a block shape (such as a rectangle), the data connection electrode 74 is connected to the second connection electrode 52 through the twenty-first via V21, and the data connection electrode 74 is configured to be connected to a subsequent formed data signal line or a first vertical trace.

[0260] In an exemplary embodiment, the shape of the first anode connection electrode 75 may be a block shape (such as a rectangle), the first anode connection electrode 75 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the first anode connection electrode 75 is configured to be connected to a subsequent formed second anode connection electrode.

[0261] In an exemplary embodiment, in this process, the fourth conductive layer in the second display region is etched away.

[0262] (18)Form a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization thin film on the substrate on which the foregoing pattern is formed, patterning the second planarization thin film using a patterning process to form a second planarization layer covering the fourth conductive layer pattern, and a plurality of vias are provided on the second planarization layer, as Figure 17 shown.

[0263] In an exemplary embodiment, the plurality of vias in each circuit unit in the first display area at least include a thirty-first via V31 and a thirty-second via V32.

[0264] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is within the range of the orthographic projection of the data connection electrode 74 on the substrate. The second planarization layer in the thirty-first via V31 is removed to expose the surface of the data connection electrode 74. The thirty-first via V31 is configured to enable a subsequently formed data signal line or a first vertical trace to be connected to the data connection electrode 74 through this via.

[0265] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is within the range of the orthographic projection of the first anode connection electrode 75 on the substrate. The second planarization layer in the thirty-second via V32 is removed to expose the surface of the first anode connection electrode 75. The thirty-second via V32 is configured to enable a subsequently formed second anode connection electrode to be connected to the first anode connection electrode 75 through this via.

[0266] In an exemplary embodiment, in this process, a second planarization layer is formed on the first planarization layer in the second display area.

[0267] (19)Form a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive thin film using a patterning process to form a fifth conductive layer provided on the first planarization layer, as Figure 18A and Figure 18B shown, Figure 18B is Figure 18A a schematic plan view of the fifth conductive layer in. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source-drain metal (SD3) layer.

[0268] In an exemplary embodiment, the fifth conductive layer of each first circuit unit in the first display area at least includes a second power supply line 72, a data signal line 73, and a second anode connection electrode 76. The fifth conductive layer of each second circuit unit in the first display area at least includes a second anode connection electrode 76, a first vertical trace 110, and a second vertical trace 120.

[0269] In an exemplary embodiment, the shape of the second power supply line 72 in the first circuit unit may be linear or zigzag with the main body extending along the second direction Y, and the second power supply line 72 is configured to be connected to the cathode of the light-emitting device. In an exemplary embodiment, multiple second power supply lines 72 may extend to the bonding region or the upper border region and be connected to the power supply leads for transmitting the second power signal, realizing the structure of the second power supply line in the panel (VSS in Panel, abbreviated as SIP), which can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, improve the display quality and display performance, and can also reduce the border width, increase the screen-to-body ratio, and facilitate the realization of a full-screen display.

[0270] In an exemplary embodiment, the shape of the data signal line 73 in the first circuit unit may be linear or zigzag with the main body extending along the second direction Y, and the data signal line 73 is connected to the data connection electrode 74 through the thirty-first via V31. Since the data connection electrode 74 in the first circuit unit is connected to the second connection electrode 52 through a via, and the second connection electrode 52 is connected to the first region of the fourth active layer through a via, the data signal line 73 can write the data signal to the first pole of the fourth transistor T4 in the first circuit unit.

[0271] In an exemplary embodiment, the shape of the second anode connection electrode 76 may be block-shaped (such as rectangular), and the second anode connection electrode 76 is connected to the first anode connection electrode 75 through the thirty-second via V32. Among them, the second anode connection electrode 76 in the first circuit unit is configured to be connected to the anode in the subsequently formed first display region 100A. Since the first anode connection electrode 75 in the first circuit unit is connected to the fourth connection electrode 54 through a via, and the fourth connection electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a via, the pixel driving circuit in the first circuit unit can output a driving current to the light-emitting device in the first display region 100A. The second anode connection electrode 76 in the second circuit unit is configured to be a dummy electrode, which is neither connected to the anode in the first display region 100A nor connected to the anode in the second display region 100B.

[0272] In an exemplary embodiment, the shape of the first vertical trace 110 in the second circuit unit may be linear or zigzag with the main body extending along the second direction Y. The first vertical trace 110 is connected to the data connection electrode 74 through the thirty-first via V31. Since the data connection electrode 74 is connected to the second connection electrode 52 through a via, the second connection electrode 52 is not only connected to the first region of the fourth active layer through a via, but also connected to the first data connection block 66. The first data connection block 66 is connected to the first initial signal line 41 through a via. Therefore, the first vertical trace 110 and the first initial signal line 41 have the same potential, which can not only prevent the first vertical trace 110 from floating, but also enable the first vertical trace 110 to write the first initial signal into the first pole of the fourth transistor T4 in the second circuit unit.

[0273] In an exemplary embodiment, the first vertical connection line formed in the second circuit unit is connected to the first node N1 of the pixel driving circuit in the second circuit unit. By writing the first initial signal into the first pole of the fourth transistor T4 in the second circuit unit, the present disclosure can effectively prevent a short circuit between the first node N1 and the second node N2 when the fourth transistor T4 is turned on.

[0274] In an exemplary embodiment, the position and shape of the first vertical trace 110 in the second circuit unit may be substantially the same as the position and shape of the data signal line 73 in the first circuit unit. The difference is that the data signal line 73 extends to the bonding area and is connected to the data lead-out line for transmitting the data signal, while the first vertical trace 110 is only provided in the display area.

[0275] In an exemplary embodiment, the shape of the second vertical trace 120 in the second circuit unit may be linear or zigzag with the main body extending along the second direction Y. In at least one second circuit unit, the first vertical trace 110 and the second vertical trace 120 may be connected to each other through at least one trace connection line 120-1. The shape of the trace connection line 120-1 may be linear or zigzag with the main body extending along the first direction X. The first end of the trace connection line 120-1 is connected to the first vertical trace 110, and the second end of the trace connection line 120-1 is connected to the second vertical trace 120.

[0276] In an exemplary embodiment, in at least one insertion unit column, the first vertical trace 110, the second vertical trace 120, and the trace connection line 120-1 may be an integrally connected structure.

[0277] In an exemplary embodiment, the position and shape of the second vertical trace 120 in the second circuit unit may be substantially the same as those of the second power line 72 in the first circuit unit. The difference is that the second power line 72 may extend to the bonding area or the upper border area and then be connected to a power lead for transmitting a second power signal, while the second vertical trace 120 is only provided in the display area.

[0278] In an exemplary embodiment, since the first vertical connection line 91 and the first vertical trace 110 transmit a first initial signal, and the second vertical trace 120 is connected to the first vertical trace 110, the second vertical trace 120 also transmits the first initial signal. The first vertical connection line 91, the first vertical trace 110, and the second vertical trace 120 extending along the second direction Y form a vertical three-line structure for transmitting the first initial signal, which can further reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal.

[0279] In an exemplary embodiment, the horizontal two-line structure composed of the first initial signal line 41 and the first horizontal connection line 81 and the vertical three-line structure composed of the first vertical connection line 91, the first vertical trace 110, and the second vertical trace 120 can form a plurality of first mesh connection structures, which can minimize the resistance of the first initial signal line and minimize the voltage drop of the first initial signal.

[0280] In some other embodiments, for the display substrate of the FIP structure, the normal unit column may further include a second data connection line. The first end of the second data connection line is connected to the first data connection line, and the second end of the second data connection line extends to the bonding area and then is connected to a data lead-out line. The second data connection line and the second power line may be arranged on the same layer and formed synchronously through the same patterning process. A second break may be provided between the second data connection line and the second power line arranged in the same unit column, and the second break is configured to achieve electrical insulation between the second data connection line and the second power line.

[0281] In an exemplary embodiment, in this process, the fifth conductive layer in the second display area is etched away.

[0282] The subsequent preparation process may include forming a third planarization layer. An anode via is provided on the third planarization layer, and the anode via exposes the surface of the second anode connection electrode. The anode via is configured to enable the subsequently formed anode to be connected to the second anode connection electrode through the via.

[0283] So far, the driving structure layer of this embodiment has been prepared on the substrate. The driving structure layer in the first display area may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, a fourth conductive layer, a second planarization layer, a fifth conductive layer, and a third planarization layer sequentially arranged on the substrate. The semiconductor layer may at least include the active layers of multiple transistors. The first conductive layer may at least include a first scan signal line, a second scan signal line, a light-emitting signal line, and a first electrode plate of a storage capacitor. The second conductive layer may at least include a first initial signal line, a second initial signal line, and a second electrode plate of the storage capacitor. The third conductive layer may at least include a first horizontal connection line, a first vertical connection line, and multiple connection electrodes. The fourth conductive layer may at least include a first power supply line. The fifth conductive layer may at least include a data signal line, a second power supply line, a first vertical trace, and a second vertical trace.

[0284] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer may be amorphous silicon (a-si).

[0285] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), etc., or may be made of an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc., and may be a single-layer structure, or may be a multi-layer composite structure such as Ti / Al / Ti, etc. The first planarization layer, the second planarization layer, and the third planarization layer may be made of an organic material such as resin or polyimide.

[0286] In an exemplary embodiment, after the driving structure layer is prepared, the light-emitting structure layer may be prepared on the driving structure layer, and the encapsulation structure layer may be prepared on the light-emitting structure layer, which will not be elaborated here.

[0287] An exemplary embodiment of the present disclosure provides a display substrate. By forming a first horizontal connection line extending along the first direction X and a first vertical connection line extending along the second direction Y in the display area, and the first horizontal connection line and the first vertical connection line form a first mesh connection structure for transmitting the first initial signal in a mesh shape, the resistance of the first initial signal line can be effectively reduced, the voltage drop of the first initial signal can be reduced, the uniformity of the first initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0288] In an embodiment of the present disclosure, a horizontal double-line structure for transmitting the first initial signal is respectively formed in the second conductive layer and the third conductive layer, and a vertical triple-line structure for transmitting the first initial signal is respectively formed in the third conductive layer and the fifth conductive layer. The horizontal double-line structure and the vertical triple-line structure can form a plurality of first mesh connection structures, which can minimize the resistance of the first initial signal line and minimize the voltage drop of the first initial signal.

[0289] In an embodiment of the present disclosure, by forming the first mesh connection structure for transmitting the first initial signal, the static electricity of the longer signal lines in the first conductive layer and the second conductive layer can be transferred to the third conductive layer and released from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality. In addition, forming the first mesh connection structure on the display substrate can also effectively improve the holemura phenomenon.

[0290] In the embodiments of the present disclosure, by adopting a compression method to arrange circuit units, and the first display area adopts a 4-in-1 structure, it can not only reduce the circuit differences in each area, avoid defects such as off-screen watermarks caused by circuit differences, but also has a reasonable structural layout and will not affect the transmittance, etc.

[0291] In the embodiments of the present disclosure, by arranging a second power line in the display area, an SIP structure is realized. It can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, improve the display quality and display performance, but also can reduce the frame width, increase the screen-to-body ratio, and is beneficial to realizing a full-screen display.

[0292] In the embodiments of the present disclosure, by setting the first vertical trace to be connected to the first initial signal line, it can not only prevent the first vertical trace in the second circuit unit from being floating, but also effectively prevent short circuits between nodes in the pixel driving circuit.

[0293] The manufacturing process of the embodiments of the present disclosure can be well compatible with the existing manufacturing processes, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield.

[0294] Figure 19 It is a schematic structural diagram of another first display area of an exemplary embodiment of the present disclosure. In the exemplary embodiment, the main structure of the display substrate in this embodiment is basically the same as that of the Figure 8 display substrate shown. The difference is that the driving structure layer of the first display area may further include at least one second horizontal connection line 82 and at least one second vertical connection line 92. The second initial signal line 42 and the second vertical connection line 92 form a second mesh connection structure on the display substrate, and the second horizontal connection line  82 and the second vertical connection line 92 form another second mesh connection structure on the display substrate.

[0295] Figure 20A and Figure 20B It is a schematic structural diagram of a second mesh connection structure of an exemplary embodiment of the present disclosure. As shown in Figure 19 and Figure 20A shown, the shape of the second horizontal connection line 82 may be a straight line or a broken line extending along the first direction X. In at least one unit row, the second horizontal connection line 82 may be continuously arranged in a plurality of first circuit units and a plurality of second circuit units. The shape of the second vertical connection line 92 may be a broken line extending along the second direction Y, and may be arranged in a plurality of second circuit units of at least one insertion unit column. For example, the second vertical connection line 92 may be respectively arranged in the (N + 1)th unit column and the (N + 6)th unit column.

[0296] In an exemplary embodiment, the first circuit unit and the second circuit unit may further include a sixth connection electrode 56. One end of the sixth connection electrode 56 is connected to the first pole of the seventh transistor T7, and the other end of the sixth connection electrode 56 is connected to the second initial signal line 42.

[0297] In an exemplary embodiment, at least one second circuit unit may further include a first connection electrode 51, a third connection electrode 53, a fifth connection electrode 55, an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The above structure is substantially the same as that of the Figure 8 illustrated embodiment. The difference is that the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the second lateral connection line 82, and the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 of this unit row and the second lateral connection line 82 of the previous unit row. Thus, a second vertical connection line 92 extending along the second direction Y is formed in the second circuit unit.

[0298] In an exemplary embodiment, at least one second circuit unit may further include a fifteenth connection electrode 65. The fifteenth connection electrode 65 may be disposed between the fifth connection electrode 55 and the sixth connection electrode 56 and is respectively connected to the fifth connection electrode 55 and the sixth connection electrode 56.

[0299] In an exemplary embodiment, since the thirteenth connection electrode 63 of this unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same second lateral connection line 82, not only the mutual connection of multiple second vertical connection lines 92 in one unit column is realized, but also a second mesh communication structure is formed by the second lateral connection line 82 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the sixth connection electrode 56 through the fifteenth connection electrode 65, and the sixth connection electrode 56 is connected to the second initial signal line 42, another second mesh communication structure is formed by the second initial signal line 42 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y.

[0300] In an exemplary embodiment, in at least one first circuit unit, the first power supply line 71 may be connected to the third connection electrode 53. In at least one second circuit unit, the first power supply line 71 is not connected to the third connection electrode 53.

[0301] Such as Figure 19 and Figure 20BAs shown, at least one first circuit unit may further include a second data connection block 67, and the second data connection block 67 is connected to the sixth connection electrode 56. At least one second circuit unit may further include a third data connection block 68, the third data connection block 68 is connected to the data connection electrode 74, and the third data connection block 68 is connected to the second data connection block 67 through a via.

[0302] In an exemplary embodiment, the first vertical trace 110 in the second circuit unit is connected to the data connection electrode 74 through a via. Since the data connection electrode 74 is connected to the third data connection block 68, the third data connection block 68 is connected to the second data connection block 67 through a via, the second data connection block 67 is connected to the sixth connection electrode 56, and the sixth connection electrode 56 is connected to the second initial signal line 42, the first vertical trace 110 and the second initial signal line 42 have the same potential. Since the second vertical trace 120 is connected to the first vertical trace 110 through the trace connection line 120-1, the second vertical trace 120 and the first vertical trace 110 have the same potential.

[0303] In an exemplary embodiment, the second initial signal line 42 extending along the first direction X and the second lateral connection line 82 form a lateral double-line structure for transmitting the second initial signal, and the second vertical connection line 92, the first vertical trace 110, and the second vertical trace 120 extending along the second direction Y form a vertical triple-line structure for transmitting the second initial signal. The lateral double-line structure and the vertical triple-line structure form a plurality of second mesh connection structures in a mesh shape for transmitting the second initial signal.

[0304] In an exemplary embodiment, the preparation process of the present embodiment for the substrate may include the following operations.

[0305] (21) to (23) sequentially form a semiconductor layer, a first conductive layer, and a second conductive layer pattern. The formation process and the formed semiconductor layer, first conductive layer, and second conductive layer pattern are substantially the same as those in Figure 8 the illustrated embodiment.

[0306] (24) Form a fourth insulating layer pattern. The formation process and the formed fourth insulating layer pattern are substantially the same as those in Figure 8 the illustrated embodiment. The difference is that, since a second vertical connection line is formed in the second circuit unit in the subsequent process and the second vertical connection line is connected to the second initial signal line, the second circuit unit does not provide a ninth via V9, that is, the fifth connection electrode of the second circuit unit formed subsequently is not connected to the first initial connection block 41-1. In addition, no eleventh via is formed on the fourth insulating layer in the present embodiment, as shown in Figure 21 the illustration.

[0307] (25)Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as Figure 22A and Figure 22B shown, Figure 22B which Figure 22A is a plan view of the third conductive layer in

[0308] In an exemplary embodiment, the third conductive layer of each circuit unit in the first display area at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a second lateral connection line 82. The structures of the first connection electrode 51 to the sixth connection electrode 56 are substantially the same as those in Figure 8 the embodiment shown.

[0309] In an exemplary embodiment, the shape of the second lateral connection line 82 may be a straight line or a broken line extending along the first direction X, and it may be located between the light-emitting signal line 23 of this unit row and the second initial signal line 42 of the next unit row.

[0310] In an exemplary embodiment, the third conductive layer of at least one second circuit unit may further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The above structures are substantially the same as those in Figure 8 the embodiment shown. The difference is that the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the second lateral connection line 82, and the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 of this unit row and the second lateral connection line 82 of the previous unit row. Therefore, a second vertical connection line 92 extending along the second direction Y is formed in the second circuit unit, and the second vertical connection line 92 is connected to the first node N1 of the pixel driving circuit in the second circuit unit.

[0311] In an exemplary embodiment, the third conductive layer of at least one second circuit unit may further include a fifteenth connection electrode 65. The shape of the fifteenth connection electrode 65 may be a strip shape extending along the first direction X, and it may be disposed between the fifth connection electrode 55 and the sixth connection electrode 56. The first end of the fifteenth connection electrode 65 is connected to the fifth connection electrode 55, and the second end of the fifteenth connection electrode 65 is connected to the sixth connection electrode 56.

[0312] In an exemplary embodiment, since the thirteenth connection electrode 63 of this unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same second lateral connection line 82, not only the mutual connection of multiple second vertical connection lines 92 in a unit column is achieved, but also a second mesh communication structure is formed by the second lateral connection line 82 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y. This second mesh communication structure is formed by the third conductive layer. Since the fifth connection electrode 55 in the first vertical connection line 91 is connected to the sixth connection electrode 56 through the fifteenth connection electrode 65, and the sixth connection electrode 56 is connected to the second initial signal line 42, another second mesh communication structure is formed by the second initial signal line 42 extending along the first direction X and the second vertical connection line 92 extending along the second direction Y. This second mesh communication structure is formed by the second conductive layer and the third conductive layer. In this way, both of the two second mesh communication structures are mesh structures for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0313] In an exemplary embodiment, the present disclosure forms two second mesh communication structures for transmitting the second initial signal in the second conductive layer and the third conductive layer, which can transfer the static electricity of the longer signal lines in the first conductive layer and the second conductive layer to the third conductive layer and release it from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality.

[0314] In an exemplary embodiment, the second initial signal line 42 and the second lateral connection line 82 extending along the first direction X form a horizontal double-line structure for transmitting the second initial signal, which can further reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal.

[0315] In an exemplary embodiment, the third conductive layer of at least one first circuit unit may further include a second data connection block 67. The shape of the second data connection block 67 may be block-shaped (such as rectangular), may be disposed on the side of the sixth connection electrode 56 away from the fifth connection electrode 55, and is connected to the sixth connection electrode 56. The first data connection block 66 is configured to be connected to a third data connection block formed subsequently.

[0316] In an exemplary embodiment, in at least one first circuit unit, the sixth connection electrode 56 and the second data connection block 67 may be an integrally connected structure.

[0317] In an exemplary embodiment, the second data connection block 67 may be disposed in a first circuit unit on one side of the first direction X of the second circuit unit. For example, for the (N + 1)-th unit column being an insertion unit column, the second data connection block 67 may be disposed in at least one first circuit unit of the (N + 2)-th unit column. Another example is that for the (N + 6)-th unit column being an insertion unit column, the second data connection block 67 may be disposed in at least one first circuit unit of the (N + 7)-th unit column.

[0318] (26) Form a fifth insulating layer and a first planarized layer pattern. The forming process and the formed fifth insulating layer and first planarized layer pattern are substantially the same as those in the Figure 8 illustrated embodiment, except that a twenty-fourth via V24 is further provided on the fifth insulating layer and the first planarized layer, as Figure 23 illustrated.

[0319] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is within the range of the orthographic projection of the second data connection block 67 on the substrate. The fifth insulating layer and the first planarized layer within the twenty-fourth via V24 are removed to expose the surface of the second data connection block 67. The twenty-fourth via V24 is configured to enable a third data connection block formed subsequently to be connected to the second data connection block 67 through this via.

[0320] In an exemplary embodiment, the twenty-second via V22 may be provided only in the first circuit unit. Since the third connection electrodes 53 in the second circuit unit form a second vertical connection line and are connected to the second horizontal connection line, the twenty-second via V22 is not provided in the second circuit unit, that is, the first power supply line formed subsequently is not connected to the third connection electrode 53 in the second circuit unit.

[0321] (27) Form a fourth conductive layer pattern. The forming process and the formed fourth conductive layer pattern are substantially the same as those in the Figure 8 illustrated embodiment, except that the fourth conductive layer of at least one second circuit unit may further include a third data connection block 68, as Figure 24A and Figure 24B illustrated, Figure 24B being Figure 24A a plan view of the fourth conductive layer in

[0322] In an exemplary embodiment, the shape of the third data connection block 68 disposed in the second circuit unit may be in a block shape (such as a rectangle), may be disposed on a side of the data connection electrode 74 close to the second data connection block 67, and is connected to the data connection electrode 74. The third data connection block 68 is connected to the second data connection block 67 through the twenty-fourth via V24.

[0323] In an exemplary embodiment, in at least one second circuit unit, the data connection electrode 74 and the third data connection block 68 may be integrally connected to each other.

[0324] In an exemplary embodiment, since the second circuit unit is formed with a second vertical connection line, the first power supply line 71 in the second circuit unit and the third connection electrode 53 in the second circuit unit are not connected.

[0325] (28) The second planar layer and the fifth conductive layer pattern are sequentially formed. The forming process and the formed second planar layer and fifth conductive layer pattern are substantially the same as those in the Figure 8 illustrated embodiment, as Figure 19 illustrated.

[0326] In an exemplary embodiment, the first vertical trace 110 in the second circuit unit is connected to the data connection electrode 74 through a via. Since the data connection electrode 74 is connected to the third data connection block 68, the third data connection block 68 is connected to the second data connection block 67 through a via, the second data connection block 67 is connected to the sixth connection electrode 56, and the sixth connection electrode 56 is connected to the second initial signal line 42, the first vertical trace 110 and the second initial signal line 42 have the same potential. This can not only prevent the first vertical trace 110 from floating, but also enable the first vertical trace 110 to write the second initial signal to the first pole of the fourth transistor T4 in the second circuit unit. By writing the second initial signal to the first pole of the fourth transistor T4 in the second circuit unit, the present disclosure can effectively prevent a short circuit between the first node N1 and the second node N2 when the fourth transistor T4 is turned on.

[0327] In an exemplary embodiment, since the second vertical trace 120 is connected to the first vertical trace 110 through the trace connection line 120-1, the second vertical trace 120 and the first vertical trace 110 have the same potential. In this way, the second vertical connection line 92, the first vertical trace 110, and the second vertical trace 120 extending along the second direction Y form a vertical three-line structure for transmitting the second initial signal, which can further reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal.

[0328] In an exemplary embodiment, the horizontal two-line structure composed of the second initial signal line 42 and the second horizontal connection line 82 and the vertical three-line structure composed of the second vertical connection line 92, the first vertical trace 110, and the second vertical trace 120 can form a plurality of second mesh connection structures, which can minimize the resistance of the second initial signal line and minimize the voltage drop of the second initial signal.

[0329] An exemplary embodiment of the present disclosure provides a display substrate. By forming a second horizontal connection line extending along the first direction X and a second vertical connection line extending along the second direction Y in the display area, and the second horizontal connection line and the second vertical connection line form a second mesh connection structure for transmitting a second initial signal in a mesh shape, the resistance of the second initial signal line can be effectively reduced, the voltage drop of the second initial signal can be reduced, the uniformity of the second initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0330] In an embodiment of the present disclosure, a horizontal double-line structure for transmitting a second initial signal is respectively formed in the second conductive layer and the third conductive layer, and a vertical triple-line structure for transmitting a second initial signal is respectively formed in the third conductive layer and the fifth conductive layer. The horizontal double-line structure and the vertical triple-line structure can form a plurality of second mesh connection structures, which can minimize the resistance of the second initial signal line and minimize the voltage drop of the second initial signal.

[0331] In an embodiment of the present disclosure, by forming a second mesh connection structure for transmitting a second initial signal, the static electricity of the longer signal lines in the first conductive layer and the second conductive layer can be transferred to the third conductive layer and released from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality. In addition, forming a second mesh connection structure on the display substrate can also effectively improve the holemura phenomenon.

[0332] In an embodiment of the present disclosure, by setting the first vertical trace to be connected to the second initial signal line, not only can the floating of the first vertical trace in the second circuit unit be avoided, but also the short circuit between the nodes in the pixel driving circuit can be effectively avoided.

[0333] Figure 25 It is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the main structure of the display substrate in this embodiment is basically the same as the main structure of the aforementioned display substrate. The difference is that the driving structure layer of the first display area may further include at least one third horizontal connection line 83 and at least one third vertical connection line 93. The third horizontal connection line 83 and the first power supply line 71 form a third mesh connection structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third mesh connection structure on the display substrate.

[0334] Figure 26A and Figure 26B It is a schematic structural diagram of a third mesh connection structure according to an exemplary embodiment of the present disclosure. As Figure 25 and Figure 26AAs shown, the shape of the third horizontal connection line 83 can be a straight line or a broken line extending along the first direction X. In at least one unit row, the third horizontal connection line 83 can be continuously arranged in a plurality of first circuit units and a plurality of second circuit units. The shape of the third vertical connection line 93 can be a broken line extending along the second direction Y, and can be arranged in a plurality of second circuit units of at least one insertion unit column. For example, the third vertical connection line 93 can be respectively arranged in the (N + 1)th unit column and the (N + 6)th unit column.

[0335] In an exemplary embodiment, at least one second circuit unit may further include a first connection electrode 51, a third connection electrode 53, a fifth connection electrode 55, an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The above structure is basically the same as that in Figure 8 the shown embodiment. The difference is that the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the third horizontal connection line 83, and the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 of the current unit row and the third horizontal connection line 83 of the previous unit row. Therefore, a third vertical connection line 93 extending along the second direction Y is formed in the second circuit unit.

[0336] In an exemplary embodiment, since the thirteenth connection electrode 63 of the current unit row and the fourteenth connection electrode 64 of the next unit row are connected to the same third horizontal connection line 83, not only the mutual connection of a plurality of third vertical connection lines 93 in one unit column is realized, but also a third mesh connection structure is formed by the third horizontal connection line 83 extending along the first direction X and the third vertical connection line 93 extending along the second direction Y. Since the third connection electrode 53 in the third vertical connection line 93 is connected to the first power supply line 71, another third mesh connection structure is formed by the third horizontal connection line 83 extending along the first direction X and the first power supply line 71 extending along the second direction Y.

[0337] In an exemplary embodiment, since the second electrode plate and the electrode plate connection strip in the second conductive layer form a horizontal power supply signal line 30, the horizontal power supply signal line 30 can form another third mesh connection structure with the third vertical connection line 93.

[0338] In an exemplary embodiment, the first power supply line 71 is connected not only to the third connection electrode 53 in the first circuit unit, but also to the third connection electrode 53 in the second circuit unit.

[0339] As Figure 25 and Figure 26B shown, at least one second circuit unit may further include a power supply connection block 71-1, and the power supply connection block 71-1 is respectively connected to the first power supply line 71 and the data connection electrode 74.

[0340] In an exemplary embodiment, the first vertical trace 110 in the second circuit unit is connected to the data connection electrode 74 through a via. Since the data connection electrode 74 is connected to the first power line 71 through the power connection block 71-1, the first vertical trace 110 and the first power line 71 have the same potential. Since the second vertical trace 120 is connected to the first vertical trace 110 through the trace connection line 120-1, the second vertical trace 120 and the first vertical trace 110 have the same potential.

[0341] In an exemplary embodiment, the horizontal power signal line 30 extending along the first direction X and the third horizontal connection line 83 form a horizontal double-line structure for transmitting the first power signal, and the first power line 71, the third vertical connection line 93, the first vertical trace 110, and the second vertical trace 120 extending along the second direction Y form a vertical four-line structure for transmitting the first power signal. The horizontal double-line structure and the vertical four-line structure form a plurality of third mesh connection structures in a mesh shape for transmitting the first power signal.

[0342] In an exemplary embodiment, the preparation process of the present embodiment for the display substrate may include the following operations.

[0343] (31) to (34) sequentially form a semiconductor layer, a first conductive layer, a second conductive layer, and a fourth insulating layer pattern. The formation process and the formed semiconductor layer, first conductive layer, second conductive layer, and fourth insulating layer pattern are substantially the same as those in the Figure 8 illustrated embodiment. The difference is that, in the subsequent process, a third vertical connection line is formed in the second circuit unit, and the third vertical connection line is configured to be connected to the first power line. Therefore, the second circuit unit does not have the ninth via V9. In addition, the eleventh via is not formed on the fourth insulating layer in this embodiment.

[0344] (35) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing patterns are formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer provided on the fourth insulating layer, as Figure 27A and Figure 27B shown, Figure 27B is Figure 27A the plan view of the third conductive layer in

[0345] In an exemplary embodiment, the third conductive layer of each circuit unit in the first display area at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, and a third horizontal connection line 83. The structures of the first connection electrode 51 to the sixth connection electrode 56 are the same as those in Figure 8The illustrated embodiments are substantially the same.

[0346] In an exemplary embodiment, the shape of the third horizontal connection line 83 may be a straight line or a broken line extending along the first direction X, and it may be located between the light-emitting signal line 23 of the current cell row and the first power supply line 71 of the next cell row.

[0347] In an exemplary embodiment, the third conductive layer of at least one second circuit unit may further include an eleventh connection electrode 61, a twelfth connection electrode 62, a thirteenth connection electrode 63, and a fourteenth connection electrode 64. The above structure is Figure 8 substantially the same as the illustrated embodiment. The difference is that the thirteenth connection electrode 63 realizes the connection between the third connection electrode 53 and the third horizontal connection line 83, and the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 of the current cell row and the third horizontal connection line 83 of the previous cell row. Thus, a third vertical connection line 93 extending along the second direction Y is formed in the second circuit unit, and the third vertical connection line 93 is connected to the first node N1 of the pixel driving circuit in the second circuit unit.

[0348] In an exemplary embodiment, since the thirteenth connection electrode 63 of the current cell row and the fourteenth connection electrode 64 of the next cell row are connected to the same third horizontal connection line 83, not only the mutual connection of multiple third vertical connection lines 93 in a unit column is realized, but also a third mesh communication structure is formed by the third horizontal connection line 83 extending along the first direction X and the third vertical connection line 93 extending along the second direction Y. This third mesh communication structure is formed by the third conductive layer. Since the third connection electrode 53 in the third vertical connection line 93 is connected to the subsequently formed first power supply line, another third mesh communication structure is formed by the third horizontal connection line 83 extending along the first direction X and the first power supply line extending along the second direction Y. This third mesh communication structure is formed by the third conductive layer and the fourth conductive layer. In this way, both of the two third mesh communication structures are mesh structures for transmitting the first power signal, which can effectively reduce the resistance of the first power supply line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0349] In an exemplary embodiment, by forming multiple third mesh communication structures for transmitting the first power signal in the second conductive layer and the third conductive layer, the present disclosure can transfer the static electricity of the longer signal lines in the first conductive layer and the second conductive layer to the third conductive layer and release it from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of the transistors in the pixel driving circuit, and improving the product quality.

[0350] In an exemplary embodiment, third vertical connection line 93 can extend to the binding area or the upper frame area and connect to the power lead that transmits the first power signal, effectively preventing the occurrence of process static electricity. By providing a third vertical connection line to connect the first power signal at the upper frame and the binding area, the present disclosure allows static electricity to be conducted from the display area to the upper frame and the binding area through the meshed interconnection structure, further eliminating static electricity accumulation generated during the process.

[0351] (36) forming a fifth insulating layer and a first planar layer pattern, the formation process and the formed fifth insulating layer and the first planar layer pattern Figure 8 The embodiment shown is basically the same, except that the twenty-second via hole V22 can be provided in the first circuit unit and the second circuit unit, that is, the first power lines formed subsequently are connected to the third connection electrodes 53 in the first circuit unit and the second circuit unit, as shown in FIG. Figure 28 shown.

[0352] (37) forming a fourth conductive layer pattern, forming process and the formed fourth conductive layer pattern and Figure 8 The embodiment shown is substantially the same, except that the fourth conductive layer of at least one second circuit unit may further include a power connection block 71-1, such as Figure 29A and Figure 29B As shown, Figure 29B for Figure 29A Schematic plan view of the fourth conductive layer in FIG.

[0353] In an exemplary embodiment, the first power line 71 may be connected to the third connection electrode 53 in the first and second circuit units through the twenty-second via hole V22 .

[0354] In an exemplary embodiment, the power connection block 71-1 set in the second circuit unit can be block-shaped (such as rectangular) and can be set between the first power line 71 and the data connection electrode 74. The first end of the power connection block 71-1 is connected to the data connection electrode 74, and the second end of the power connection block 71-1 is connected to the first power line 71.

[0355] In an exemplary embodiment, in at least one second circuit unit, the first power line 71 , the power connection block 71 - 1 , and the data connection electrode 74 may be an integrated structure connected to each other.

[0356] (38) The second flat layer and the fifth conductive layer patterns are formed in sequence, and the formation process and the formed second flat layer and the fifth conductive layer patterns are Figure 8 The embodiments shown are essentially the same, as Figure 25 shown.

[0357] In an exemplary embodiment, a first vertical trace 110 in a second circuit unit is connected to a data connection electrode 74 through a via. Since the data connection electrode 74 is connected to a first power supply line 71 through a power supply connection block 71-1, the first vertical trace 110 and the first power supply line 71 have the same potential, which can not only prevent the first vertical trace 110 from floating, but also enable the first vertical trace 110 to write a first power signal into a first pole of a fourth transistor T4 in the second circuit unit.

[0358] In an exemplary embodiment, since a second vertical trace 120 is connected to the first vertical trace 110 through a trace connection line 120-1, the second vertical trace 120 and the first vertical trace 110 have the same potential. In this way, the first power supply line 71, a third vertical connection line 93, the first vertical trace 110, and the second vertical trace 120 extending along the second direction Y form a vertical four-line structure for transmitting the first power signal, which can further reduce the resistance of the first power supply signal line and reduce the voltage drop of the first power signal.

[0359] In an exemplary embodiment, a horizontal two-line structure of a horizontal power supply signal line 30 and a third horizontal connection line 83 and a vertical four-line structure composed of the first power supply line 71, the third vertical connection line 93, the first vertical trace 110, and the second vertical trace 120 can form a plurality of third mesh connection structures, which can minimize the resistance of the first power supply signal line and minimize the voltage drop of the first power signal.

[0360] An exemplary embodiment of the present disclosure provides a display substrate. By forming a third horizontal connection line extending along a first direction X and a third vertical connection line extending along a second direction Y in a display area, and the third horizontal connection line and the third vertical connection line form a mesh third mesh connection structure for transmitting a first power signal, the resistance of the first power supply signal line can be effectively reduced, the voltage drop of the first power signal can be reduced, the uniformity of the first power signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0361] An embodiment of the present disclosure forms a horizontal two-line structure for transmitting a first power signal in a second conductive layer and a third conductive layer, and respectively forms a vertical four-line structure for transmitting a first power signal in a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The horizontal two-line structure and the vertical four-line structure can form a plurality of third mesh connection structures, which can minimize the resistance of the first power supply signal line and minimize the voltage drop of the first power signal.

[0362] In an embodiment of the present disclosure, by forming a third mesh connection structure for transmitting a first power signal, the static electricity of the longer signal lines in the first conductive layer and the second conductive layer can be transferred to the third conductive layer and released from the third conductive layer, effectively eliminating the static electricity accumulation generated in the process, effectively avoiding the damage and short circuit of transistors in the pixel driving circuit, and improving the product quality.

[0363] In an embodiment of the present disclosure, by connecting the second vertical trace of the second circuit unit to the first power line, not only can the floating of the second vertical trace in the second circuit unit be avoided, but also the short circuit between nodes in the pixel driving circuit can be effectively avoided.

[0364] Figure 30 FIG. 7 is a schematic structural diagram of another first display area according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the display substrate in this embodiment is substantially the same as the main structure of the display substrate shown above. The difference is that a first mesh connection structure and a second mesh connection structure are simultaneously formed on the display substrate.

[0365] As Figure 30 shown, the driving structure layer of the first display area may further include at least one first horizontal connection line 81, at least one second horizontal connection line 82, at least one first vertical connection line 91, and at least one second vertical connection line 92. The first initial signal line 41 and the first vertical connection line 91 form a first mesh connection structure on the display substrate, the first horizontal connection line 81 and the first vertical connection line 91 form another first mesh connection structure on the display substrate, the second initial signal line 42 and the second vertical connection line 92 form a second mesh connection structure on the display substrate, and the second horizontal connection line 82 and the second vertical connection line 92 form another second mesh connection structure on the display substrate.

[0366] In an exemplary embodiment, the first horizontal connection line 81 and the second horizontal connection line 82 may be disposed on the same layer and formed synchronously through the same patterning process. In at least one unit row, the first horizontal connection line 81 and the second horizontal connection line 82 may be alternately disposed in the first direction X. A first break K1 is disposed between the adjacent first horizontal connection line 81 and the second horizontal connection line 82 in the first direction X, and the first break K1 is configured to achieve mutual insulation between the first horizontal connection line 81 and the second horizontal connection line 82. For example, the first horizontal connection line 81 extending along the first direction X may be disposed in the (N + 1)th unit column to the (N + 5)th unit column, and the second horizontal connection line 82 extending along the first direction X may be disposed in the (N + 6)th unit column to the (N + 10)th unit column.

[0367] In an exemplary embodiment, the first vertical connection line 91 and the second vertical connection line 92 may be disposed on the same layer and formed synchronously through the same patterning process. The first vertical connection line 91 and the second vertical connection line 92 may be respectively disposed in different insertion unit columns, and the first vertical connection line 91 and the second vertical connection line 92 may be alternately disposed in the first direction X. For example, the first vertical connection line 91 extending along the second direction Y may be disposed in the (N + 1)-th unit column, and the second vertical connection line 92 extending along the second direction Y may be disposed in the (N + 6)-th unit column.

[0368] In an exemplary embodiment, the driving structure layer of the first display area may further include a first vertical trace and a second vertical trace, and their structures may be substantially the same as those in the foregoing embodiments and will not be described herein again.

[0369] In an exemplary embodiment, in the area where the (N + 1)-th unit column to the (N + 5)-th unit column are located, the first initial signal line 41 extending along the first direction X and the first horizontal connection line 81 form a horizontal double-line structure for transmitting the first initial signal, and the first vertical connection line 91, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the first initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of first mesh connection structures for transmitting the first initial signal in a mesh shape.

[0370] In an exemplary embodiment, in the area where the (N + 6)-th unit column to the (N + 10)-th unit column are located, the second initial signal line 42 extending along the first direction X and the second horizontal connection line 82 form a horizontal double-line structure for transmitting the second initial signal, and the second vertical connection line 92, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the second initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of second mesh connection structures for transmitting the second initial signal in a mesh shape.

[0371] In an exemplary embodiment, the first mesh connection structure and the second mesh connection structure may be arranged in units of repeating columns. For example, the first mesh connection structure may be arranged in a repeating column including the (N + 1)-th unit column to the (N + 5)-th unit column, and the second mesh connection structure may be arranged in a repeating column including the (N + 6)-th unit column to the (N + 10)-th unit column. The first mesh connection structure and the second mesh connection structure are alternately arranged in the first direction X. For another example, the first mesh connection structure may be arranged in a repeating column including the (N + 1)-th unit column to the (N + 5)-th unit column, the first mesh connection structure may be arranged in a repeating column including the (N + 6)-th unit column to the (N + 10)-th unit column, the second mesh connection structure may be arranged in a repeating column including the (N + 11)-th unit column to the (N + 15)-th unit column, and the second mesh connection structure may be arranged in a repeating column including the (N + 16)-th unit column to the (N + 20)-th unit column. The first mesh connection structure, the first mesh connection structure, the second mesh connection structure, and the second mesh connection structure are alternately arranged in the first direction X. The present disclosure does not make any limitation here.

[0372] In the embodiment of the present disclosure, by forming the first mesh connection structure for transmitting the first initial signal and the second mesh connection structure for transmitting the second initial signal in the display area, the resistance of the first initial signal line and the second initial signal line can be effectively reduced, the signal voltage drop can be reduced, the display uniformity can be effectively improved, and the display quality and display performance can be enhanced.

[0373] Figure 31 FIG. 7 is a schematic structural diagram of another first display area according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the display substrate in this embodiment is substantially the same as that of the Figure 30 display substrate shown, except that a first mesh connection structure and a third mesh connection structure are simultaneously formed on the display substrate.

[0374] As shown in Figure 31 FIG. 8, the driving structure layer of the first display area may further include at least one first horizontal connection line 81, at least one third horizontal connection line 83, at least one first vertical connection line 91, and at least one third vertical connection line 93. The first initial signal line 41 and the first vertical connection line 91 form a first mesh connection structure on the display substrate, the first horizontal connection line 81 and the first vertical connection line 91 form another first mesh connection structure on the display substrate, the third horizontal connection line 83 and the first power supply line 71 form a third mesh connection structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third mesh connection structure on the display substrate.

[0375] In an exemplary embodiment, the first horizontal connection line 81 and the third horizontal connection line 83 may be disposed on the same layer and formed synchronously through the same patterning process. In at least one unit row, the first horizontal connection line 81 and the third horizontal connection line 83 may be alternately disposed in the first direction X, and a first break K1 is provided between the adjacent first horizontal connection line 81 and third horizontal connection line 83 in the first direction X, and the first break K1 is configured to achieve mutual insulation between the first horizontal connection line 81 and the third horizontal connection line 83. For example, the first horizontal connection line 81 extending along the first direction X may be disposed in the (N + 1)th unit column to the (N + 5)th unit column, and the third horizontal connection line 83 extending along the first direction X may be disposed in the (N + 6)th unit column to the (N + 10)th unit column.

[0376] In an exemplary embodiment, the first vertical connection line 91 and the third vertical connection line 93 may be disposed on the same layer and formed synchronously through the same patterning process. The first vertical connection line 91 and the third vertical connection line 93 may be respectively disposed in different inserted unit columns, and the first vertical connection line 91 and the third vertical connection line 93 may be alternately disposed in the first direction X. For example, the first vertical connection line 91 extending along the second direction Y may be disposed in the (N + 1)th unit column, and the third vertical connection line 93 extending along the second direction Y may be disposed in the (N + 6)th unit column.

[0377] In an exemplary embodiment, the driving structure layer of the first display area may further include a first vertical trace and a second vertical trace, and its structure may be substantially the same as that of the foregoing embodiment, and will not be described herein again.

[0378] In an exemplary embodiment, in the area where the (N + 1)th unit column to the (N + 5)th unit column are located, the first initial signal line 41 extending along the first direction X and the first horizontal connection line 81 form a horizontal double-line structure for transmitting the first initial signal, and the first vertical connection line 91, the first vertical trace and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the first initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of first mesh connection structures for transmitting the first initial signal in a mesh shape.

[0379] In an exemplary embodiment, in the area where the (N + 6)th unit column to the (N + 10)th unit column are located, the horizontal power supply signal line 30 extending along the first direction X and the third horizontal connection line 83 form a horizontal double-line structure for transmitting the first power supply signal, and the first power supply line 71, the third vertical connection line 93, the first vertical trace and the second vertical trace extending along the second direction Y form a vertical quadruple-line structure for transmitting the first power supply signal. The horizontal double-line structure and the vertical quadruple-line structure form a plurality of third mesh connection structures for transmitting a power supply signal in a mesh shape.

[0380] In an exemplary embodiment, the first mesh connection structure and the third mesh connection structure may be arranged in units of repeated columns. For example, the first mesh connection structure may be arranged in a repeated column including the (N + 1)-th unit column to the (N + 5)-th unit column, and the third mesh connection structure may be arranged in a repeated column including the (N + 6)-th unit column to the (N + 10)-th unit column. The first mesh connection structure and the third mesh connection structure are alternately arranged in the first direction X. For another example, the first mesh connection structure may be arranged in a repeated column including the (N + 1)-th unit column to the (N + 5)-th unit column, the first mesh connection structure may be arranged in a repeated column including the (N + 6)-th unit column to the (N + 10)-th unit column, the third mesh connection structure may be arranged in a repeated column including the (N + 11)-th unit column to the (N + 15)-th unit column, and the third mesh connection structure may be arranged in a repeated column including the (N + 16)-th unit column to the (N + 20)-th unit column. The first mesh connection structure, the first mesh connection structure, the third mesh connection structure, and the third mesh connection structure are alternately arranged in the first direction X. The present disclosure does not limit this here.

[0381] In the embodiment of the present disclosure, by forming a first mesh connection structure for transmitting a first initial signal and a third mesh connection structure for transmitting a first power signal in the display area, the resistance of the first initial signal line and the first power line can be effectively reduced, the signal voltage drop can be reduced, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0382] Figure 32 This is a schematic structural diagram of another first display area in an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the display substrate in this embodiment is substantially the same as that of the Figure 30 display substrate shown, except that a second mesh connection structure and a third mesh connection structure are formed on the display substrate at the same time.

[0383] As Figure 32 shown, the driving structure layer of the first display area may further include at least one second horizontal connection line 82, at least one third horizontal connection line 83, at least one second vertical connection line 92, and at least one third vertical connection line 93. The second initial signal line 42 and the second vertical connection line 92 form a second mesh connection structure on the display substrate, the second horizontal connection line 82 and the second vertical connection line 92 form another second mesh connection structure on the display substrate, the third horizontal connection line 83 and the first power line 71 form a third mesh connection structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third mesh connection structure on the display substrate.

[0384] In an exemplary embodiment, the second horizontal connection line 82 and the third horizontal connection line 83 may be disposed on the same layer and formed synchronously through the same patterning process. In at least one unit row, the second horizontal connection line 82 and the third horizontal connection line 83 may be alternately disposed in the first direction X. A first break K1 is provided between the adjacent second horizontal connection line 82 and third horizontal connection line 83 in the first direction X, and the first break K1 is configured to achieve electrical insulation between the second horizontal connection line 82 and the third horizontal connection line 83. For example, the second horizontal connection line 82 extending along the first direction X may be disposed in the (N + 1)th unit column to the (N + 5)th unit column, and the third horizontal connection line 83 extending along the first direction X may be disposed in the (N + 6)th unit column to the (N + 10)th unit column.

[0385] In an exemplary embodiment, the second vertical connection line 92 and the third vertical connection line 93 may be disposed on the same layer and formed synchronously through the same patterning process. The second vertical connection line 92 and the third vertical connection line 93 may be respectively disposed in different insertion unit columns, and the second vertical connection line 92 and the third vertical connection line 93 may be alternately disposed in the first direction X. For example, the second vertical connection line 92 extending along the second direction Y may be disposed in the (N + 1)th unit column, and the third vertical connection line 93 extending along the second direction Y may be disposed in the (N + 6)th unit column.

[0386] In an exemplary embodiment, the driving structure layer of the first display area may further include a first vertical trace and a second vertical trace, and their structures may be substantially the same as those in the foregoing embodiments, which will not be described herein again.

[0387] In an exemplary embodiment, in the area where the (N + 1)th unit column to the (N + 5)th unit column are located, the second initial signal line 42 extending along the first direction X and the second horizontal connection line 82 form a horizontal double-line structure for transmitting the second initial signal, and the second vertical connection line 92, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the second initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of second mesh connection structures for transmitting the second initial signal in a mesh shape.

[0388] In an exemplary embodiment, in the area where the (N + 6)th unit column to the (N + 10)th unit column are located, the horizontal power supply signal line 30 extending along the first direction X and the third horizontal connection line 83 form a horizontal double-line structure for transmitting the first power supply signal, and the first power supply line 71, the third vertical connection line 93, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical quadruple-line structure for transmitting the first power supply signal. The horizontal double-line structure and the vertical quadruple-line structure form a plurality of third mesh connection structures for transmitting the first power supply signal in a mesh shape.

[0389] In an exemplary embodiment, the second mesh connection structure and the third mesh connection structure may be provided in units of repeating columns. For example, the second mesh connection structure may be provided in a repeating column including the (N + 1)th unit column to the (N + 5)th unit column, and the third mesh connection structure may be provided in a repeating column including the (N + 6)th unit column to the (N + 10)th unit column. The second mesh connection structure and the third mesh connection structure are alternately arranged in the first direction X. Another example is that the second mesh connection structure may be provided in a repeating column including the (N + 1)th unit column to the (N + 5)th unit column, the second mesh connection structure may be provided in a repeating column including the (N + 6)th unit column to the (N + 10)th unit column, the third mesh connection structure may be provided in a repeating column including the (N + 11)th unit column to the (N + 15)th unit column, and the third mesh connection structure may be provided in a repeating column including the (N + 16)th unit column to the (N + 20)th unit column. The second mesh connection structure, the second mesh connection structure, the third mesh connection structure, and the third mesh connection structure are alternately arranged in the first direction X. The present disclosure does not make any limitation here.

[0390] In the embodiment of the present disclosure, by forming a second mesh connection structure for transmitting a second initial signal and a third mesh connection structure for transmitting a first power signal in the display area, the resistance of the second initial signal line and the first power line can be effectively reduced, the signal voltage drop can be reduced, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0391] Figure 33 This is a schematic structural diagram of another first display area in an exemplary embodiment of the present disclosure. In an exemplary embodiment, the main structure of the display substrate in this embodiment is substantially the same as the main structure of the display substrate shown above. The difference is that a first mesh connection structure, a second mesh connection structure, and a third mesh connection structure are simultaneously formed on the display substrate.

[0392] Such as Figure 33As shown, the driving structure layer of the first display area may further include at least one first horizontal connection line 81, at least one second horizontal connection line 82, at least one third horizontal connection line 83, at least one first vertical connection line 91, at least one second vertical connection line 92, and at least one third vertical connection line 93. The first initial signal line 41 and the first vertical connection line 91 form a first mesh connection structure on the display substrate, and the first horizontal connection line 81 and the first vertical connection line 91 form another first mesh connection structure on the display substrate. The second initial signal line 42 and the second vertical connection line 92 form a second mesh connection structure on the display substrate, and the second horizontal connection line 82 and the second vertical connection line 92 form another second mesh connection structure on the display substrate. The third horizontal connection line 83 and the first power supply line 71 form a third mesh connection structure on the display substrate, and the third horizontal connection line 83 and the third vertical connection line 93 form another third mesh connection structure on the display substrate.

[0393] In an exemplary embodiment, the first horizontal connection line 81, the second horizontal connection line 82, and the third horizontal connection line 83 may be arranged in the same layer and formed synchronously through the same patterning process. In at least one unit row, the first horizontal connection line 81, the second horizontal connection line 82, and the third horizontal connection line 83 may be periodically arranged in the first direction X. A first break K1 is provided between the adjacent first horizontal connection line 81 and the second horizontal connection line 82 in the first direction X, a first break K1 is provided between the adjacent second horizontal connection line 82 and the third horizontal connection line 83 in the first direction X, a first break K1 is provided between the adjacent third horizontal connection line 83 and the first horizontal connection line 81 in the first direction X, and the first break K1 is configured to achieve mutual insulation between the adjacent horizontal connection lines. For example, the first horizontal connection line 81 extending along the first direction X may be arranged in the (N + 1)-th unit column to the (N + 5)-th unit column, the second horizontal connection line 82 extending along the first direction X may be arranged in the (N + 6)-th unit column to the (N + 10)-th unit column, and the third horizontal connection line 83 extending along the first direction X may be arranged in the (N + 11)-th unit column to the (N + 15)-th unit column.

[0394] In an exemplary embodiment, the first vertical connection line 91, the second vertical connection line 92, and the third vertical connection line 93 may be arranged on the same layer and formed synchronously through the same patterning process. The first vertical connection line 91, the second vertical connection line 92, and the third vertical connection line 93 may be respectively arranged in different insertion unit columns, and the first vertical connection line 91, the second vertical connection line 92, and the third vertical connection line 93 may be periodically arranged in the first direction X. For example, the first vertical connection line 91 extending along the second direction Y may be arranged in the (N + 1)-th unit column, the second vertical connection line 92 extending along the second direction Y may be arranged in the (N + 6)-th unit column, and the third vertical connection line 93 extending along the second direction Y may be arranged in the (N + 11)-th unit column.

[0395] In an exemplary embodiment, the driving structure layer of the first display area may further include a first vertical trace and a second vertical trace, and their structures may be substantially the same as those of the foregoing embodiments and will not be described herein again.

[0396] In an exemplary embodiment, in the area where the (N + 1)-th unit column to the (N + 5)-th unit column are located, the first initial signal line 41 extending along the first direction X and the first horizontal connection line 81 form a horizontal double-line structure for transmitting the first initial signal, and the first vertical connection line 91, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the first initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of first mesh connection structures for transmitting the first initial signal in a mesh pattern.

[0397] In an exemplary embodiment, in the area where the (N + 6)-th unit column to the (N + 10)-th unit column are located, the second initial signal line 42 extending along the first direction X and the second horizontal connection line 82 form a horizontal double-line structure for transmitting the second initial signal, and the second vertical connection line 92, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical triple-line structure for transmitting the second initial signal. The horizontal double-line structure and the vertical triple-line structure form a plurality of second mesh connection structures for transmitting the second initial signal in a mesh pattern.

[0398] In an exemplary embodiment, in the area where the (N + 11)-th unit column to the (N + 15)-th unit column are located, the horizontal power signal line 30 extending along the first direction X and the third horizontal connection line 83 form a horizontal double-line structure for transmitting the first power signal, and the first power line 71, the third vertical connection line 93, the first vertical trace, and the second vertical trace extending along the second direction Y form a vertical quadruple-line structure for transmitting the first power signal. The horizontal double-line structure and the vertical quadruple-line structure form a plurality of third mesh connection structures for transmitting a power signal in a mesh pattern.

[0399] In an exemplary embodiment, the first mesh connection structure, the second mesh connection structure, and the third mesh connection structure may be arranged in units of repeated columns. For example, the first mesh connection structure may be arranged in a repeated column including the (N + 1)-th unit column to the (N + 5)-th unit column, the second mesh connection structure may be arranged in a repeated column including the (N + 6)-th unit column to the (N + 10)-th unit column, and the third mesh connection structure may be arranged in a repeated column including the (N + 11)-th unit column to the (N + 15)-th unit column. The first mesh connection structure, the second mesh connection structure, and the third mesh connection structure are periodically arranged in the first direction X, and the present disclosure does not limit this here.

[0400] In the embodiments of the present disclosure, by forming a first mesh connection structure for transmitting a first initial signal, a second mesh connection structure for transmitting a second initial signal, and a third mesh connection structure for transmitting a first power signal in the display area, the resistance of the first initial signal line, the second initial signal line, and the first power line can be effectively reduced, the signal voltage drop can be reduced, the display uniformity can be effectively improved, and the display quality and display performance can be enhanced.

[0401] The foregoing structure shown in the present disclosure and its manufacturing process are merely an exemplary illustration. In an exemplary embodiment, the corresponding structure may be changed according to actual needs, and the lithography process may be increased or decreased.

[0402] In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), etc., and the present disclosure does not limit this here.

[0403] The present disclosure also provides a display device, and the display device includes the foregoing display substrate. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present invention are not limited thereto.

[0404] Although the disclosed embodiments are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that, It includes a first display area and a second display area. The first display area at least partially surrounds the second display area. The first display area is configured to perform image display, and the second display area is configured to perform image display and transmit light. The first display area includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. The driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The light-emitting structure layer includes a plurality of first light-emitting devices. The circuit units at least include a first circuit unit and a second circuit unit. Both the first circuit unit and the second circuit unit include a pixel driving circuit. The pixel driving circuit of the first circuit unit is connected to the first light-emitting device, and the pixel driving circuit of the second circuit unit is not connected to the first light-emitting device. At least one second circuit unit further includes at least one horizontal connection line extending along a first direction and at least one vertical connection line extending along a second direction. The horizontal connection line is connected to the vertical connection line to form a mesh communication structure. The first direction and the second direction intersect.

2. The display substrate according to claim 1, characterized in that, In at least one first circuit unit, the pixel driving circuit at least includes a storage capacitor, a first reset transistor, a second reset transistor, and a first light-emitting control transistor. A first pole of the first reset transistor is connected to a first initial signal line through a fifth connection electrode. A second pole of the first reset transistor is connected to a first plate of the storage capacitor through a first connection electrode. A first pole of the first light-emitting control transistor is connected to a second plate of the storage capacitor through a third connection electrode. A first pole of the second reset transistor is connected to a second initial signal line through a sixth connection electrode. The third connection electrode is connected to a first power supply line. A plurality of the second plates in at least one unit row form a horizontal power supply signal line. In at least one second circuit unit, the vertical connection line includes the first connection electrode, the third connection electrode, and the fifth connection electrode. The first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode. The third connection electrode is connected to the horizontal connection line of the present unit row, and the fifth connection electrode is connected to the horizontal connection line of the previous unit row.

3. The display substrate according to claim 2, wherein At least one second circuit unit further includes an eleventh connection electrode, a twelfth connection electrode, a thirteenth connection electrode, and a fourteenth connection electrode; the eleventh connection electrode is disposed between the first connection electrode and the third connection electrode and is respectively connected to the first connection electrode and the third connection electrode; the twelfth connection electrode is disposed between the first connection electrode and the fifth connection electrode and is respectively connected to the first connection electrode and the fifth connection electrode; the thirteenth connection electrode is disposed between the third connection electrode and the horizontal connection line of this unit row and is respectively connected to the third connection electrode and the horizontal connection line of this unit row; the fourteenth connection electrode is disposed between the fifth connection electrode and the horizontal connection line of the previous unit row and is respectively connected to the fifth connection electrode and the horizontal connection line of the previous unit row.

4. The display substrate according to claim 2, wherein The horizontal connection line includes a first horizontal connection line, the vertical connection line includes a first vertical connection line, the fifth connection electrode in the first vertical connection line is connected to the first initial signal line, and the first initial signal line and the first horizontal connection line form a horizontal double-line structure for transmitting a first initial signal.

5. The display substrate according to claim 4, wherein In at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line, the second connection electrode is connected to a first pole of the data writing transistor, the data connection electrode is connected to the second connection electrode, and the data signal line is connected to the data connection electrode; at least one second circuit unit further includes a first data connection block, and the first data connection block is respectively connected to the second connection electrode and the first initial signal line.

6. The display substrate according to claim 5, wherein At least one second circuit unit further includes a first vertical trace and a second vertical trace, the first vertical trace is connected to the data connection electrode, the second vertical trace is connected to the first vertical trace, the first vertical connection line, the first vertical trace, and the second vertical trace form a vertical triple-line structure for transmitting a first initial signal, and the horizontal double-line structure and the vertical triple-line structure form a plurality of first mesh connection structures.

7. The display substrate according to claim 4, characterized in that In at least one second circuit unit, the third connection electrode is not connected to the first power supply line.

8. The display substrate according to claim 2, wherein The horizontal connection line includes a second horizontal connection line, the vertical connection line includes a second vertical connection line; at least one second circuit unit further includes a fifteenth connection electrode, the fifteenth connection electrode is disposed between the fifth connection electrode and the sixth connection electrode and is respectively connected to the fifth connection electrode and the sixth connection electrode; the second initial signal line and the second horizontal connection line form a horizontal double-line structure for transmitting a second initial signal.

9. The display substrate according to claim 8, wherein In at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, a second data connection block, and a data signal line. The second connection electrode is connected to a first pole of the data writing transistor. The data connection electrode is connected to the second connection electrode. The data signal line is connected to the data connection electrode. The second data connection block is connected to the sixth connection electrode. In at least one second circuit unit, it further includes a third data connection block. The third data connection block is respectively connected to the second data connection block and the data connection electrode.

10. The display substrate according to claim 9, wherein In at least one second circuit unit, it further includes a first vertical trace and a second vertical trace. The first vertical trace is connected to the data connection electrode. The second vertical trace is connected to the first vertical trace. The second vertical connection line, the first vertical trace, and the second vertical trace form a vertical three-line structure for transmitting a second initial signal. The horizontal two-line structure and the vertical three-line structure form a plurality of second mesh connection structures.

11. The display substrate according to claim 8, wherein In at least one second circuit unit, the third connection electrode is not connected to the first power supply line, and the fifth connection electrode is not connected to the first initial signal line.

12. The display substrate according to claim 2, wherein The horizontal connection line includes a third horizontal connection line. The vertical connection line includes a third vertical connection line. The third connection electrode in the third vertical connection line is connected to the first power supply line. The horizontal power signal line and the third horizontal connection line form a horizontal two-line structure for transmitting a first power signal.

13. The display substrate according to claim 12, wherein In at least one first circuit unit, the pixel driving circuit further includes a data writing transistor, a second connection electrode, a data connection electrode, and a data signal line. The second connection electrode is connected to a first pole of the data writing transistor. The data connection electrode is connected to the second connection electrode. The data signal line is connected to the data connection electrode. In at least one second circuit unit, it further includes a power connection block. The power connection block is respectively connected to the data connection electrode and the first power supply line.

14. The display substrate according to claim 13, wherein In at least one second circuit unit, it further includes a first vertical trace and a second vertical trace. The first vertical trace is connected to the data connection electrode. The second vertical trace is connected to the first vertical trace. The first power supply line, the third vertical connection line, the first vertical trace, and the second vertical trace form a vertical four-line structure for transmitting a first power signal. The horizontal two-line structure and the vertical four-line structure form a plurality of third mesh connection structures.

15. The display substrate according to claim 12, wherein In at least one second circuit unit, the fifth connection electrode is not connected to the first initial signal line.

16. The display substrate according to any one of claims 1 to 15, characterized in that, The horizontal connection line includes a first horizontal connection line, a second horizontal connection line, and / or a third horizontal connection line. The vertical connection line includes a first vertical connection line, a second vertical connection line, and / or a third vertical connection line. The mesh connection structure includes a first mesh connection structure, a second mesh connection structure, and / or a third mesh connection structure.

17. A display device, characterized in that, Comprising the display substrate according to any one of claims 1 to 16.

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