Power failure protection circuit and terminal equipment

Abstract

The utility model discloses a power-down protection circuit and terminal equipment, and relates to the technical field of protection circuits, in the power-down protection circuit, a first DCDC power supply is used for supplying power to a power-down detection chip, a storage unit and a central processing unit CPU; the power failure detection chip is used for detecting a direct current input voltage; the DC input voltage is used for supplying power to the first DCDC power supply and the second DCDC power supply; the control output end of the power failure detection chip is respectively connected to the CPU and the second DCDC power supply; when the DC input voltage is smaller than a first preset value, the control output end of the power failure detection chip outputs a first level so as to turn off the second DCDC power supply. The circuit can reduce the power failure speed of the whole equipment, so that the influence of sudden power failure on the CPU and the storage unit is reduced as much as possible, and the equipment safety risk caused by power failure is reduced.

Description

Technical Field

[0001] This application relates to the technical field of protection circuits, and specifically relates to a power-off protection circuit and a terminal device. Background Art

[0002] When electronic devices such as servers experience abnormal power-off, it may cause the storage units (such as abnormal EMMC and SSD) that store program data inside the device, resulting in the device being unable to boot and work properly when powered on again.

[0003] In the prior art, in order to avoid the above problems as much as possible, a UPS power supply can be used as a backup power supply. When abnormal power-off occurs, the UPS automatically switches to the normal power supply to keep the device powered on; or a battery can be installed on the motherboard to keep the device powered on; however, the above solutions are all costly, and when the UPS power supply or the battery also malfunctions, it cannot ensure that the EMMC and SSD of the device are not abnormal, resulting in a relatively high safety risk for electronic devices in the abnormal power-off state. Utility Model Content

[0004] This application provides a power-off protection circuit and a terminal device, which can reduce the safety risk of the device caused by power-off.

[0005] On the one hand, a power-off protection circuit is provided for power-off protection of a data storage system. The data storage system includes a central processing unit CPU, a storage unit, and peripheral devices. The power-off protection circuit includes a first DCDC power supply, a second DCDC power supply, and a power-off detection chip; the first DCDC power supply is used to supply power to the power-off detection chip, the storage unit, and the central processing unit CPU;

[0006] The power-off detection chip is used to detect the DC input voltage; the DC input voltage is used to supply power to the first DCDC power supply and the second DCDC power supply; the control output terminal of the power-off detection chip is respectively connected to the central processing unit CPU and the second DCDC power supply;

[0007] When the input voltage is less than a first preset value, the control output terminal of the power-off detection chip outputs a first level to turn off the second DCDC power supply.

[0008] In a possible implementation, when the input voltage is greater than or equal to the first preset value, the control output terminal of the power-off detection chip outputs a second level to start the second DCDC power supply and make the central processing unit CPU operate normally.

[0009] In a possible implementation, the power-down protection circuit further includes an ACDC power supply; an AC input terminal of the ACDC power supply is connected to an AC voltage; a DC output terminal of the ACDC power supply is grounded through a first capacitor;

[0010] The DC output terminal of the ACDC power supply is respectively connected to a power supply input terminal of a first DCDC power supply and a power supply input terminal of a second DCDC power supply;

[0011] The DC output terminal of the ACDC power supply is further connected to a detection input terminal of the power-down detection chip through a first resistor; the DC output terminal of the ACDC power supply is further grounded through a second resistor.

[0012] In a possible implementation, the detection input terminal of the power-down detection chip is further grounded through a second capacitor.

[0013] In a possible implementation, the power-down detection chip includes a delay pin, and the delay pin is grounded through a third capacitor;

[0014] When the input voltage is greater than or equal to a first preset value, and when the voltage value on the third capacitor is greater than the second preset value, a control output terminal of the power-down detection chip outputs a second level to start the second DCDC power supply.

[0015] In a possible implementation, the storage unit includes a flash memory unit and a data storage unit; the flash memory unit is Flash; the data storage unit is EMMC / SSD.

[0016] In a possible implementation, the central processing unit CPU is electrically connected to the data storage unit;

[0017] When the DC input voltage is less than the first preset value, a control output terminal of the power-down detection chip outputs a first level to interrupt the central processing unit; and when the central processing unit is interrupted, the position of the current reading and writing of the data storage unit is stored.

[0018] In another aspect, the present application further provides a terminal device, the terminal device includes a data storage system and the above-mentioned power-down protection circuit, and the data storage system includes a central processing unit CPU, a storage unit and a peripheral device.

[0019] The technical solution provided by the present application may include the following beneficial effects:

[0020] The present application provides a power-down protection circuit, which includes a first DCDC power supply and a second DCDC power supply. The first DCDC power supply supplies power to a power-down detection chip, a storage unit, and a central processing unit (CPU). The second DCDC power supply is used to supply power to a peripheral circuit. The control output terminal of the power-down detection chip is respectively connected to the CPU and the second DCDC power supply. At this time, when the DC input voltage is less than a first preset value, it indicates that the power-down detection chip detects a power-down situation of the DC input voltage. The storage unit in the device is likely to be abnormal due to power-down. In this application, the control output terminal of the power-down detection chip outputs a first level, thereby turning off the second DCDC power supply, reducing the overall power-down speed of the device, and thus minimizing the impact of sudden power-off on the CPU and the storage unit to reduce the device safety risk caused by power-down. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 is a schematic structural diagram of a power-down protection circuit shown according to an exemplary embodiment.

[0023] Figure 2 shows a partial circuit structure diagram of a terminal device related to an embodiment of the present application.

[0024] Figure 3 shows a specific circuit structure diagram of a power-down protection circuit related to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following will clearly and completely describe the technical solutions of the present application in conjunction with the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0026] In the description of the embodiments of the present application, the term "corresponding" can represent a direct or indirect corresponding relationship between two, can also represent an associated relationship between two, or can be a relationship such as indication and being indicated, configuration and being configured, etc.

[0027] Figure 1 is a schematic structural diagram of a power-down protection circuit shown according to an exemplary embodiment. AsFigure 1 As shown, it is used for power-off protection of a data storage system. The data storage system includes a central processing unit (CPU), a storage unit, and peripheral devices. The power-off protection circuit includes a first DC-DC power supply, a second DC-DC power supply, and a power-off detection chip. The first DC-DC power supply is used to supply power to the power-off detection chip, the storage unit, and the central processing unit (CPU).

[0028] The power-off detection chip is used to detect the DC input voltage. The DC input voltage is used to supply power to the first DC-DC power supply and the second DC-DC power supply. The control output terminal of the power-off detection chip is respectively connected to the central processing unit (CPU) and the second DC-DC power supply.

[0029] When the input voltage is less than the first preset value, the control output terminal of the power-off detection chip outputs a first level to turn off the second DC-DC power supply.

[0030] For example, the first preset value can be 80% of the normal input voltage (such as 12V). When the device loses power abnormally, when the power-off detection chip detects that the input voltage drops to 80%, it can output a first level through the control output terminal, thereby notifying the CPU that the input power supply has lost power abnormally. At the same time, the first level can also be output to the EN enable terminal of the peripheral power supply (that is, the second DC-DC power supply) chip to stop the second DC-DC power supply from supplying power to other peripheral circuits, thereby controlling the shutdown of other peripheral power supplies on the board except for the minimum system, ensuring that the system is at the lowest power consumption at the moment of power-off. That is, at this time, only the first DC-DC power supply supplies power to the power-off detection chip, the storage unit, and the central processing unit (CPU). Therefore, the storage unit and the central processing unit (CPU) have a longer power-off response time, and the central processing unit (CPU) and the storage unit have more sufficient time to save data, reducing the harm caused by sudden power-off to the data storage system; especially by extending the power-off time of the first DC-DC power supply, the data read / write time of the storage unit for data read / write processing is extended.

[0031] In a possible implementation, when the DC input voltage is greater than or equal to the first preset value, the control output terminal of the power-off detection chip outputs a second level to start the second DC-DC power supply and enable the central processing unit (CPU) to operate normally.

[0032] When the device is normally powered, the 12V power supply can be divided by a resistor and applied to the power-off detection chip. The power-off detection chip can judge whether the voltage value of the DC input voltage is normal by the magnitude of the received voltage value. If it is normal (such as greater than 80% of 12V), the control output terminal outputs a high level to control the normal power supply of the peripheral power supply and at the same time prompt the CPU that the device can work normally at this time.

[0033] Furthermore, an embodiment of the present application further provides a terminal device, which includes a data storage system and the above-mentioned power-off protection circuit. The data storage system includes a central processing unit (CPU), a storage unit, and peripheral devices. Please refer to Figure 2 , which shows a partial circuit structure diagram of the terminal device involved in the embodiment of the present application. As Figure 2 shown, in the partial circuit of the terminal device, the circuit part mainly involves the power-off protection circuit protecting the data storage system.

[0034] As Figure 2 shown, in a possible implementation, the power-off protection circuit further includes an ACDC power supply; the AC input terminal of the ACDC power supply is connected to an AC voltage; the DC output terminal of the ACDC power supply is grounded through a first capacitor C1;

[0035] the DC output terminal of the ACDC power supply is respectively connected to the power supply input terminals of a first DCDC power supply and a second DCDC power supply;

[0036] the DC output terminal of the ACDC power supply is further connected to the detection input terminal of the power-off detection chip through a first resistor R1; the DC output terminal of the ACDC power supply is further grounded through a second resistor R2.

[0037] Specifically, in the embodiment of the present application, the device where the power-off protection circuit is located is powered by 220V AC, which is converted to 12V by a power supply module (i.e., the ACDC power supply) to supply power to the main board. The main board's 12V input is designed with a normal input filter capacitor C1 for the DCDC. The power on the main board is divided into two parts of DCDC: the first DCDC power supply for the minimum system power of the main control CPU, flash, EMMC, and power-off detection; the second DCDC power supply for supplying power to other peripheral circuits (such as: PCIE devices, USB devices, network port devices, etc.).

[0038] Optionally, the storage unit includes a flash memory unit and a data storage unit; the flash memory unit is Flash; the data storage unit is EMMC / SSD.

[0039] At this time, as Figure 2 shown, the main control CPU is designed with two parts of storage: nor flash is used to store bios or boot files, and this data will not be modified; EMMC or SSD is used to store the operating system and business software, etc. EMMC or SSD is divided into a backup area to back up the data files that may be read, written, and modified.

[0040] In an embodiment of the present application, the power-down protection circuit is used to protect the data storage unit in the storage unit, that is, the EMMC or SSD that will be affected by power-down.

[0041] In a possible implementation, the central processing unit (CPU) is electrically connected to the data storage unit; when the central processing unit is interrupted, the central processing unit stores the position where the data storage unit is currently being read and written.

[0042] That is, after the CPU receives an interrupt signal, it can pause the current operation and record the position where the EMMC / SSD is currently being read and written in a specific area. The time required to record only the position is very short. When the device loses power abnormally, when the power-down detection chip detects that the input voltage drops to 80%, the power-down detection chip outputs a first level to the EN enable terminal of the second DCDC power supply, stopping the second DCDC power supply from supplying power to other peripheral circuits, extending the power-down time of the first DCDC power supply, enabling the central processing unit (CPU) to have a longer power-down response time, and allowing the central processing unit (CPU) to have enough time to record the position where the EMMC / SSD is currently being read and written in a specific area, so that the recording is consistent with the reading and writing of the storage unit, and the position where the EMMC / SSD is read and written is completely recorded.

[0043] When the device is powered on again next time, the CPU first boots from the flash. After the boot or BIOS boot is completed, it first reads the last power-down information stored on the EMMC / SSD to determine whether key area data was being read and written during the previous power-on. If so, it reads the data of the corresponding block from the backup area for replacement and repair, and then boots into the system; if not, it boots the system normally.

[0044] In a possible implementation, the detection input terminal of the power-down detection chip is also grounded through a second capacitor C2.

[0045] In a possible implementation, the power-down detection chip includes a delay pin CT, and the delay pin CT is grounded through a third capacitor C3;

[0046] When the input voltage is greater than or equal to a first preset value, and when the voltage value on the third capacitor is greater than a second preset value, the control output terminal of the power-down detection chip outputs a second level to start the second DCDC power supply.

[0047] Optionally, in an embodiment of the present application, the model of the power-down detection chip can be ET3895.

[0048] Please refer to Figure 3 , which shows a schematic diagram of the peripheral circuit of the power-down detection chip involved in an embodiment of the present application. Combining Figure 2 and Figure 3, the power-down detection chip can also be designed with a second capacitor C2 at the detection input terminal to filter out the high-frequency spike interference of the 12V power supply. At the same time, ET3895 (power-down detection chip) is also designed with a third capacitor C3 for start-up delay to wait for the 12V power supply to stabilize before turning on the subsequent power supply, making the device more reliable when powered on.

[0049] In summary, the present application provides a power-down protection circuit, which includes a first DCDC power supply and a second DCDC power supply; the first DCDC power supply supplies power to the power-down detection chip, the storage unit, and the central processing unit CPU; the second DCDC power supply is used to supply power to the peripheral circuit, and the control output terminal of the power-down detection chip is respectively connected to the central processing unit CPU and the second DCDC power supply. At this time, when the DC input voltage is less than the first preset value, it means that the power-down detection chip detects a power-down situation of the DC input voltage. The storage unit in the device is likely to be abnormal due to power-down. In this application, the control output terminal of the power-down detection chip outputs a first level, thereby turning off the second DCDC power supply, reducing the overall power-down speed of the device, and thus minimizing the impact of sudden power-off on the CPU and the storage unit to reduce the device safety risk caused by power-down.

[0050] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and the practice of the utility model disclosed herein. The present application aims to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the well-known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0051] It should be understood that the present application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A power-off protection circuit for protecting a data storage system from power failure, wherein the data storage system includes a central processing unit (CPU), a storage unit, and peripheral devices, characterized in that: The power-off protection circuit includes a first DCDC power supply, a second DCDC power supply and a power-off detection chip; the first DCDC power supply is used to supply power to the power-off detection chip, the storage unit and the central processing unit CPU; The power failure detection chip is used to detect the DC input voltage; the DC input voltage is used to power the first DCDC power supply and the second DCDC power supply; the control output end of the power failure detection chip is connected to the central processing unit CPU and the second DCDC power supply respectively; When the DC input voltage is less than a first preset value, the control output terminal of the power-off detection chip outputs a first level to turn off the second DCDC power supply.

2. The circuit according to claim 1, wherein: When the DC input voltage is greater than or equal to the first preset value, the control output terminal of the power failure detection chip outputs a second level, so that the second DCDC power supply is started and the central processing unit CPU operates normally.

3. The circuit according to claim 2, characterized in that The power-off protection circuit further includes an ACDC power supply; an AC input terminal of the ACDC power supply is connected to an AC voltage; a DC output terminal of the ACDC power supply is grounded via a first capacitor; The DC output end of the ACDC power supply is connected to the power supply input end of the first DCDC power supply and the power supply input end of the second DCDC power supply respectively; The DC output end of the ACDC power supply is further connected to the detection input end of the power-off detection chip through a first resistor; and the DC output end of the ACDC power supply is further grounded through a second resistor.

4. The circuit according to claim 3, characterized in that The detection input terminal of the power-off detection chip is also grounded through a second capacitor.

5. The circuit according to claim 4, characterized in that The power-off detection chip includes a delay pin, and the delay pin is grounded via a third capacitor; When the input voltage is greater than or equal to a first preset value, and when the voltage on the third capacitor is greater than a second preset value, the control output terminal of the power failure detection chip outputs a second level to start the second DCDC power supply.

6. The circuit according to any one of claims 1 to 5, characterized in that: The storage unit includes a flash memory unit and a data storage unit; the flash memory unit is Flash; and the data storage unit is EMMC / SSD.

7. The circuit according to claim 6, characterized in that The central processing unit CPU is electrically connected to the data storage unit; When the DC input voltage is less than a first preset value, the control output terminal of the power failure detection chip outputs a first level to interrupt the central processing unit; and the central processing unit stores the current reading and writing position of the data storage unit when the central processing unit is interrupted.

8. A terminal device, characterized in that: The terminal device includes a data storage system and a power-off protection circuit according to any one of claims 1 to 7, wherein the data storage system includes a central processing unit (CPU), a storage unit, and peripheral devices.

Images