Overcurrent protection circuit
By combining the comparison circuit and the self-locking circuit, the accurate protection of the power management chip in the case of overcurrent or short circuit is achieved, the problem of untimely protection in the prior art is solved, and the safety and reliability of the power management chip is improved.
Patent Information
- Application Number
- CN202422342795.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2034-09-25
AI Technical Summary
The overcurrent protection mechanism of the existing power management chip is based on the protection of the primary side of the transformer. The leakage inductance causes untimely protection and low safety.
By comparing the output reference voltage of the power management chip and the power supply voltage, the self-locking circuit is used to lock the low level after the target node voltage is pulled down, and the target device is controlled to make the compensation end low, and the power management chip is stopped.
It improves the accuracy and safety of overcurrent protection, ensures that the power management chip stops working in a timely manner when overcurrent or short circuit, and improves the safety and reliability of the power management chip.
Smart Images
Figure CN223194392U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power supply circuits, and in particular to an overcurrent protection circuit. Background Art
[0002] Power Management Integrated Circuits (PMICs) are chips responsible for converting, distributing, detecting, and other energy management functions within electronic equipment systems. They are primarily responsible for identifying the CPU power supply amplitude, generating corresponding short-term waveforms, and driving power output in subsequent circuits.
[0003] The power management chip is generally equipped with an overpower (output overcurrent) protection mechanism. Usually, the overcurrent protection mechanism in the power management chip is based on the protection of the primary side of the transformer, that is, the primary current is detected by a precision current detection resistor to control the output power. However, the transformer has leakage inductance. Therefore, when the primary current is detected by a precision current detection resistor, if the output overcurrent or the output end is short-circuited, the protection may not be timely, which will affect the energy-consuming equipment and have low safety. Utility Model Content
[0004] The present application provides an overcurrent protection circuit to improve the safety of a power management chip.
[0005] The overcurrent protection circuit includes a comparison circuit, a self-locking circuit and a power management chip;
[0006] The comparison circuit includes a comparator; the comparator is used to compare the reference voltage output by the output reference source of the power management chip with the power supply voltage of the power management chip, and when the reference voltage is less than a specified ratio of the power supply voltage, the comparator outputs a low level;
[0007] The output end of the comparator is connected to the target node of the self-locking circuit; the self-locking circuit is used to lock the voltage of the target node at a low level after the voltage of the target node is pulled down;
[0008] The target node is connected to the first end of the target device; the compensation end of the power management chip is connected to the second end of the target device; the target device is used to make the second end of the target device at a low level when the first end is at a low level; when the compensation end of the power management chip is at a low level, the power management chip stops working.
[0009] In one possible implementation, the output reference source of the power management chip is connected to the non-inverting input terminal of the comparator through a first resistor; the non-inverting input terminal is further grounded through a second resistor; the power supply voltage of the power management chip is connected to the inverting input terminal of the comparator through a third resistor; the inverting input terminal is further grounded through a fourth resistor;
[0010] The non-inverting input terminal of the comparator is also grounded through a first capacitor; the inverting input terminal of the comparator is also grounded through a second capacitor.
[0011] In a possible implementation, the positive power supply terminal of the comparator is connected to the output reference source of the power management chip; and the negative power supply terminal of the comparator is grounded.
[0012] In one possible implementation, in the self-locking circuit, the target node is connected to the base of a first transistor via a sixth resistor; the output reference source of the power management chip is further connected to the emitter of the first transistor via a fifth resistor; the emitter of the first transistor is further grounded via a third capacitor; and the collector of the first transistor is connected to the base of the second transistor via a seventh resistor.
[0013] The base of the second transistor is further connected to the emitter of the second transistor through an eighth resistor and is grounded; the target node is also connected to the collector of the second transistor.
[0014] In a possible implementation, the first transistor is a PNP transistor; the second transistor is an NPN transistor;
[0015] The target node is connected to the base of the target transistor; the compensation terminal of the power management chip is connected to the emitter of the target transistor; and the collector of the target transistor is grounded.
[0016] In a possible implementation, the power management chip further includes a voltage feedback pin;
[0017] The voltage feedback pin is further connected to the emitter of the target transistor through a tenth resistor; the voltage feedback pin is further connected to the emitter of the target transistor through a fifth capacitor;
[0018] The base of the target transistor is also grounded via a fourth capacitor.
[0019] In a possible implementation, the output reference source of the power management chip is further connected to the base of the target transistor via a ninth resistor.
[0020] In a possible implementation, the circuit further includes a rectifier bridge, an energy storage capacitor, a high-voltage startup circuit, a high-frequency transformer, an output capacitor, a first diode, a second diode, and an isolation optocoupler;
[0021] The AC voltage end in the circuit is connected to the two poles of the energy storage capacitor through the rectifier bridge;
[0022] The positive electrode of the energy storage capacitor is connected to the first end of the first winding of the high-frequency transformer; the second end of the first winding is connected to the drain of the power switch tube; the source of the power switch tube is grounded; and the gate of the power switch tube is connected to the output end of the power management chip;
[0023] The positive electrode of the energy storage capacitor is also connected to the power supply end of the power management chip through a high-voltage startup circuit;
[0024] A first end of the second winding of the high-frequency transformer is connected to the power supply end of the power management chip through the first diode; a second end of the second winding is grounded;
[0025] The first end of the third winding of the high-frequency transformer is connected to the voltage output end through the second diode; the voltage output end is grounded through the output capacitor; the second end of the third winding is grounded; and the voltage output end is also connected to the feedback end of the power management chip through the isolation optocoupler.
[0026] The technical solution provided by this application may have the following beneficial effects:
[0027] In an embodiment of the present application, a comparator is used to compare a reference voltage output by an output reference source of a power management chip with the power supply voltage of the power management chip. When the power supply voltage of the power management chip is greater than a preset value, the output of the comparator changes from a high level to a low level, thereby changing the target node of the self-locking circuit from a high level to a low level. Due to the characteristics of the self-locking circuit, when the voltage of the target node is pulled low, the voltage of the target node is locked at a low level, thereby pulling the compensation pin Comp low through the target device, thereby stopping the chip from operating. Furthermore, the reference voltage used in the above scheme is provided by the output reference source of the power management chip, and its voltage is relatively accurate. Therefore, the accuracy of the overcurrent protection function is high, thereby improving the safety of the power management chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0029] Figure 1 The figure is a schematic structural diagram of an overcurrent protection circuit according to an exemplary embodiment.
[0030] Figure 2 is a circuit structure diagram of an overcurrent protection circuit according to an exemplary embodiment.
[0031] Figure 3 This is a circuit diagram of a flyback constant voltage converter based on a power management chip. DETAILED DESCRIPTION
[0032] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0033] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.
[0034] Figure 1 FIG. 1 is a schematic diagram showing the structure of an overcurrent protection circuit according to an exemplary embodiment. Figure 1 As shown, the overcurrent protection circuit includes a comparison circuit, a self-locking circuit and a power management chip;
[0035] The comparison circuit includes a comparator; the comparator is used to compare the reference voltage output by the output reference source of the power management chip with the power supply voltage of the power management chip, and when the reference voltage is less than the power supply voltage of the specified ratio, the comparator outputs a low level;
[0036] The output end of the comparator is connected to the target node of the self-locking circuit; the self-locking circuit is used to lock the voltage of the target node at a low level after the voltage of the target node is pulled down;
[0037] The target node is connected to the first end of the target device; the compensation end of the power management chip is connected to the second end of the target device; the target device is used to make the second end of the target device at a low level when the first end is at a low level; when the compensation end of the power management chip is at a low level, the power management chip stops working.
[0038] like Figure 1 The comparator shown is used to compare the reference voltage output by the output reference source of the power management chip with the power supply voltage of the power management chip. When the power supply voltage of the power management chip is greater than the preset value, the output of the comparator changes from a high level to a low level, so the target node of the self-locking circuit also changes from a high level to a low level; and due to the characteristics of the self-locking circuit, when the voltage of the target node is pulled down, the voltage of the target node will be locked in a low level state, thereby causing the compensation pin Comp to be pulled down through the target device, thereby stopping the chip from working.
[0039] For details, please refer to Figure 2, which shows a circuit structure diagram of an overcurrent protection circuit involved in an embodiment of the present application. Figure 2 As shown, in the comparison circuit, the output reference source of the power management chip is connected to the non-inverting input terminal of the comparator through the first resistor R1; the non-inverting input terminal is also grounded through the second resistor R2; the power supply voltage of the power management chip is connected to the inverting input terminal of the comparator through the third resistor R3; the inverting input terminal is also grounded through the fourth resistor R4.
[0040] In this embodiment, the output reference source of the power management chip is used as the reference voltage of the comparator, which ensures the accuracy of the comparison voltage, improves the accuracy of the overcurrent protection function, and further improves the safety of the power management chip.
[0041] Optionally, in an embodiment of the present application, the comparator can be LM393, and the positive power supply terminal of the comparator is connected to the output reference source of the power management chip; the negative power supply terminal of the comparator is grounded, that is, in the overcurrent protection circuit shown in the embodiment of the present application, the output reference source of the power management chip supplies power to the comparator.
[0042] Optionally, in an embodiment of the present application, the power management chip may be a SA2845SATR chip, and the output reference source of the power management chip is used to output a 5V reference voltage Vref through a Ref pin of the power management chip.
[0043] Optionally, in the embodiment of the present application, there is no limitation on the specific structure of the self-locking circuit, as long as it can achieve locking the low level state of the node when the target node connected to the comparator becomes a low level.
[0044] Optionally, the target device in the embodiment of the present application is a device that is first turned on and then closed when powered on. It can be based on the connection relationship with the target node of the self-locking circuit and the compensation end of the power management chip, so that when the voltage of the target node is locked at a low level, the compensation end of the power management chip is at a low level.
[0045] like Figure 2 The output terminal of the comparator is connected to the target node of the self-locking circuit; the self-locking circuit is used to lock the voltage of the target node at a low level after the voltage of the target node is pulled low;
[0046] In a preferred embodiment, Figure 1 The target device shown can be implemented as Figure 2, the target transistor Q3 is shown in the figure. At this time, the target node is connected to the base of the target transistor Q3, the compensation terminal of the power management chip is connected to the emitter of the target transistor, and the collector of the target transistor is grounded; when the target transistor Q3 is turned on, the compensation terminal Comp of the power management chip is grounded through the target transistor Q3, so that the compensation terminal Comp of the power management chip is at a low level; when the compensation terminal Comp of the power management chip is at a low level, the power management chip stops working.
[0047] Optionally, the target transistor is a PNP transistor.
[0048] In an embodiment of the present application, when the voltage divider value at the power supply terminal of the power management chip exceeds a preset value, the comparator output changes from a high level to a low level, causing the target node of the self-locking circuit to also change from a high level to a low level. Due to the characteristics of the self-locking circuit, once the voltage at the target node is lowered, the voltage at the target node remains locked at a low level, thereby continuously lowering the base level of the target transistor, turning the target transistor on and pulling the compensation pin Comp low, causing the chip to stop operating. Furthermore, the reference voltage used in the above scheme is provided by the output reference source of the power management chip, resulting in a more accurate voltage, thereby improving the accuracy of the overcurrent protection circuit.
[0049] And in Figure 2 In the overcurrent protection circuit shown, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be adaptively adjusted according to actual needs to adjust the critical value of the power supply terminal voltage of the power management chip at which the output terminal of the comparator becomes a low level. Figure 2 The overcurrent protection circuit shown can also be applied to other types of power management chips in addition to the chip exemplarily shown in the embodiment of the present application.
[0050] Further, such as Figure 2 As shown, in the self-locking circuit, the target node is connected to the base of the first transistor Q1 through the sixth resistor R6; the output reference source of the power management chip is further connected to the emitter of the first transistor Q1 through the fifth resistor R5; the emitter of the first transistor Q1 is further grounded through the third capacitor C3; the collector of the first transistor Q1 is connected to the base of the second transistor Q1 through the seventh resistor R7;
[0051] The base of the second transistor Q2 is further connected to the emitter of the second transistor Q2 via an eighth resistor R8 and is grounded; the target node is also connected to the collector of the second transistor Q2.
[0052] Further, such as Figure 2As shown, the comparator's non-inverting input is also grounded via a first capacitor C1; the comparator's inverting input is also grounded via a second capacitor C2; and the emitter of the first transistor is also grounded via a third capacitor C3. The first and second capacitors C1 and C2 are filter capacitors used to filter out noise. In one embodiment, the capacitance of the third capacitor C3 is greater than that of the fourth capacitor C4 to ensure that Q1 does not conduct during startup.
[0053] The first transistor Q1 is a PNP transistor; the second transistor Q2 is an NPN transistor.
[0054] That is, the self-locking circuit consists of a first transistor Q1, a second transistor Q2, and various resistors. When the collector of the second transistor Q2 is pulled low, the first transistor Q1 is turned on. This conduction of the first transistor Q1 increases the base current of the second transistor Q2, turning on the second transistor Q2. The mutual conduction between the first transistor Q1 and the second transistor Q2 causes the collector of the second transistor Q2 to be locked at a low level, that is, the target node is locked at a low level.
[0055] The self-locking circuit formed by the first and second transistors Q1 and Q2 locks the collector of the second transistor Q2 to a low level. This saturates the target transistor Q3, pulling down the first pin of the chip and shutting down the chip, thus achieving OCP (output overcurrent protection). Once OCP is activated, due to the self-locking circuit, when the power supply voltage exceeds the reference voltage and the output overcurrent occurs, the compensation terminal of the power management chip is low, and the chip is completely shut down. This circuit provides strong anti-interference capabilities.
[0056] Furthermore, the power management chip also includes a voltage feedback pin VFb;
[0057] The voltage feedback pin VFb is further connected to the emitter of the target transistor Q3 via a tenth resistor R10; the voltage feedback pin is further connected to the emitter of the target transistor Q3 via a fifth capacitor C5;
[0058] The base of the target transistor Q3 is also grounded via a fourth capacitor C4.
[0059] The ninth resistor R9, the fourth capacitor C4, and the target transistor Q3 implement the soft start function of the SA2845SATR chip. When the chip is powered on and started, the reference voltage Vref charges the fourth capacitor C4 through the ninth resistor R9. At the beginning, the base of the target transistor Q3 is at a low level, and the target transistor Q3 is saturated and turned on, that is, the compensation pin Comp is pulled low. The compensation pin Comp is the output end of the error amplifier inside the chip.
[0060] Figure 3 This is a circuit diagram of a flyback constant voltage converter based on a power management chip.
[0061] Specifically, such as Figure 3 As shown, it includes a rectifier bridge, an energy storage capacitor, a high-voltage starting circuit, a high-frequency transformer, an output capacitor, a power switch tube, a first diode D1, a second diode D2, an isolation optocoupler and a power management chip;
[0062] The AC voltage end in the circuit is connected to the two poles of the energy storage capacitor through a rectifier bridge;
[0063] The positive electrode of the energy storage capacitor is connected to the first end of the first winding of the high-frequency transformer; the second end of the first winding is connected to the drain of the power switch tube; the source of the power switch tube is grounded; and the gate of the power switch tube is connected to the output end of the power management chip;
[0064] The positive electrode of the energy storage capacitor is also connected to the power supply terminal of the power management chip through a high-voltage startup circuit;
[0065] A first end of the second winding of the high-frequency transformer is connected to the power supply end of the power management chip through a first diode; a second end of the second winding is grounded;
[0066] The first end of the third winding of the high-frequency transformer is connected to the voltage output end through the second diode; the voltage output end is grounded through the output capacitor; the second end of the third winding is grounded; the voltage output end is also connected to the feedback end of the power management chip through the isolation optocoupler.
[0067] In such Figure 3 In the circuit shown, AC220V mains power is converted into 311V DC power through a rectifier bridge and energy storage capacitors. The SA2845SATR chip (i.e., the power management chip) is then started through a high-voltage startup circuit. After the chip is started, the high-frequency transformer Aux winding supplies power to the chip VCC through the rectifier tube D1.
[0068] At this time, you can Figure 2 Overcurrent protection circuit access Figure 3 The circuit in, specifically, Figure 3 The Aux winding voltage of the transformer shown in the figure is connected to the VCC pin of the power management chip. At this time, the VCC pin can be connected to the VCC pin through Figure 2 The third resistor is connected to the inverting input of the comparator. Since VCC is open-loop controlled, the output overcurrent protection point is designed using the mapping relationship between VCC and output current. The first capacitor C1 and the second capacitor C2 are filter capacitors.
[0069] When the output is overcurrent (short circuit), the duty cycle of the SA2845SATR drive signal increases, which causes VCC to rise. VCC is higher than the reference source, and the high-speed comparator LM393 output is pulled low. The self-locking circuit locks the base voltage of the target transistor Q3 at a low level.
[0070] Combine Figure 3 After the chip stops working, due to the presence of high-voltage startup capacitors, the energy storage capacitor supplies power to the chip VCC through the high-voltage startup circuit. The SA2845SATR chip will keep trying to start. At this time, the designed circuit will continue to compare whether there is an output overcurrent (or short circuit). If so, the above process will be repeated, that is, the power chip enters the set hiccup mode.
[0071] Specifically, at this time, the compensation pin Comp, the voltage feedback pin VFb, the fifth capacitor C5 and the tenth resistor R10 constitute a compensator. The target transistor Q3 is connected to the Comp pin of the power management chip. When the target transistor Q3 is turned on, the Comp pin level will be pulled low, so that based on the working principle of the chip itself, the duty cycle PWM output of the chip OUT pin becomes extremely low. The output is rectified by the high-frequency transformer and the rectifier tube D1, pulling down VCC, causing the chip to enter the undervoltage lockout mode UVLO, and the chip stops working; at this time, the energy storage capacitor will try to power VCC and try to restart the chip. In this process, Figure 2 The middle circuit synchronously detects whether overcurrent or short circuit occurs. By repeating the above process, the output duty cycle of the chip can be controlled. That is, the target transistor Q3 is saturated and turned on to stop the chip from driving the waveform output.
[0072] In summary, in the embodiments of the present application, a comparator is used to compare the reference voltage output by the output reference source of the power management chip with the power supply voltage of the power management chip. When the power supply voltage of the power management chip is greater than a preset value, the output of the comparator changes from a high level to a low level, and thus the target node of the self-locking circuit also changes from a high level to a low level. Due to the characteristics of the self-locking circuit, when the voltage of the target node is pulled low, the voltage of the target node will remain locked at a low level, thereby pulling the compensation pin Comp low through the target device, causing the chip to stop working. The reference voltage used in the above scheme is provided by the output reference source of the power management chip, and its voltage is relatively accurate. Therefore, the accuracy of the overcurrent protection function is high, thereby improving the safety of the power management chip.
[0073] Moreover, since the target transistor Q3 is connected to the Comp pin of the power management chip, when the target transistor Q3 is turned on, the Comp pin level will be pulled down, so that based on the working principle of the chip itself, the duty cycle PWM output by the chip OUT pin becomes extremely low. The output is rectified through the high-frequency transformer and the rectifier tube D1, pulling down VCC, causing the chip to enter the undervoltage lockout mode UVLO, and the chip stops working. At this time, the energy storage capacitor will try to supply power to VCC and try to restart the chip. In other words, the solution shown in the embodiment of the present application can also adjust the chip duty cycle output during overcurrent protection, and continuously try to restart while ensuring the safety of the chip, thereby improving the reliability of the power management chip.
[0074] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0075] It will be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.
Claims
1. An overcurrent protection circuit, characterized in that: The overcurrent protection circuit includes a comparison circuit, a self-locking circuit and a power management chip; The comparison circuit includes a comparator; the comparator is used to compare the reference voltage output by the output reference source of the power management chip with the power supply voltage of the power management chip, and when the reference voltage is less than a specified ratio of the power supply voltage, the comparator outputs a low level; The output end of the comparator is connected to the target node of the self-locking circuit; the self-locking circuit is used to lock the voltage of the target node at a low level after the voltage of the target node is pulled down; The target node is connected to the first end of the target device; the compensation end of the power management chip is connected to the second end of the target device; the target device is used to make the second end of the target device at a low level when the first end is at a low level; when the compensation end of the power management chip is at a low level, the power management chip stops working.
2. The overcurrent protection circuit according to claim 1, characterized in that: The output reference source of the power management chip is connected to the non-inverting input terminal of the comparator through a first resistor; the non-inverting input terminal is also grounded through a second resistor; the power supply voltage of the power management chip is connected to the inverting input terminal of the comparator through a third resistor; the inverting input terminal is also grounded through a fourth resistor; The non-inverting input terminal of the comparator is also grounded through a first capacitor; and the inverting input terminal of the comparator is also grounded through a second capacitor.
3. The overcurrent protection circuit according to claim 2, wherein: The positive power supply terminal of the comparator is connected to the output reference source of the power management chip; and the negative power supply terminal of the comparator is grounded.
4. The overcurrent protection circuit according to claim 1, wherein: In the self-locking circuit, the target node is connected to the base of the first transistor through a sixth resistor; the output reference source of the power management chip is further connected to the emitter of the first transistor through a fifth resistor; the emitter of the first transistor is further grounded through a third capacitor; and the collector of the first transistor is connected to the base of the second transistor through a seventh resistor. The base of the second transistor is further connected to the emitter of the second transistor through an eighth resistor and is grounded; the target node is also connected to the collector of the second transistor.
5. The overcurrent protection circuit according to claim 4, characterized in that: The first transistor is a PNP transistor; the second transistor is an NPN transistor.
6. The overcurrent protection circuit according to claim 1, wherein: The target device is a target transistor, and the target transistor is a PNP transistor; The target node is connected to the base of the target transistor; the compensation terminal of the power management chip is connected to the emitter of the target transistor; and the collector of the target transistor is grounded.
7. The overcurrent protection circuit according to claim 6, characterized in that: The power management chip also includes a voltage feedback pin; The voltage feedback pin is further connected to the emitter of the target transistor through a tenth resistor; the voltage feedback pin is further connected to the emitter of the target transistor through a fifth capacitor; The base of the target transistor is also grounded via a fourth capacitor.
8. The overcurrent protection circuit according to claim 7, characterized in that: The output reference source of the power management chip is further connected to the base of the target transistor through a ninth resistor.
9. The overcurrent protection circuit according to any one of claims 1 to 8, characterized in that: The circuit also includes a rectifier bridge, an energy storage capacitor, a high-voltage starting circuit, a high-frequency transformer, an output capacitor, a first diode, a second diode and an isolation optocoupler; The AC voltage end in the circuit is connected to the two poles of the energy storage capacitor through the rectifier bridge; The positive electrode of the energy storage capacitor is connected to the first end of the first winding of the high-frequency transformer; the second end of the first winding is connected to the drain of the power switch tube; the source of the power switch tube is grounded; and the gate of the power switch tube is connected to the output end of the power management chip; The positive electrode of the energy storage capacitor is also connected to the power supply end of the power management chip through a high-voltage startup circuit; A first end of the second winding of the high-frequency transformer is connected to the power supply end of the power management chip through the first diode; a second end of the second winding is grounded; The first end of the third winding of the high-frequency transformer is connected to the voltage output end through the second diode; the voltage output end is grounded through the output capacitor; the second end of the third winding is grounded; and the voltage output end is also connected to the feedback end of the power management chip through the isolation optocoupler.