Chip packaging structure
By installing the front of the chip on the frame pad of the lead frame in the power device packaging structure and connecting it with metal strips, the problem of poor heat dissipation is solved, and better heat dissipation effect and chip reliability are achieved, welding short circuit is avoided, and thermal stability is improved.
Patent Information
- Application Number
- CN202422471425.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-10-12
AI Technical Summary
The existing power device packaging structure has poor heat dissipation effect, resulting in insufficient thermal stability and reliability of the chip, and prone to thermal breakdown failure.
Design a chip package structure where the front of the chip is installed on the frame pad of the lead frame near the device junction area, and the back of the chip and the pins are connected through metal strips. The strong heat dissipation ability of the lead frame is used to enhance the heat dissipation effect, and a boss is installed on the surface of the frame pad to avoid the risk of welding short circuit.
It effectively reduces the thermal resistance of the packaging system, reduces the junction temperature of the chip, improves the thermal stability and reliability of the chip, and avoids the risk of short circuit during soldering.
Smart Images
Figure CN223218302U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging, in particular to a chip packaging structure. Background Art
[0002] Power devices are widely used in consumer electronics, photovoltaic green energy, industrial control, automotive electronics, and military applications. Thermal management of these devices has long been a research focus. Power devices such as diodes and transistors are prone to temperature rise due to their high current and high frequency operating environments. If device temperature rise is not adequately controlled, thermal runaway can occur, leading to severe thermal breakdown and failure.
[0003] Figure 1 This is a schematic diagram of an exemplary power device packaging structure. Figure 1 As shown, conventional methods for packaging power devices generally directly and completely adhere the chip backside 100b to the leadframe pad 201. For diodes, the chip backside 100b serves as the cathode, and for transistors, the chip backside 100b serves as the drain. The chip frontside 100a, connected to the lead 202 via a metal strip 300, serves as the anode for diodes or the source or gate for transistors. However, with this power device packaging structure, the thermal resistance of the entire packaging system is not conducive to heat dissipation from the chip 100, resulting in poor heat dissipation for the chip 100, which in turn affects the thermal stability and reliability of the chip 100. Utility Model Content
[0004] One of the purposes of the present invention is to improve the heat dissipation effect of the packaging structure on the chip and to improve the thermal stability and reliability of the chip.
[0005] To achieve the above objectives, the present invention provides a chip packaging structure. The chip packaging structure includes: a chip having a front side and a back side facing each other, a device junction region located between the front side and the back side of the chip, the device junction region being closer to the front side than the device junction region to the back side of the chip; a lead frame including a frame pad and pins located on either side of the frame pad, the chip front side being soldered to the frame pad; and a metal strip electrically connecting the chip back side and the pins.
[0006] Optionally, when the chip is working, the heat on the front side of the chip is greater than the heat on the back side of the chip.
[0007] Optionally, the lead frame includes a plurality of frame pads, the chip is arranged on the plurality of frame pads, the front side of the chip has a plurality of chip pads, and the chip pads are welded to the corresponding frame pads.
[0008] Optionally, the front of the chip has a chip pad, the surface of the frame pad has a boss, the top surface of the boss is close to the chip and the bottom surface is away from the chip, the chip pad is welded on the corresponding top surface of the boss, and the width of the chip pad is greater than the width of the corresponding top surface of the boss.
[0009] Optionally, the width of the top surface of the boss is smaller than the width of the bottom surface of the boss.
[0010] Optionally, solder is provided between the chip pad and the top surface of the boss.
[0011] Optionally, the lead frame is made of copper.
[0012] Optionally, the chip includes a diode, the front side of the chip is the positive electrode of the diode, and the back side of the chip is the negative electrode of the diode.
[0013] Optionally, the chip includes a transistor, the front side of the chip is the source or gate of the transistor, and the back side of the chip is the drain of the transistor.
[0014] Optionally, the chip is a power device.
[0015] The chip packaging structure provided by the present invention includes a chip, a lead frame and a metal strip. The chip has a device junction area located between the front side and the back side of the chip. The distance between the device junction area and the front side of the chip is smaller than the distance between the device junction area and the back side of the chip, that is, the device junction area is close to the front side of the chip. The lead frame includes a frame pad and pins located on the side of the frame pad. The front side of the chip is welded to the frame pad, and the metal strip electrically connects the back side of the chip and the pins. In this way, the front side of the chip with higher heat is mounted on the frame pad of the lead frame. The front side of the chip can make maximum use of the advantage of the strong heat dissipation capacity of the lead frame, that is, make maximum use of the lead frame to dissipate heat for the chip, thereby enhancing the heat dissipation effect of the chip, effectively reducing the thermal resistance of the entire packaging system, reducing the Tj temperature of the chip, and greatly improving the thermal stability and reliability of the chip.
[0016] Furthermore, the chip has a chip pad on the front side, and the frame pad has a boss on the surface. The chip pad is soldered to the corresponding boss on the frame pad, and the width of the chip pad is greater than the top width of the corresponding boss. During soldering of the chip pad and boss, due to the good wettability of the solder with the lead frame and the effect of gravity, the solder will overflow to the side wall of the boss rather than to the side of the chip during the soldering process, thus effectively avoiding the risk of chip short circuit during soldering. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 The figure is a schematic structural diagram of an exemplary power device packaging structure.
[0018] Figure 2 This is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present invention.
[0019] Explanation of reference numerals: 100 - chip; 100a - front side of chip; 100b - back side of chip; 201 - frame pad; 202 - pin; 300 - metal strip; 400 - solder. DETAILED DESCRIPTION
[0020] refer to Figure 1 As shown, during chip operation, heat generated within chip 100 primarily comes from the device junction region and locations near the junction region. The device junction region is typically near the chip front 100a. The chip front 100a is connected to the leadframe pins 202 via a metal strip 300, while the chip back 100b is mounted on the leadframe's frame pads 201. However, the contact area between the metal strip 300 and the chip front 100a, as well as the width of the metal strip 300, are both smaller than the heat dissipation area of the entire frame pad 201 on the chip back 100b. A larger heat dissipation area results in better heat dissipation. Therefore, conventional chip packaging structures do not fully and effectively utilize the leadframe for heat dissipation. The thermal resistance of the entire packaging system is not friendly to chip heat dissipation, resulting in an increase in the chip's Tj temperature (junction temperature), affecting the chip's thermal stability and reliability.
[0021] To address the aforementioned issues, the present invention provides a chip packaging structure in which the front surface of the chip, near the device junction region, is mounted on a lead frame pad. This allows the front surface of the chip to take maximum advantage of the lead frame's strong heat dissipation capabilities. This maximizes the use of the lead frame to dissipate heat from the chip, enhancing the chip's heat dissipation effect, effectively reducing the thermal resistance of the entire packaging system, lowering the chip's Tj temperature (junction temperature), and significantly improving the chip's thermal stability and reliability.
[0022] Furthermore, a boss is provided on the surface of the frame pad, and the chip pad on the front of the chip is welded to the top surface of the corresponding boss, and the width of the chip pad is greater than the width of the top surface of the corresponding boss. In the process of welding the chip pad and the boss, due to the good wettability of the solder with the lead frame and due to the effect of gravity, the solder will overflow to the side wall of the boss instead of overflowing to the side of the chip during the tin climbing process, which can effectively avoid the risk of chip short circuit during welding.
[0023] The chip packaging structure proposed by the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element would now be below that element.
[0024] Figure 2 This is a schematic diagram of the chip packaging structure provided by an embodiment of the present invention. Figure 2 As shown, the chip package structure includes a chip 100 , a lead frame and a metal strip 300 .
[0025] The chip 100 has a front side 100a and a back side 100b facing each other. A device junction region is located between the front side 100a and the back side 100b within the chip 100. The distance between the device junction region and the front side 100a is smaller than the distance between the device junction region and the back side 100b. That is, the device junction region is closer to the front side 100a and farther from the back side 100b. When the chip 100 is operating, heat is primarily generated by the device junction region, resulting in greater heat on the front side 100a than on the back side 100b.
[0026] It should be noted that in this embodiment, chip 100 is a semiconductor chip having a PN junction, a Schottky junction, and / or a heterojunction region within chip 100. The device junction region is the region where the PN junction, Schottky junction, and / or heterojunction region is located. For example, chip 100 may be a power device, but is not limited thereto. Chip 100, or the power device, may be, but is not limited to, a diode or a transistor.
[0027] When the chip 100 includes a diode, the front surface 100a of the chip is the anode of the diode, and the back surface 100b of the chip is the cathode of the diode. When the chip 100 includes a transistor, the front surface 100a of the chip is the source or gate of the transistor, and the back surface 100b of the chip is the drain of the transistor.
[0028] The chip 100 includes a substrate, which may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI), etc. Certain doping particles may be implanted into the substrate according to design requirements to change electrical parameters.
[0029] The chip front side 100a may have at least one chip bonding pad (not shown in the figure), through which the chip front side 100a is electrically connected to an external circuit. The chip bonding pad may be made of materials including but not limited to copper, nickel, stainless steel, or beryllium copper.
[0030] Continue to refer Figure 2 As shown, the lead frame includes a frame pad 201 and pins 202 located on the side of the frame pad 201 , and the chip front side 100 a is soldered on the frame pad 201 .
[0031] The number of the frame pads 201 is based on the chip pad configuration of the chip front side 100a. The number of the pins 202 can be multiple, and the multiple pins 202 are distributed around the frame pad 201 to establish an electrical connection between the chip back side 100b and the pins 202.
[0032] In this embodiment, reference Figure 2 As shown, the chip front side 100 a is mounted on a frame pad 201 .
[0033] In other embodiments of the present application, the lead frame may include a plurality of frame pads 201, the chip 100 is disposed on the plurality of frame pads 201, and the chip front surface 100a has a plurality of chip pads, which are welded to corresponding frame pads 201. By designing a plurality of frame pads 201 on the lead frame corresponding to the positions of the plurality of chip pads, electrical connections can be achieved on the front surfaces of different chip devices.
[0034] In this embodiment, the lead frame is made of copper. Due to copper's advantages in electrical conductivity, heat dissipation, compatibility with plastic packaging, and cost, the lead frame's frame pads 201 effectively dissipate heat from the chip front surface 100a. Exemplary copper grades include, but are not limited to, KFC, C19210, TFe0.1, and EFTEC64T. In other embodiments, the lead frame may be made of other materials with good thermal conductivity.
[0035] refer to Figure 2 As shown, the surface of the frame pad 201 may have a boss 203, the top surface of the boss 203 is close to the chip 100 and the bottom surface is away from the chip 100, the chip pad on the front side 100a of the chip is welded on the top surface of the corresponding boss 203, the width of the chip pad is greater than the top surface width of the corresponding boss 203, wherein the width of the chip pad and the top surface width of the boss 203 are both Figure 2 Horizontal size.
[0036] A boss 203 is provided on the surface of the frame pad 201, and solder 400 is provided between the chip pad and the top surface of the boss 203. The chip pad on the front side 100a of the chip and the corresponding boss 203 are welded via the solder 400. In the process of welding the chip pad and the boss 203, due to the good wettability of the solder 400 with the lead frame (specifically the boss 203) and due to the effect of gravity, the solder 400 will overflow to the side wall of the boss 203 instead of overflowing to the side of the chip 100 during the tin climbing process. The overflowed solder can cover at least part of the side wall of the boss 203, thereby effectively avoiding the risk of chip short circuit during welding.
[0037] In this embodiment, the material of the solder 400 includes tin (Sn) or an alloy mainly containing tin, for example, the alloy mainly containing tin is SnAg, but is not limited thereto.
[0038] In this embodiment, the material of the boss 203 includes but is not limited to copper or graphene. In some embodiments, the material of the boss 203 can be the same as that of the frame pad 201. The boss 203 and the frame pad 201 can be an integrally formed structure.
[0039] To allow the solder 400 to flow better toward the sidewalls of the boss 203 during soldering, in this embodiment, the width of the top surface of the boss 203 is smaller than the width of the bottom surface of the boss 203. The top surface of the boss 203 is close to the chip 100, and the bottom surface of the boss 203 is away from the chip 100. Exemplarily, the cross-section of the boss 203 perpendicular to the chip front surface 100a is trapezoidal, but not limited thereto.
[0040] refer to Figure 2As shown, the chip package structure includes a metal strip 300 , which electrically connects the chip back side 100 b and the pins 202 .
[0041] Specifically, the metal strip 300 is a metal strip, one end of which is welded to the chip back side 100b, and the other end of which is welded to the pin 202. The width of the metal strip 300 is generally greater than that of a bonding wire. Compared to standard wire bonding, using the metal strip 300 to connect the chip back side 100b and the pin 202 can achieve a unique package resistance value, higher current flow, and better thermal conductivity. Furthermore, the soldering point of the pin 202 does not require silver plating, which can significantly reduce the cost of silver plating and poor silver plating.
[0042] In this embodiment, the material of the metal strip 300 includes but is not limited to copper.
[0043] The chip packaging structure provided by the present invention includes a chip 100, a lead frame and a metal strip 300. The chip 100 has a device junction area located between the chip front side 100a and the chip back side 100b. The distance between the device junction area and the chip front side 100a is smaller than the distance between the device junction area and the chip back side 100b, that is, the device junction area is close to the chip front side 100a. The lead frame includes a frame pad 201 and a pin 202 located on the side of the frame pad 201. The chip front side 100a is soldered to the frame. On the pad 201, the metal strip 300 electrically connects the chip back side 100b and the pin 202, so that the chip front side 100a with greater heat is mounted on the frame pad 201 of the lead frame. The chip front side 100a can make maximum use of the advantage of the strong heat dissipation capability of the lead frame, that is, make maximum use of the lead frame to dissipate heat for the chip 100, thereby enhancing the heat dissipation of the chip 100, effectively reducing the thermal resistance of the entire packaging system, reducing the chip Tj temperature, and greatly improving the thermal stability and reliability of the chip 100.
[0044] Furthermore, the chip front side 100a has a chip pad, and the frame pad 201 has a boss 203 on its surface. The top surface of the boss 203 is close to the chip 100 and the bottom surface is away from the chip 100. The chip pad is soldered to the top surface of the corresponding boss of the frame pad 201, and the width of the chip pad is greater than the width of the top surface of the corresponding boss 203. During the soldering process between the chip pad and the boss 203, due to the good wettability of the solder 400 with the lead frame and the effect of gravity, the solder 400 will overflow to the sidewalls of the boss 203 during the soldering process instead of overflowing to the side of the chip, thus effectively avoiding the risk of chip short circuit during soldering.
[0045] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: A chip having a front side and a back side facing each other, a device junction region located between the front side and the back side of the chip, and a distance between the device junction region and the front side of the chip being smaller than a distance between the device junction region and the back side of the chip; A lead frame, the lead frame comprising a frame pad and pins located on the side of the frame pad, the front side of the chip being welded to the frame pad; and A metal strip electrically connects the back side of the chip and the pins.
2. The chip packaging structure according to claim 1, wherein: When the chip is working, the heat on the front side of the chip is greater than the heat on the back side of the chip.
3. The chip packaging structure according to claim 1, wherein: The lead frame includes a plurality of frame pads, the chip is arranged on the plurality of frame pads, the front surface of the chip has a plurality of chip pads, and the chip pads are welded to the corresponding frame pads.
4. The chip packaging structure according to claim 1, wherein: The front of the chip has a chip pad, the surface of the frame pad has a boss, the top surface of the boss is close to the chip and the bottom surface is away from the chip, the chip pad is welded on the corresponding top surface of the boss, and the width of the chip pad is greater than the width of the corresponding top surface of the boss.
5. The chip packaging structure according to claim 4, wherein: The width of the top surface of the boss is smaller than the width of the bottom surface of the boss.
6. The chip packaging structure according to claim 5, wherein: Solder is provided between the chip pad and the top surface of the boss.
7. The chip packaging structure according to claim 1, wherein: The lead frame is made of copper.
8. The chip packaging structure according to claim 1, wherein: The chip includes a diode, the front side of the chip is the anode of the diode, and the back side of the chip is the cathode of the diode.
9. The chip packaging structure according to claim 1, wherein: The chip includes a transistor, the front side of the chip is the source or gate of the transistor, and the back side of the chip is the drain of the transistor.
10. The chip packaging structure according to claim 1, wherein: The chip is a power device.