Display substrate and display device

Abstract

According to the display substrate and the display device, the display substrate comprises a display area and a hole area, the display area is arranged around the hole area, and the hole area comprises a first area and a second area which are sequentially arranged away from the display area; a plurality of isolation columns are arranged in the first area and the second area, an insulation filling structure is filled between at least two adjacent isolation columns in the first area and the second area, and at least one insulation filling structure at least partially covers the side walls, close to the insulation filling structure, of the two adjacent isolation columns; the thickness of the at least one first insulation filling structure is smaller than that of the at least one second insulation filling structure, the first insulation filling structures are arranged between the adjacent first isolation columns, the first isolation columns are isolation columns located in the first area, and the second insulation filling structures are arranged between the adjacent second isolation columns; the second isolation column is an isolation column located in the second area.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present application provide a display substrate and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate comprising: a display area and a hole area, wherein the display area is arranged around the hole area, and the hole area comprises: a first area and a second area arranged sequentially away from the display area; a plurality of isolation pillars are provided in the first area and the second area, an insulating filling structure is filled between at least two adjacent isolation pillars in the first area and the second area, and at least one insulating filling structure at least partially covers sidewalls of two adjacent isolation pillars close to the insulating filling structure;

[0006] The thickness of at least one first insulating filling structure is less than the thickness of at least one second insulating filling structure, the first insulating filling structure is arranged between adjacent first isolation columns, the first isolation columns are isolation columns located in the first area, and the second insulating filling structure is arranged between adjacent second isolation columns, the second isolation columns are isolation columns located in the second area.

[0007] In an exemplary embodiment, a ratio of a thickness of the second insulating filling structure to a thickness of the first insulating filling structure is between 1.05 and 3.85.

[0008] In an exemplary embodiment, the second insulating filling structure includes: a second sub-filling structure, or includes: a first sub-filling structure and a second sub-filling structure, and when the second insulating filling structure includes: the first sub-filling structure and the second sub-filling structure, the first sub-filling structure is located on a side of the second sub-filling structure close to the display area;

[0009] The thickness of the first sub-filling structure is smaller than the thickness of the second sub-filling structure.

[0010] In an exemplary embodiment, a thickness of the first insulating filling structure is smaller than a thickness of the second sub-filling structure.

[0011] In an exemplary embodiment, the display substrate includes: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, the light-emitting structure layer includes: an organic light-emitting layer and a cathode layer, the organic light-emitting layer and the cathode layer extending from the display area to the second frame area;

[0012] The organic light emitting layer and the cathode layer located in the first frame region or the second frame region are separated by at least one isolation column located in the first frame region or the second frame region;

[0013] The organic light-emitting layer located in the first frame region or the second frame region includes: a first organic structure and a second organic structure spaced apart from each other; the cathode layer located in the first frame region or the second frame region includes: a first cathode structure and a second cathode structure spaced apart from each other, the first cathode structure corresponding to the first organic structure in a one-to-one manner, and the second cathode structure corresponding to the second organic structure in a one-to-one manner;

[0014] The first organic structure is arranged between at least part of adjacent isolation columns and at least partly covers at least part of the side walls of adjacent isolation columns. The second organic structure is arranged on the surface of at least one isolation column away from the substrate. The first cathode structure is arranged between at least part of adjacent isolation columns and at least partly covers the side walls of adjacent isolation columns. The second cathode structure is arranged on the side of the second organic structure away from the substrate. The maximum distance between the surface of at least one second organic structure away from the substrate and the substrate is greater than the maximum distance between the surface of the first cathode structure away from the substrate and the substrate.

[0015] In an exemplary embodiment, the second organic structures provided on the two isolation columns with the insulating filling structure therebetween are interconnected, and their orthographic projections on the substrate cover the orthographic projections of the insulating filling structure on the substrate, and the second cathode structures provided on the two isolation columns with the insulating filling structure therebetween are interconnected, and their orthographic projections on the substrate cover the orthographic projections of the insulating filling structure on the substrate.

[0016] In an exemplary embodiment, the display substrate includes: a base and a circuit structure layer disposed on the base, the circuit structure layer including: M source / drain metal layers, the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the base, M ≥ 2, 1 ≤ m ≤ M-1;

[0017] At least one isolation column among the plurality of isolation columns comprises a first isolation structure, and the first isolation structure of the at least one isolation column among the plurality of isolation columns is located in one of the M source / drain metal layers.

[0018] In an exemplary embodiment, the display substrate includes: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, the light-emitting structure layer includes: a pixel definition layer, and the circuit structure layer includes: N planar layers sequentially stacked on the base, the n+1th planar layer is located on a side of the nth planar layer away from the base, 1≤N≤M, 1≤n≤N-1;

[0019] The first insulating filling structure is located in the Nth planarization layer or the pixel definition layer.

[0020] In an exemplary embodiment, the display substrate includes: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, the light-emitting structure layer includes: a pixel definition layer, and the circuit structure layer includes: N planar layers sequentially stacked on the base, the n+1th planar layer is located on a side of the nth planar layer away from the base, 1≤N≤M, 1≤n≤N-1;

[0021] The first sub-filling structure is located in the Nth planar layer or pixel definition layer.

[0022] In an exemplary embodiment, the display substrate includes: a base and a light emitting structure layer disposed on the base, the light emitting structure layer includes: a pixel definition layer and a spacer disposed on the pixel definition layer;

[0023] The second sub-filling structure is arranged in the same layer as the spacer.

[0024] In an exemplary embodiment, the circuit structure layer further includes: K gate metal layers sequentially stacked on the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate;

[0025] At least one of the plurality of isolation pillars further comprises: at least one isolation structure from the second isolation structure to the K+1th isolation structure, wherein an orthographic projection of at least one of the second isolation structure to the K+1th isolation structure on the substrate overlaps with an orthographic projection of the first isolation structure;

[0026] The k+1th isolation structure is located in the kth gate metal layer, 1≤k≤K.

[0027] In an exemplary embodiment, the hole area further includes: a third area and a fourth area, the third area is located between the first area and the second area, and the fourth area is located on a side of the second area away from the display area;

[0028] The third region is provided with at least one isolation dam, and the fourth region is provided with a cutting groove or at least one isolation column.

[0029] In an exemplary embodiment, the display substrate includes: a base and a circuit structure layer disposed on the base, the circuit structure layer further including: a plurality of inorganic insulating layers and a plurality of organic insulating layers; the frame region includes: a composite insulating layer, the composite insulating layer including: a plurality of inorganic insulating layers located on a side of the Mth source / drain metal layer close to the base, the inorganic insulating layer extending from the display region to the fourth region;

[0030] The cutting groove is arranged in the composite insulating layer.

[0031] In an exemplary embodiment, the first isolation structure of at least one isolation column among the plurality of isolation columns includes: a first isolation portion, a second isolation portion, and a third isolation portion, wherein the first isolation portion is located on a side of the second isolation portion close to the substrate, and the third isolation portion is located on a side of the second isolation portion away from the substrate;

[0032] The orthographic projection of the surface of the second isolation portion close to the substrate on the substrate is located within the range of the orthographic projection of the surface of the first isolation portion away from the substrate on the substrate, and the orthographic projection of the surface of the second isolation portion away from the substrate on the substrate is located within the range of the orthographic projection of the surface of the third isolation portion close to the substrate on the substrate.

[0033] In an exemplary embodiment, the first insulating filling structure overlaps an orthographic projection of the third isolation portion of the first isolation column on the substrate, and the second insulating filling structure overlaps an orthographic projection of the third isolation portion of the second isolation column on the substrate.

[0034] In an exemplary embodiment, the present invention includes: a substrate, the isolation column is disposed on the substrate, at least one of the isolation columns includes: L conductive structures and L insulating structures arranged in a stacked manner, the L conductive structures and the L insulating structures being alternately arranged, the lth insulating structure being located on a side of the lth conductive structure away from the substrate, and L being a positive integer greater than or equal to 1;

[0035] At least one sidewall of the conductive structure is in a groove shape.

[0036] In an exemplary embodiment, when L is greater than or equal to 2, the orthographic projection of the surface of the lth conductive structure close to the substrate on the substrate is located within the range of the orthographic projection of the surface of the l-1th insulating structure away from the substrate on the substrate, and the maximum distance between the side wall of the lth conductive structure and the center line of the isolation column is less than the minimum distance between the side wall of the l-1th insulating structure and the center line of the isolation column.

[0037] In an exemplary embodiment, the isolation column includes: a first conductive structure and a first insulating structure;

[0038] The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1;

[0039] The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0040] The first conductive structure is located in one of the K gate metal layers and the M source / drain metal layers, and the first insulating structure is located in one of the multiple inorganic insulating layers.

[0041] In an exemplary embodiment, the isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure;

[0042] The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1;

[0043] The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0044] At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and the M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multi-layer inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

[0045] In an exemplary embodiment, the isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure;

[0046] The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1;

[0047] The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer;

[0048] The first conductive structure, the second conductive structure and the third conductive structure are located in three of the K gate metal layers and the M source / drain metal layers, and the first conductive structure, the second conductive structure and the third conductive structure are located in different layers; the first insulating structure, the second insulating structure and the third insulating structure are located in three of the multi-layer inorganic insulating layers, and the first insulating structure, the second insulating structure and the third insulating structure are located in different layers.

[0049] In an exemplary embodiment, the display substrate includes: a base, and a circuit structure layer and a light emitting structure layer sequentially stacked on the base, the light emitting structure layer includes: a pixel definition layer, and the circuit structure layer includes: a plurality of planar layers sequentially stacked on the base;

[0050] At least one isolation dam includes: a plurality of dam bases stacked in sequence in a direction away from the substrate, at least one of the plurality of dam bases is located on at least one flat layer, and at least one of the plurality of dam bases is located on a pixel definition layer.

[0051] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0052] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0054] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0055] Figure 2 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 1 ;

[0056] Figure 3 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 2 ;

[0057] Figure 4 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 3 ;

[0058] Figure 5 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 4 ;

[0059] Figure 6 Schematic diagram of the structure of the display substrate in the hole area provided by the embodiment of the present disclosure Figure 1 ;

[0060] Figure 7 Schematic diagram of the structure of the display substrate in the hole area provided by the embodiment of the present disclosure Figure 2 ;

[0061] Figure 8 A schematic structural diagram of a hole region of a display substrate provided in an exemplary embodiment;

[0062] Figure 9 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 1 ;

[0063] Figure 10 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 2 ;

[0064] Figure 11 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 3 ;

[0065] Figure 12 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 4 ;

[0066] Figure 13 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 5 ;

[0067] Figure 14 A schematic diagram of a portion of the structure of the first area and the second area provided in an embodiment of the present disclosure;

[0068] Figure 15 for Figure 14 Schematic diagram of the provided film layers Figure 1 ;

[0069] Figure 16 for Figure 14 Schematic diagram of the provided film layers Figure 2 ;

[0070] Figure 17 for Figure 14 Schematic diagram of the provided film layers Figure 3 ;

[0071] Figure 18 for Figure 14 Schematic diagram of the provided film layers Figure 4 ;

[0072] Figure 19 for Figure 14 Schematic diagram of the provided film layers Figure 5 ;

[0073] Figure 20 for Figure 14 Schematic diagram of the provided film layers Figure 6 ;

[0074] Figure 21 for Figure 14 Schematic diagram of the provided film layers Figure 7 ;

[0075] Figure 22 for Figure 14 Schematic diagram of the provided film layers Figure 8 ;

[0076] Figure 23 for Figure 14 Schematic diagram of the provided film layers Figure 9 ;

[0077] Figure 24 for Figure 14 Schematic diagram of the provided film layers Figure 10 ;

[0078] Figure 25 for Figure 14 Schematic diagram of the provided film layers Figure 10 one;

[0079] Figure 26 for Figure 14 Schematic diagram of the provided film layers Figure 10 two;

[0080] Figure 27 for Figure 14 Schematic diagram of the provided film layers Figure 10 three;

[0081] Figure 28 for Figure 14 Schematic diagram of the provided film layers Figure 10 Four;

[0082] Figure 29 for Figure 14 Schematic diagram of the provided film layers Figure 10 five;

[0083] Figure 30 for Figure 14 Schematic diagram of the provided film layers Figure 10 six;

[0084] Figure 31 for Figure 14 Schematic diagram of the provided film layers Figure 10 seven;

[0085] Figure 32 for Figure 14 Schematic diagram of the provided film layers Figure 10 eight;

[0086] Figure 33 for Figure 14 Schematic diagram of the provided film layers Figure 10 Nine;

[0087] Figure 34 for Figure 14 Schematic diagram of the provided film layers Figure 2 ten;

[0088] Figure 35 for Figure 14 Schematic diagram of the provided film layers Figure 2 eleven;

[0089] Figure 36 is a schematic diagram after the composite insulation layer is formed;

[0090] Figure 37 is a schematic diagram after forming the first isolation structure;

[0091] Figure 38 is a schematic diagram after forming an insulating filling structure;

[0092] Figure 39 for Figures 15 to 20 A schematic diagram after forming a first isolation insulating layer;

[0093] Figure 40 for Figures 15 to 20 A schematic diagram after forming a first insulating structure;

[0094] Figure 41 for Figures 15 to 20 A schematic diagram after forming a first conductive structure;

[0095] Figure 42 for Figures 15 to 20 Schematic diagram after forming the insulating filling structure;

[0096] Figure 43 for Figures 15 to 20 Schematic diagram after forming multiple covering structures;

[0097] Figure 44 for Figures 21 to 29 A schematic diagram after forming a second isolation insulating layer;

[0098] Figure 45 for Figures 21 to 29 A schematic diagram after forming the first insulating structure and the second insulating structure;

[0099] Figure 46 for Figures 20 to 29 A schematic diagram after forming the first conductive structure and the second conductive structure;

[0100] Figure 47 for Figures 21 to 29 Schematic diagram after forming the insulating filling structure;

[0101] Figure 48 for Figures 21 to 29 Schematic diagram after forming multiple covering structures;

[0102] Figure 49 for Figures 30 to 34 A schematic diagram after forming a third isolation insulating layer;

[0103] Figure 50 for Figures 30 to 34 A schematic diagram after forming the first insulating structure, the second insulating structure and the third insulating structure;

[0104] Figure 51 for Figures 30 to 34 A schematic diagram after forming the first conductive structure, the second conductive structure and the third conductive structure;

[0105] Figure 52 for Figures 30 to 34 Schematic diagram after forming the insulating filling structure;

[0106] Figure 53 for Figures 30 to 34Schematic diagram after forming multiple covering structures;

[0107] Figure 54 for Figure 35 A schematic diagram after forming a fourth isolation insulating layer;

[0108] Figure 55 for Figure 35 A schematic diagram after forming a first insulating structure, a second insulating structure, a third insulating structure, and a fourth insulating structure;

[0109] Figure 56 for Figure 35 A schematic diagram after forming a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure;

[0110] Figure 57 for Figure 35 Schematic diagram after forming the insulating filling structure;

[0111] Figure 58 for Figure 35 Schematic diagram after forming multiple covering structures;

[0112] Figure 59 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0114] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0115] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0116] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0117] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two elements. Among them, "connection" can include "electrical connection", and "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances.

[0118] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0119] In this specification, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. Furthermore, the gate electrode can also be referred to as a control electrode. The functions of "source" and "drain" are sometimes interchangeable when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchangeable.

[0120] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0121] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0122] In this specification, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In this disclosure, "substantially the same" means that the numerical values differ by less than 10%.

[0123] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0124] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0125] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features being referred to. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include at least one of the features.

[0126] In the embodiments of the present disclosure, the thickness of a component refers to the dimension of the component in a direction perpendicular to the substrate.

[0127] The display substrate includes a display area and a hole area. When the isolation column located in the hole area is energized, electrochemical corrosion will occur, and there will be residual glue on the isolation column. When the display substrate is opened, water vapor will enter the display area along the residual glue, which may cause black spots to appear on the display substrate, affecting the display effect of the display substrate.

[0128] Figure 1 FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the shape of the display substrate can be a closed polygon including linear edges. The display substrate may include: a display area AA, a hole area VV at least partially surrounded by the display area AA, a binding area BB located on one side of the display area AA, and a frame area CC located on at least one side of the display area AA. For example, the display area AA may include: a first display edge (lower display edge) and a second display edge (upper display edge) arranged opposite to each other in the first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) arranged opposite to each other in the second direction D2. The first display edge and the second display edge may be linear edges parallel to each other, and the third display edge and the fourth display edge may be linear edges parallel to each other. Adjacent linear edges may be connected by curved edges (e.g., arcuate edges).

[0129] In an exemplary embodiment, the hole region VV may be circular. The hole region VV may also be in other suitable shapes, not limited to a circular shape. Furthermore, the location of the hole region VV is not limited to the center of the display area and may be set as needed.

[0130] In an exemplary embodiment, at least part of the structure in the hole region VV is removed. For example, all structures in the hole region VV of the display substrate are removed. For example, after forming the encapsulation layer, a hole is dug to remove the portion of the display substrate located in the hole region VV.

[0131] In an exemplary embodiment, the display device may further include: a sensor, which may be disposed in the hole area VV or may be entirely disposed in the hole area. For example, the sensor may include a camera.

[0132] In an exemplary embodiment, Figure 1 As shown, the binding area BB may connect the first display edge.

[0133] In an exemplary embodiment, Figure 1 As shown, the frame area CC may include: an upper frame area of the display substrate, a left frame area of the display substrate, and a right frame area of the display substrate. However, this embodiment is not limited to this.

[0134] In an exemplary embodiment, Figure 1As shown, the binding area BB may include: a first sub-area B11, a bending area B12, and a second sub-area B13 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B11 can also be referred to as a first fan-out area. The first sub-area B11 can be connected to the left and right border areas and connected to the display area AA. The bending area B12 can be connected between the first sub-area B11 and the second sub-area B13. The bending area B12 can be configured to bend the second sub-area B13 to the back of the display area AA.

[0135] In an exemplary embodiment, the second sub-area B13 of the binding area BB may include: a second fan-out area, a circuit setting area, a third fan-out area, a first signal access area B134 and a second signal access area B135, which are arranged in sequence in the first direction D1 along a direction away from the bending area B12.

[0136] In an exemplary embodiment, Figure 1 As shown, the display area AA of the display substrate may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX. For example, the pixel control signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0137] In an exemplary embodiment, the second direction D2 may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA; the first direction D1 may be an extending direction (e.g., a column direction) of the data lines in the display area AA. The first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.

[0138] In an exemplary embodiment, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light). However, this embodiment is not limited to this. In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0139] In an exemplary embodiment, a sub-pixel may include: a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit may include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In an exemplary embodiment, the plurality of transistors in the pixel driving circuit may include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel driving circuit may be P-type transistors or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0140] In an exemplary embodiment, the shape of the light-emitting elements of a sub-pixel can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0141] In an exemplary embodiment, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element may be determined as needed. In an exemplary embodiment, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited to this.

[0142] The display substrate of this example may be integrated with a touch structure, for example, an integrated mutual capacitance touch structure, to form an FMLOC structure.

[0143] In an exemplary embodiment, the display substrate may include a base, and a circuit structure layer and a light emitting structure layer sequentially disposed on the base, wherein the circuit structure layer includes a pixel driving circuit located in the display area, and the light emitting structure layer includes a light emitting element located in the display area.

[0144] In an exemplary embodiment, the display substrate may further include at least one film layer of an encapsulation structure layer and a touch structure layer, which is not limited in the present disclosure.

[0145] Figure 2 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 1 , Figure 2 In this example, the structure of a sub-pixel in the display area is used as an example for illustration. In this example, the pixel driving circuit includes a low-temperature polysilicon thin film transistor as an example for description.

[0146] In an exemplary embodiment, Figure 2As shown, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on a substrate 10. A first insulating layer 101 (which may be referred to as a buffer layer) may be disposed between the substrate and the semiconductor layer; a second insulating layer 102 (which may be referred to as a first gate insulating layer) may be disposed between the semiconductor layer and the first gate metal layer; a third insulating layer 103 (which may be referred to as a second gate insulating layer) may be disposed between the first gate metal layer and the second gate metal layer; a fifth insulating layer 105 (which may be referred to as an interlayer insulating layer) may be disposed between the second gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (which may also be referred to as a passivation layer) and a seventh insulating layer 107 (which may also be referred to as a first planarizing layer) may be disposed between the first source-drain metal layer and the second source-drain metal layer; the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (which may also be referred to as a second planarizing layer) may be disposed on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. The present disclosure is illustrated by taking the display substrate as an example including two gate metal layers and two source and drain metal layers. However, this embodiment is not limited to this. In other examples, a bottom shielding metal layer (BSM) can be further provided on the side of the first insulating layer close to the substrate, and the bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel driving circuit to prevent external light from affecting the performance of the transistor. In other examples, only the sixth insulating layer or the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0147] In an exemplary embodiment, Figure 2 As shown, the semiconductor layer may include at least a first active layer 210 of the transistor 21 located in the display area. The first active layer 210 of the transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate electrode 213 of the transistor 21 located in the display area and a first plate 231 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 located in the display area and a third gate electrode 224 of the second-type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, the two may coincide.

[0148] In an exemplary embodiment, Figure 2 As shown, the first source-drain metal layer in the display area may include at least: a first source electrode 211 and a first drain electrode 212 of the transistor 21 located in the display area. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via and a second pixel via) in the display area. The fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The fifth insulating layer 105, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The first source electrode 211 of the transistor 21 may be electrically connected to the first region 2101 of the first active layer 210 via the first pixel via, and the first drain electrode 212 may be electrically connected to the second region 2102 of the first active layer 210 via the second pixel via. The second source-drain metal layer may include at least a first switching electrode 241. The first switching electrode 241 may be electrically connected to the first drain electrode 212 of the transistor 21 of the pixel driving circuit through a fifth pixel via hole defined by the sixth insulating layer 106 and the seventh insulating layer 107. In this example, the first switching electrode 241 may be used to achieve electrical connection between the pixel driving circuit and the light-emitting element.

[0149] In an exemplary embodiment, the gate line of the display area may be located in the first gate metal layer and the second gate metal layer, the data line of the display area may be located in the second source / drain metal layer, and the first power line of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0150] In an exemplary embodiment, Figure 2As shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements located in the display area. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0151] In an exemplary embodiment, the light-emitting structure layer may include: an anode layer, an organic material layer and a cathode layer, the anode layer includes: a first electrode of at least one light-emitting element located in the display area, the organic material layer includes: an organic light-emitting layer of at least one light-emitting element located in the display area, and the cathode layer includes: a second electrode of at least one light-emitting element located in the display area.

[0152] In an exemplary embodiment, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the desired grayscale.

[0153] In an exemplary embodiment, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In an exemplary embodiment, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In an exemplary embodiment, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0154] In an exemplary embodiment, Figure 2 As shown, the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0155] In an exemplary embodiment, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0156] In an exemplary embodiment, Figure 2As shown, in a direction perpendicular to the display substrate, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protection layer (TOC) 154, which are arranged in sequence. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the touch protection layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integrated structure connected to each other. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes through vias provided in the touch interlayer insulating layer 153. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be interconnected as an integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In an exemplary embodiment, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0157] In an exemplary embodiment, the first touch electrode and the second touch electrode may have a rhombus shape, for example, a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the present disclosure.

[0158] In an exemplary embodiment, the first and second touch electrodes may be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0159] Figure 3 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 2 In an exemplary embodiment, as Figure 3As shown, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged on the substrate 10. A fourth insulating layer 104 (which may be referred to as a third gate insulating layer) may be provided between the second gate metal layer and the third gate metal layer; a fifth insulating layer 105 (which may be referred to as an interlayer insulating layer) may be provided between the third gate metal layer and the first source-drain metal layer. Among them, the fourth insulating layer 104 may be an inorganic insulating layer. The present disclosure is described by taking the display substrate including three gate metal layers and two source-drain metal layers as an example. However, this embodiment is not limited to this. The remaining structures of the display area of the display substrate of this example can be referred to. Figure 2 The description of the embodiment shown is omitted here.

[0160] In an exemplary embodiment, the third gate metal layer may include a third electrode plate 233 of a capacitor located in the display area, the third electrode plate 233 is connected to the first electrode plate 231, and the orthographic projection of the third electrode plate 233 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode plate 232 on the substrate 10, for example, may coincide.

[0161] In an exemplary embodiment, the gate line of the display area may be located in at least one of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the data line of the display area may be located in the second source / drain metal layer, and the first power line of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0162] Figure 4 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 3 In an exemplary embodiment, as Figure 4 As shown, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. An eighth insulating layer 108 (which may also be called a second flat layer) may be arranged between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 (which may also be called a third flat layer) may be arranged on the side of the third source-drain metal layer away from the substrate 10. The present disclosure is explained by taking the display substrate including two gate metal layers and three source-drain metal layers as an example. This example can realize the electrical connection between the pixel driving circuit and the light-emitting element through the first transfer electrode 241 and the second transfer electrode 242. For the remaining structures of the display area of the display substrate of this example, please refer to Figure 2 The description of the embodiment shown is omitted here.

[0163] In an exemplary embodiment, the gate line of the display area may be located, for example, in the first gate metal layer and the second gate metal layer, the data line of the display area may be located, for example, in the second source / drain metal layer or the third source / drain metal layer, and the first power line of the display area may be located, for example, in the second source / drain metal layer or the third source / drain metal layer. This embodiment is not limited to this.

[0164] Figure 5 A partial cross-sectional view of the display area of at least one embodiment of the present disclosure Figure 4 In an exemplary embodiment, as Figure 5 As shown, the circuit structure layer 12 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate 10. A fourth insulating layer 104 (which may be referred to as a third gate insulating layer) may be provided between the second gate metal layer and the third gate metal layer, an eighth insulating layer 108 (which may also be referred to as a second flat layer) may be provided between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 (which may also be referred to as a third flat layer) may be provided on the side of the third source-drain metal layer away from the substrate 10. The fourth insulating layer 104 may be an inorganic insulating layer, and the ninth insulating layer 109 may be an organic insulating layer. The present disclosure is illustrated by taking the display substrate including three gate metal layers and three source-drain metal layers as an example. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transfer electrode 241 and the second transfer electrode 242. For the remaining structures of the display area of the display substrate of this example, reference may be made to Figure 2 and Figure 3 The description of the embodiment shown is omitted here.

[0165] In an exemplary embodiment, the gate line of the display area may be located in at least one of the first gate metal layer, the second gate metal layer, and the third gate metal layer, the data line of the display area may be located in the second source / drain metal layer or the third source / drain metal layer, and the first power line of the display area may be located in the second source / drain metal layer or the third source / drain metal layer. This embodiment is not limited to this.

[0166] Figure 6 Schematic diagram of the structure of the display substrate in the hole area provided by the embodiment of the present disclosure Figure 1 , Figure 7 Schematic diagram of the structure of the display substrate in the hole area provided by the embodiment of the present disclosure Figure 2 .like Figure 6 and Figure 7As shown, the display substrate provided by the embodiment of the present disclosure includes: a display area (not shown in the figure) and a hole area, the hole area includes: a first area R1 and a second area R2 arranged in sequence away from the display area; the first area R1 and the second area R2 are provided with a plurality of isolation columns 300, and an insulating filling structure 400 is filled between at least two adjacent isolation columns 300 located in the first area R1 and the second area R2, and at least one insulating filling structure 400 at least partially covers the side walls of the two adjacent isolation columns 300 close to the insulating filling structure 400.

[0167] like Figure 6 and Figure 7 As shown, the thickness H1 of at least one first insulating filling structure 410 is less than the thickness H2 of at least one second insulating filling structure 420, wherein the first insulating filling structure 410 is arranged between adjacent first isolation columns 310, and the first isolation columns 310 are isolation columns located in the first region R1, and the second insulating filling structure 420 is arranged between adjacent second isolation columns 320, and the second isolation columns 320 are isolation columns located in the second region R2. Figure 6 and Figure 7 The description is made by taking an example that the thickness of any one of the at least one first insulating filling structures 410 is smaller than the thickness of any one of the second insulating filling structures 420 .

[0168] In example embodiments, the light transmittance of the at least one second insulating filling structure 420 may be lower than the light transmittance of the at least one first insulating filling structure 410 .

[0169] In an exemplary embodiment, the display substrate includes a base 10 covering the display area and the hole area VV.

[0170] In an exemplary embodiment, Figure 6 and Figure 7 As shown, a distance W1 between the surface of the at least one insulating filling structure 400 away from the substrate 10 and the substrate 10 is greater than a distance W2 between the surface of the at least one isolation column 300 away from the substrate 10 and the substrate 10 .

[0171] The present disclosure sets the thickness H1 of at least one first insulating filling structure 410 to be smaller than the thickness H2 of at least one second insulating filling structure 420, thereby not only disconnecting the power supply to the frame area, but also removing the residual glue in the first isolation column through the first insulating filling structure with smaller thickness, thereby effectively solving the black spot problem of the display substrate and improving the display effect of the display substrate.

[0172] In an exemplary embodiment, Figure 6 and Figure 7As shown, the display substrate further includes: a circuit structure layer and a light emitting structure layer sequentially stacked on the base. The frame region includes: a composite insulating layer 20, at least part of at least one isolation column is located on a side of the composite insulating layer 20 away from the base.

[0173] In exemplary embodiments, the thickness H1 of the first insulating filling structure 410 may be 0.8 micrometers to 2.1 micrometers.

[0174] In exemplary embodiments, the thickness H2 of the second insulating filling structure 420 may be 2.3 micrometers to 3 micrometers.

[0175] In exemplary embodiments, a ratio of the thickness H2 of the second insulating filling structure 420 to the thickness H1 of the first insulating filling structure 410 may be between 1.05 and 3.85.

[0176] In the present disclosure, the thickness of a structure refers to the vertical distance between the highest point of the surface of the structure away from the substrate and the surface of the composite insulating layer 20 on the substrate away from the substrate.

[0177] In an exemplary embodiment, Figure 6 and Figure 7 As shown, the frame area further includes: a third area R3 and a fourth area R4. The third area R3 is located between the first area R1 and the second area R2. The fourth area R4 is located on a side of the second area away from the display area.

[0178] In exemplary embodiments, the third region R3 may be provided with at least one isolation dam 510 .

[0179] In an exemplary embodiment, Figure 6 As shown, the fourth region R4 may be provided with at least one third isolation column 330, or as shown in FIG. Figure 7 As shown, the fourth region R4 may be provided with a cutting groove V.

[0180] In an exemplary embodiment, the fourth region R4 may be referred to as a cutting region, and the display substrate is cut in the fourth region R4. In an exemplary embodiment, the provision of the third spacer or cutting groove in the fourth region R4 can reduce cracks when cutting the AAH hole, thereby improving the reliability of the display substrate.

[0181] In an exemplary embodiment, a distance W3 between the surface of the isolation dam 510 away from the substrate 10 and the substrate 10 is greater than a distance W2 between the surface of at least one of the first, second, and third isolation pillars 310 , 320 , and 330 away from the substrate 10 and the substrate.

[0182] In example embodiments, the second insulating filling structure may include a second sub-filling structure, or may include a first sub-filling structure and a second sub-filling structure, the first sub-filling structure having a different thickness from the second sub-filling structure.

[0183] In an exemplary embodiment, Figure 8 FIG. 1 is a schematic structural diagram of a hole region of a display substrate provided in an exemplary embodiment. Figure 8 As shown, the second insulating filling structure 420 includes a first sub-filling structure 421 and a second sub-filling structure 422 , and the first sub-filling structure 421 is located on a side of the second sub-filling structure 422 close to the display area.

[0184] In an exemplary embodiment, Figure 8 As shown, the thickness H21 of the first sub-filling structure 421 is less than the thickness H22 of the second sub-filling structure 422. The thickness of the filling structure refers to the vertical distance between the highest point of the filling structure away from the substrate surface and the surface of the composite insulating layer 20 on the substrate away from the substrate.

[0185] In example embodiments, the light transmittance of the first sub-filling structure 421 may be greater than the light transmittance of the second sub-filling structure 422 .

[0186] In an exemplary embodiment, Figure 8 As shown, the thickness H1 of the first insulating filling structure 410 is less than the thickness H22 of the second sub-filling structure 422. The thickness of the first insulating filling structure 410 may be greater than the thickness H21 of the first sub-filling structure 421, or may be equal to the thickness H21 of the first sub-filling structure 421, or may be less than the thickness H21 of the first sub-filling structure 421, and this disclosure does not impose any limitation on this.

[0187] Figure 9 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 1 , Figure 10 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 2 , Figure 11 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 3 , Figure 12 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 4 , Figure 13 A schematic diagram of a film layer in a hole area of a display substrate provided in an exemplary embodiment Figure 5 . Figure 9 、 Figure 10 and Figure 12 The circuit structure layer includes three gate metal layers as an example for explanation. Figure 11and Figure 13 The circuit structure layer includes two gate metal layers as an example for explanation. Figures 9 to 11 The description is made by taking an example where all insulating filling structures in the second region R2 have the same thickness. Figure 12 and Figure 13 The description is made by taking an example where the insulating filling structure located in the second region R2 includes a first sub-filling structure 421 and a second sub-filling structure 422 with different thicknesses.

[0188] In an exemplary embodiment, a display substrate includes a base, and a circuit structure layer and a light emitting structure layer sequentially stacked on the base.

[0189] In an exemplary embodiment, Figures 9 to 13 As shown, the circuit structure layer includes: M source-drain metal layers, the m+1th source-drain metal layer is located on the side of the mth source-drain metal layer away from the substrate 10, M ≥ 2, 1 ≤ m ≤ M-1. Exemplarily, the circuit structure layer may include a first source-drain metal layer and a second source-drain metal layer, or may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, and the present disclosure does not impose any limitation on this.

[0190] In an exemplary embodiment, Figures 9 to 13 As shown, at least one isolation column among the multiple isolation columns located in the first region and the second region includes: a first isolation structure 301, and the first isolation structure 301 of at least one isolation column among the multiple isolation columns located in the first region and the second region is located in one of the metal layers in the Mth source and drain metal layer.

[0191] In an exemplary embodiment, Figures 9 to 13 As shown, the circuit structure layer further includes: K gate metal layers stacked sequentially on the substrate 10, with the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate 10. Exemplarily, the circuit structure layer may include: a first gate metal layer and a second gate metal layer, or may include: a first gate metal layer, a second gate metal layer, and a third gate metal layer.

[0192] In an exemplary embodiment, at least one of the first isolation column 310, the second isolation column 320 and the third isolation column further includes at least: at least one isolation structure from the second isolation structure to the K+1th isolation structure; the orthographic projection of at least one isolation structure from the second isolation structure to the K+1th isolation structure on the substrate overlaps with the orthographic projection of the first isolation structure, wherein the k+1th isolation structure is located in the kth gate metal layer, 1≤k≤K.

[0193] In an exemplary embodiment, Figures 9 to 13As shown, the first isolation structure 301 of at least one of the first isolation column 310, the second isolation column 320 and the third isolation column includes: a first isolation portion 3011, a second isolation portion 3012 and a third isolation portion 3013, the first isolation portion 3011 is located on the side of the second isolation portion 3012 close to the substrate 10, and the third isolation portion 3013 is located on the side of the second isolation portion 3012 away from the substrate 10.

[0194] In an exemplary embodiment, Figures 9 to 13 As shown, the orthographic projection of the surface of the second isolation portion 3012 close to the substrate 10 on the substrate 10 is located within the range of the orthographic projection of the surface of the first isolation portion 3011 away from the substrate 10 on the substrate 10, the orthographic projection of the surface of the second isolation portion 3012 away from the substrate 10 on the substrate 10 is located within the range of the orthographic projection of the surface of the third isolation portion 3013 close to the substrate 10 on the substrate 10, the orthographic projection of the surface of the second isolation portion 3012 away from the substrate 10 on the substrate 10 is located within the range of the orthographic projection of the surface of the second isolation portion 3012 close to the substrate 10 on the substrate 10, and the side wall of the second isolation portion 3012 is set at an acute angle to the surface of the second isolation portion 3012 close to the substrate 10. Exemplarily, the shape of the longitudinal section of the second isolation portion 3012 can be trapezoidal, and the shape of the longitudinal section of the first isolation structure 301 can be I-shaped.

[0195] In an exemplary embodiment, the conductivity of the second isolating portion 3012 is greater than the conductivity of at least one of the first isolating portion 3011 and the third isolating portion 3013. In an exemplary embodiment, the second isolating portion 3012 may be made of aluminum (Al) or copper (Cu), and the first isolating portion 3011 and the third isolating portion 3013 may be made of an inert metal, such as titanium (Ti) or molybdenum (Mo).

[0196] In an exemplary embodiment, Figure 13 As shown, the length L1 of the third isolation portion of at least one first isolation column 310 is in the range of 4 μm to 5.5 μm.

[0197] In an exemplary embodiment, Figure 13 As shown, the length L2 of the third isolation portion of at least one second isolation pillar 320 is in the range of 4 μm to 5.5 μm.

[0198] In an exemplary embodiment, Figure 13 As shown, the first insulating filling structure 410 overlaps with the orthographic projection of the third isolation portion of the first isolation column 310 on the substrate, and the second insulating filling structure 420 overlaps with the orthographic projection of the third isolation portion of the second isolation column 320 on the substrate.

[0199] In an exemplary embodiment, Figure 13As shown, the portion of the third isolation portion of at least one isolation column covered by the first insulating filling structure 410 or the first sub-insulating structure 421 is a first sub-isolation portion, and a length L3 of the first sub-isolation portion is in the range of 0.2 microns to 2.4 microns.

[0200] In an exemplary embodiment, Figure 13 As shown, the third isolation portion of the second isolation column 320 includes: a second sub-isolation portion, the orthographic projection of the second sub-isolation portion on the substrate is covered by the orthographic projection of the second sub-filling structure 421 on the substrate, and the length L4 of the second sub-isolation portion is in the range of 0.4 μm to 4.1 μm.

[0201] In an exemplary embodiment, Figure 13 As shown, the ratio of the length L3 of the first sub-isolating portion to the length L1 of the third isolating portion is in the range of 0.2 to 0.35.

[0202] In an exemplary embodiment, Figure 13 As shown, the ratio of the length L4 of the second sub-isolating portion to the length L2 of the third isolating portion is in the range of 0.4 to 0.55.

[0203] In an exemplary embodiment, Figure 13 As shown, the ratio of the distance L5 between the highest point of the surface of the first insulating filling structure 410 and the first sub-filling structure 421 away from the substrate and the surface of the target conductive structure away from the substrate to the distance L6 between the highest point of the surface of the isolation column 300 covered by the first insulating filling structure 410 and the first sub-filling structure 421 away from the substrate and the surface of the target conductive structure away from the substrate is in a range of 0.55 to 0.8. The target conductive structure is the conductive structure farthest from the substrate among the at least one conductive structure located in the gate metal layer.

[0204] In an exemplary embodiment, Figure 13 As shown, the ratio of the distance L7 between the highest point of the second sub-filling structure 422 away from the substrate surface and the target conductive structure away from the substrate to the distance L8 between the highest point of the first isolation column 320 away from the substrate surface and the target conductive structure away from the substrate is in a range of 0.35 to 0.5. The target conductive structure is the conductive structure farthest from the substrate among the at least one conductive structure located in the gate metal layer.

[0205] In an exemplary embodiment, Figure 13 As shown, an angle A1 between surfaces of the first insulating filling structure 410 and the first sub-filling structure 421 away from the substrate 10 and a surface of the first isolation column 310 away from the substrate is in a range of 8 degrees to 37 degrees.

[0206] In an exemplary embodiment, Figure 13 As shown, an angle A2 between a surface of the second sub-filling structure 422 away from the substrate 10 and a surface of the second isolation pillar 320 away from the substrate 10 is in a range of 30 degrees to 60 degrees.

[0207] In an exemplary embodiment, the circuit structure layer further includes: N planar layers stacked sequentially on the substrate 10, the n+1th planar layer being located on the side of the nth planar layer away from the substrate 10, 1≤N≤M, 1≤n≤N-1. Exemplarily, the circuit structure layer may include: a first planar layer, or may include a first planar layer and a second planar layer, or may include a first planar layer, a second planar layer and a third planar layer, and the number of planar layers depends on the number of source and drain metal layers. The first planar layer may be Figures 2 to 5 The seventh insulating layer in the second flat layer can be Figures 2 to 5 The eighth insulating layer in the third flat layer can be Figure 3 and Figure 5 The ninth insulating layer in the present disclosure does not impose any limitation on this.

[0208] In an exemplary embodiment, the first insulating filling structure 410 is located in the Nth planar layer or pixel definition layer. In the present disclosure, the first insulating filling structure 410 is located in the Nth planar layer or pixel definition layer, which can reduce the thickness of the first insulating filling structure 410 and make subsequent residual adhesive removal easier.

[0209] In an exemplary embodiment, when the insulating filling structure located in the second region R2 includes a first sub-filling structure 421 and a second sub-filling structure 422, the first sub-filling structure 421 is located in the Nth planar layer or pixel definition layer. In the present disclosure, the location of the first sub-filling structure 421 in the Nth planar layer or pixel definition layer can reduce the thickness of the first insulating filling structure 410, thereby facilitating subsequent removal of residual adhesive.

[0210] In an exemplary embodiment, the first sub-filling structure 421 may be located in the Nth planar layer, and the first insulating filling structure 410 may be located in the Nth planar layer, or the first sub-filling structure 421 may be located in the Nth planar layer, and the first insulating filling structure 410 may be located in the pixel definition layer, or the first sub-filling structure 421 may be located in the pixel definition layer, and the first insulating filling structure 410 may be located in the Nth planar layer, or the first sub-filling structure 421 may be located in the pixel definition layer, and the first insulating filling structure 410 may be located in the pixel definition layer. The present disclosure does not impose any limitations on this.

[0211] In an exemplary embodiment, the light emitting structure layer further includes: spacers disposed on the pixel definition layer; and the second sub-filling structure 422 is disposed in the same layer as the spacers.

[0212] In an exemplary embodiment, the frame region includes: a composite insulating layer 20, which includes: a plurality of inorganic insulating layers located on the side of the M-th source and drain metal layer close to the substrate 10, and the inorganic insulating layers extend from the display region to the fourth region R4. Figure 9 、 Figure 10 and Figure 12 In the provided display substrate, the inorganic insulating layer includes: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105 and a sixth insulating layer 106, Figure 11 and Figure 13 The composite insulating layer in the provided display substrate includes: a first insulating layer 101 , a second insulating layer 102 , a third insulating layer 103 , a fifth insulating layer 105 and a sixth insulating layer 106 .

[0213] In an exemplary embodiment, Figure 9 、 Figures 11 to 13 As shown, the cutting groove V is provided in the composite insulating layer 20 .

[0214] In an exemplary embodiment, Figures 9 to 13 As shown, the organic light-emitting layer and the cathode layer extend from the display area to the second area R2. The organic light-emitting layer and the cathode layer located in the first frame area R1 or the second frame area R2 are separated by at least one isolation column located in the first frame area R1 or the second frame area R2. The organic light-emitting layer located in the first region R1 or the second region R2 includes: a first organic structure 611 and a second organic structure 621 spaced apart from each other. The cathode layer located in the first region R1 or the second region R2 includes: a first cathode structure 612 and a second cathode structure 622 spaced apart from each other, with the first cathode structure 612 corresponding one-to-one to the first organic structure 611, and the second cathode structure 622 corresponding one-to-one to the second organic structure 621.

[0215] In an exemplary embodiment, the orthographic projection of the first cathode structure 612 on the substrate 10 may at least partially overlap with the orthographic projection of the second cathode structure 622 on the substrate 10 , and the orthographic projection of the first organic structure 611 on the substrate 10 may at least partially overlap with the orthographic projection of the second organic structure 621 on the substrate 10 .

[0216] In an exemplary embodiment, the first organic structure 611 is disposed between at least a portion of adjacent isolation pillars 300 and at least partially covers at least a portion of a sidewall of the second isolation portion 3012 of the adjacent isolation pillars 300. The second organic structure 621 is disposed on a surface of at least one isolation pillar 300 away from the substrate 10. The first cathode structure 612 is disposed between at least a portion of adjacent isolation pillars 300 and at least partially covers a sidewall of the second isolation portion 3012 of the adjacent isolation pillars. The second cathode structure 622 is disposed on a side of the second organic structure 621 away from the substrate 10. The maximum distance between the surface of the at least one second organic structure 621 away from the substrate 10 and the substrate 10 is greater than the maximum distance between the surface of the first cathode structure 612 away from the substrate 10 and the substrate 10.

[0217] In an exemplary embodiment, the orthographic projection of the first organic structure 611 on the substrate 10 is within the range of the orthographic projection of the corresponding first cathode structure 612 on the substrate 10 , and the orthographic projection of the second cathode structure 622 on the substrate 10 is within the range of the orthographic projection of the corresponding second organic structure 621 on the substrate 10 .

[0218] In an exemplary embodiment, Figures 9 to 13 As shown, the second organic structures 621 arranged on the two isolation columns with the insulating filling structure 400 filled therebetween are interconnected, and the orthographic projection of the second organic structures 621 on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10, and the second cathode structures 622 arranged on the two isolation columns with the insulating filling structure 400 filled therebetween are interconnected, and the orthographic projection of the second organic structures 621 on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10.

[0219] In an exemplary embodiment, Figures 9 to 13As shown, the organic light-emitting layer 631 in the third region R3 extends to portions of the sidewalls of the second isolation portion of the first isolation column 310 farthest from the display area AA and portions of the sidewalls of the second isolation portion of the second isolation column 320 closest to the display area AA. The orthographic projection of the cathode layer 632 in the third region R3 on the substrate 10 covers the orthographic projection of the isolation dam 510 on the substrate 10 and covers the orthographic projection of the organic light-emitting layer in the third region R3 on the substrate 10. In an exemplary embodiment, the second isolation portions of the plurality of isolation columns on the side of the second insulating filling structure in the second region away from the display area are electrically connected to the plurality of second cathode structures. The second isolation portions of the plurality of isolation columns on the side of the second insulating filling structure in the second region closer to the display area, the cathode layer in the third region, and the second isolation portions of the plurality of isolation columns on the side of the first insulating filling structure in the first region away from the display area are electrically connected to each other. The second isolation portions of the plurality of isolation columns on the side of the first insulating filling structure in the first region closer to the display area are electrically connected to the plurality of first cathode structures. The insulating filling structure cuts off the electrical connection between the first region and the second region, thereby achieving power disconnection in the border region.

[0220] In an exemplary embodiment, Figures 9 to 13 As shown, at least one isolation dam 510 includes: a plurality of dam bases stacked in sequence in a direction away from the substrate 10, at least one dam base is located in at least one flat layer, and at least one dam base is located in a pixel definition layer.

[0221] Figures 9 to 13 The isolation dam 510 includes three dam bases 511 to 513 for illustration, wherein the dam base 513 can be located in the pixel definition layer, the dam base 511 can be located in one of the flat layers, and the dam base 512 can be located in another flat layer. The present disclosure does not impose any limitation on this.

[0222] Figure 14 A partial structural diagram of the first area and the second area provided in an embodiment of the present disclosure. Figure 14 , only two isolation columns with an insulating filling structure are shown. Figure 14 As shown, the isolation column 300 is arranged on the side of the composite insulating layer 20 away from the substrate 10, and at least one isolation column 300 includes: L conductive structures 31 and L insulating structures 32 arranged in a stacked manner, the L conductive structures 31 and the L insulating structures 32 are alternately arranged, the lth insulating structure 32 is located on the side of the lth conductive structure 31 away from the substrate 10, and L is a positive integer greater than or equal to 1.

[0223] In an exemplary embodiment, the sidewall of at least one of the conductive structures is groove-shaped, and the edge of the sidewall is a smooth curve. Exemplarily, the longitudinal section of at least one of the conductive structures may be I-shaped.

[0224] In an exemplary embodiment, when L is greater than or equal to 2, the orthographic projection of the surface of the lth conductive structure close to the substrate on the substrate is within the range of the orthographic projection of the surface of the l-1th insulating structure away from the substrate on the substrate, and the maximum distance between the side wall of the lth conductive structure and the center line of the isolation column is less than the minimum distance between the side wall of the l-1th insulating structure and the center line of the isolation column, and the insulating structure 32 arranged on the side of the conductive structure 31 close to the substrate 10 can be an eaves structure.

[0225] In an exemplary embodiment, the shape of the longitudinal section of the insulation structure 32 may be trapezoidal.

[0226] A(B) in the following figures means that structure A is located in film layer B.

[0227] In an exemplary embodiment, a display substrate includes: a base and a circuit structure layer disposed on the base, the circuit structure layer including: K gate metal layers and M source / drain metal layers disposed on the base, wherein the k+1th gate metal layer is located on a side of the kth gate metal layer away from the base, the kth gate metal layer is located on a side of the first source / drain metal layer closer to the base, and the m+1th source / drain metal layer is located on a side of the mth source / drain metal layer away from the base, where K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1. The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, with at least one insulating layer disposed between adjacent gate metal layers, between adjacent source / drain metal layers, and between the kth gate metal layer and the first source / drain metal layer.

[0228] In an exemplary embodiment, the isolation column includes: a first conductive structure and a first insulating structure, the first conductive structure is located in one of the K gate metal layers and the M source and drain metal layers, and the first insulating structure is located in one of the multiple inorganic insulating layers.

[0229] In an exemplary embodiment, the isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, and a second insulating structure. At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and the M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multiple inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

[0230] In an exemplary embodiment, the isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, and a third insulating structure. The first conductive structure, the second conductive structure, and the third conductive structure are located in three of the K gate metal layers and the M source / drain metal layers, and the first conductive structure, the second conductive structure, and the third conductive structure are located in different layers; the first insulating structure, the second insulating structure, and the third insulating structure are located in three of the multiple inorganic insulating layers, and the first insulating structure, the second insulating structure, and the third insulating structure are located in different layers.

[0231] Figure 15 for Figure 14 Schematic diagram of the provided film layers Figure 1 , Figure 15 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 15 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10; or, when the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 can be located in the first gate metal layer, the first insulating structure 312 can be located in the third insulating layer 103, and the composite insulating layer 20 can include: the first insulating layer 101 and the second insulating layer 102.

[0232] Figure 16 for Figure 14 Schematic diagram of the provided film layers Figure 2 , Figure 16 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 16 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fifth insulating layer 105, and the composite insulating layer includes: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0233] Figure 17 for Figure 14 Schematic diagram of the provided film layers Figure 3 , Figure 16 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 16 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 can be located in the second gate metal layer, the first insulating structure 312 can be located in the fourth insulating layer 104, and the composite insulating layer may include: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0234] Figure 18 for Figure 14 Schematic diagram of the provided film layers Figure 4 , Figure 18 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 18 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 can be located in the first source-drain metal layer, the first insulating structure 312 can be located in the sixth insulating layer 106, and the composite insulating layer 20 can include: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103 and a fifth insulating layer 105.

[0235] Figure 19 for Figure 14 Schematic diagram of the provided film layers Figure 5 , Figure 19 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 19 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 can be located in the first source-drain metal layer, the first insulating structure 312 can be located in the sixth insulating layer 106, and the composite insulating layer 20 can include: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104 and a fifth insulating layer 105.

[0236] Figure 20 for Figure 14 Schematic diagram of the provided film layers Figure 6, Figure 20 The description is made by taking the example that the isolation column includes: a first conductive structure 311 and a first insulating structure 312. Figure 20 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 can be located in the third gate metal layer, the first insulating structure 312 can be located in the fifth insulating layer 105, and the composite insulating layer 20 can include: a first insulating layer 101, a second insulating layer 102, a third insulating layer 103 and a fourth insulating layer 104.

[0237] In an exemplary embodiment, Figures 15 to 20 As shown, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10 .

[0238] In an exemplary embodiment, Figures 15 to 20 As shown, the display substrate further includes: a first covering structure 611 and a second covering structure 612 arranged at intervals. The first covering structure 611 is arranged on a side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20. The second covering structure is arranged on a side of the isolation pillar 300 away from the substrate 10. The second covering structures arranged on two isolation pillars 300 with the insulating filling structure 400 filled therebetween are interconnected, and their orthographic projections on the substrate 10 cover the orthographic projections of the insulating filling structure 400 on the substrate 10.

[0239] Figure 21 for Figure 14 Schematic diagram of the provided film layers Figure 7 , Figure 21 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 21 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 can be located in the first gate metal layer, the first insulating structure 312 can be located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, and the composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0240] Figure 22 for Figure 14Schematic diagram of the provided film layers Figure 8 , Figure 22 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 22 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 includes: a first sub-insulating structure 3121 and a second sub-insulating structure 3122, the first sub-insulating structure 3121 is located in the third insulating layer 103, the second sub-insulating structure 3122 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source-drain metal layer, the second insulating structure 314 is located in the sixth insulating layer 106, and the composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0241] Figure 23 for Figure 14 Schematic diagram of the provided film layers Figure 9 , Figure 23 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 23 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source-drain metal layer, the second insulating structure 314 is located in the sixth insulating layer 106, and the composite insulating layer includes: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0242] Figure 24 for Figure 14 Schematic diagram of the provided film layers Figure 10 , Figure 24 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 24As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fourth insulating layer 104, and the composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0243] Figure 25 for Figure 14 Schematic diagram of the provided film layers Figure 10 one, Figure 25 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 25 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 includes: a first sub-insulating structure 3121 and a second sub-insulating structure 3122, the first sub-insulating structure 3121 is located in the third insulating layer 103, the second sub-insulating structure 3122 is located in the fourth insulating layer 104, the second conductive structure 313 is located in the third gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, and the composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0244] Figure 26 for Figure 14 Schematic diagram of the provided film layers Figure 10 two, Figure 26 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 26As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 includes: a first sub-insulating structure 3121, a second sub-insulating structure 3122 and a third sub-insulating structure 3123. The first sub-insulating structure 3121 is located in the third insulating layer 103, the second sub-insulating structure 3122 is located in the fourth insulating layer 104, and the third sub-insulating structure 3123 is located in the fifth insulating layer 105. The second conductive structure 313 is located in the first source-drain metal layer, and the second insulating structure 314 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0245] Figure 27 for Figure 14 Schematic diagram of the provided film layers Figure 10 three, Figure 27 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 27 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fourth insulating layer 104, the second conductive structure 313 is located in the third gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, and the composite insulating layer includes: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0246] Figure 28 for Figure 14 Schematic diagram of the provided film layers Figure 10 Four, Figure 28 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 28As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 includes: a first sub-insulating structure and a second sub-insulating structure, the first sub-insulating structure is located in the fourth insulating layer 104, the second sub-insulating structure is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source-drain metal layer, the second insulating structure 314 is located in the sixth insulating layer 106, and the composite insulating layer includes: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0247] Figure 29 for Figure 14 Schematic diagram of the provided film layers Figure 10 five, Figure 29 The description is made by taking the example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313 and a second insulating structure 314. Figure 29 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the third gate metal layer, the first insulating structure 312 is located in the fifth insulating layer 105, the second conductive structure 313 is located in the first source-drain metal layer, the second insulating structure 314 is located in the sixth insulating layer 106, and the composite insulating layer includes: the first insulating layer 101, the second insulating layer 102, the third insulating layer 103 and the fourth insulating layer 104.

[0248] In an exemplary embodiment, Figures 21 to 29 As shown, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, and the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10.

[0249] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes: a first surface, a second surface and a third surface, the first surface and the third surface are respectively located on both sides of the second surface, the orthographic projection of the second surface on the substrate 10 coincides with the orthographic projection of the second conductive structure 313 on the substrate 10, for two isolation columns filled with an insulating filling structure therebetween, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure, that is, the second surface is the covered surface of the first insulating structure 312 away from the substrate 10, and the first surface and the third surface are the uncovered surfaces of the first insulating structure 312 away from the substrate 10.

[0250] In an exemplary embodiment, Figures 21 to 29 As shown, the display substrate further includes: a first covering structure 621, a second covering structure 622 and a third covering structure 623 arranged at intervals. The first covering structure 621 is arranged on a side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20.

[0251] In an exemplary embodiment, Figures 21 to 29 As shown, the second covering structure 622 is arranged on the side of the isolation column 300 away from the substrate 10, and the second covering structures 622 arranged on the two isolation columns 300 filled with the insulating filling structure 400 are connected to each other, and the orthographic projection on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10.

[0252] In an exemplary embodiment, Figures 21 to 29 As shown, the third covering structure 623 is arranged on the first surface of the first insulating structure 312 of two isolation columns 300 with an insulating filling structure 400 filled therebetween and on the side away from the substrate 10 of the first surface and the third surface of the first insulating structure 312 of two isolation columns 300 without an insulating filling structure 400 therebetween.

[0253] Figure 30 for Figure 14 Schematic diagram of the provided film layers Figure 10 six, Figure 30 The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315 and a third insulating structure 316. Figure 30As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10, the first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, the third conductive structure 315 is located in the first source-drain metal layer, the third insulating structure 316 is located in the sixth insulating layer 106, and the composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0254] Figure 31 for Figure 14 Schematic diagram of the provided film layers Figure 10 seven, Figure 31 The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315 and a third insulating structure 316. Figure 31 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fourth insulating layer 104, the third conductive structure 315 is located in the third gate metal layer, and the third insulating structure 316 is located in the fifth insulating layer 105. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0255] Figure 32 for Figure 14 Schematic diagram of the provided film layers Figure 10 eight, Figure 32 The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315 and a third insulating structure 316. Figure 32As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 includes a first sub-insulating structure 3141 and a second sub-insulating structure 3142, the first sub-insulating structure is located in the fourth insulating layer 104, the second sub-insulating structure is located in the fifth insulating layer 105, the third conductive structure 315 is located in the first source-drain metal layer, and the third insulating structure 316 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0256] Figure 33 for Figure 14 Schematic diagram of the provided film layers Figure 10 Nine, Figure 33 The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315 and a third insulating structure 316. Figure 33 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source / drain metal layer, and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 includes a first sub-insulating structure 3121 and a second sub-insulating structure 3122, the first sub-insulating structure 3121 is located in the third insulating layer 103, the second sub-insulating structure 3122 is located in the fourth insulating layer 104, the second conductive structure 313 is located in the third gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, the third conductive structure 315 is located in the first source / drain metal layer, and the third insulating structure 316 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0257] Figure 34 for Figure 14 Schematic diagram of the provided film layers Figure 2 ten, Figure 34 The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315 and a third insulating structure 316. Figure 34As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the second gate metal layer, the first insulating structure 312 is located in the fourth insulating layer 104, the second conductive structure 313 is located in the third gate metal layer, the second insulating structure 314 is located in the fifth insulating layer 105, the third conductive structure 315 is located in the first source-drain metal layer, and the third insulating structure 316 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103.

[0258] In an exemplary embodiment, Figures 30 to 34 As shown, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10, the orthographic projection of the second insulating structure 314 on the substrate 10 covers the orthographic projection of the third conductive structure 315 on the substrate 10, and the orthographic projection of the third conductive structure 315 on the substrate 10 covers the orthographic projection of the third insulating structure 316 on the substrate 10.

[0259] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes: a first surface, a second surface and a third surface, the first surface and the third surface are respectively located on both sides of the second surface, the orthographic projection of the second surface on the substrate 10 coincides with the orthographic projection of the second conductive structure 313 on the substrate 10, for two isolation columns filled with an insulating filling structure therebetween, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure, that is, the second surface is the covered surface of the first insulating structure 312 away from the substrate 10, and the first surface and the third surface are the uncovered surfaces of the first insulating structure 312 away from the substrate 10.

[0260] In an exemplary embodiment, the surface of the second insulating structure 314 away from the substrate 10 includes: a fourth surface, a fifth surface and a sixth surface, the fourth surface and the sixth surface are respectively located on both sides of the fifth surface, the orthographic projection of the fifth surface on the substrate 10 coincides with the orthographic projection of the third conductive structure 315 on the substrate 10, for two isolation columns filled with an insulating filling structure therebetween, the fourth surface is located on the side of the fifth surface away from the insulating filling structure, and the sixth surface is located on the side of the fifth surface close to the insulating filling structure, that is, the fourth surface is the covered surface of the second insulating structure 314 away from the substrate 10, and the fifth surface and the sixth surface are the uncovered surfaces of the second insulating structure 314 away from the substrate 10.

[0261] In an exemplary embodiment, Figures 30 to 34 As shown, the display substrate further includes: a first covering structure 631 , a second covering structure 632 , a third covering structure 633 and a fourth covering structure 634 that are spaced apart.

[0262] In an exemplary embodiment, Figures 30 to 34 As shown, the first covering structure 631 is disposed on a side of the composite insulating layer 20 away from the substrate 10 and is in direct contact with the composite insulating layer 20 .

[0263] In an exemplary embodiment, Figures 30 to 34 As shown, the second covering structure 632 is arranged on the side of the isolation column 300 away from the substrate 10, and the second covering structures 632 arranged on the two isolation columns 300 filled with the insulating filling structure 400 are connected to each other, and the orthographic projection on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10.

[0264] In an exemplary embodiment, Figures 30 to 34 As shown, the third covering structure 633 is arranged on the first surface of the first insulating structure 312 of the two isolation columns 300 with the insulating filling structure 400 filled therebetween, and the first surface and the third surface of the first insulating structure 312 of the two isolation columns 300 without the insulating filling structure 400 arranged therebetween are away from the substrate 10, and the fourth covering structure 634 is arranged on the fourth surface of the second insulating structure 314 of the two isolation columns 300 with the insulating filling structure 400 filled therebetween, and the fourth surface and the sixth surface of the second insulating structure 314 of the two isolation columns 300 without the insulating filling structure 400 arranged therebetween are away from the substrate 10.

[0265] Figure 35 for Figure 14 Schematic diagram of the provided film layers Figure 2 eleven, Figure 35The description is made by taking an example that the isolation column includes: a first conductive structure 311, a first insulating structure 312, a second conductive structure 313, a second insulating structure 314, a third conductive structure 315, a third insulating structure 316, a fourth conductive structure 317 and a fourth insulating structure 318. Figure 35 As shown, the display substrate includes: a base 10 and a first insulating layer 101, a semiconductor layer, a second insulating layer 102, a first gate metal layer, a third insulating layer 103, a second gate metal layer, a fourth insulating layer 104, a third gate metal layer, a fifth insulating layer 105, a first source-drain metal layer and a sixth insulating layer 106 arranged on the base 10. The first conductive structure 311 is located in the first gate metal layer, the first insulating structure 312 is located in the third insulating layer 103, the second conductive structure 313 is located in the second gate metal layer, the second insulating structure 314 is located in the fourth insulating layer 104, the third conductive structure 315 is located in the third gate metal layer, the third insulating structure 316 is located in the fifth insulating layer 105, the fourth conductive structure 317 is located in the first source-drain metal layer, and the fourth insulating structure 318 is located in the sixth insulating layer 106. The composite insulating layer includes: the first insulating layer 101 and the second insulating layer 102.

[0266] In an exemplary embodiment, Figure 35 As shown, the orthographic projection of the first conductive structure 311 on the substrate 10 covers the orthographic projection of the first insulating structure 312 on the substrate 10, the orthographic projection of the first insulating structure 312 on the substrate 10 covers the orthographic projection of the second conductive structure 313 on the substrate 10, the orthographic projection of the second conductive structure 313 on the substrate 10 covers the orthographic projection of the second insulating structure 314 on the substrate 10, the orthographic projection of the second insulating structure 314 on the substrate 10 covers the orthographic projection of the third conductive structure 315 on the substrate 10, the orthographic projection of the third conductive structure 315 on the substrate 10 covers the orthographic projection of the third insulating structure 316 on the substrate 10, the orthographic projection of the third insulating structure 316 on the substrate 10 covers the orthographic projection of the fourth conductive structure 317 on the substrate 10, and the orthographic projection of the fourth conductive structure 317 on the substrate 10 covers the orthographic projection of the fourth insulating structure 318 on the substrate 10.

[0267] In an exemplary embodiment, the surface of the first insulating structure 312 away from the substrate 10 includes: a first surface, a second surface and a third surface, the first surface and the third surface are respectively located on both sides of the second surface, the orthographic projection of the second surface on the substrate 10 coincides with the orthographic projection of the second conductive structure 313 on the substrate 10, and for two isolation columns filled with an insulating filling structure therebetween, the first surface is located on the side of the second surface away from the insulating filling structure, and the third surface is located on the side of the second surface close to the insulating filling structure.

[0268] In an exemplary embodiment, the surface of the second insulating structure 314 away from the substrate 10 includes: a fourth surface, a fifth surface and a sixth surface, the fourth surface and the sixth surface are respectively located on both sides of the fifth surface, the orthographic projection of the fifth surface on the substrate 10 coincides with the orthographic projection of the third conductive structure 315 on the substrate 10, and for two isolation columns filled with an insulating filling structure therebetween, the fourth surface is located on the side of the fifth surface away from the insulating filling structure, and the sixth surface is located on the side of the fifth surface close to the insulating filling structure.

[0269] In an exemplary embodiment, the surface of the third insulating structure 316 away from the substrate 10 includes: a seventh surface, an eighth surface and a ninth surface, the seventh surface and the ninth surface are respectively located on both sides of the eighth surface, the orthographic projection of the eighth surface on the substrate 10 coincides with the orthographic projection of the fourth conductive structure 317 on the substrate 10, and for two isolation columns filled with an insulating filling structure therebetween, the seventh surface is located on the side of the eighth surface away from the insulating filling structure, and the ninth surface is located on the side of the eighth surface close to the insulating filling structure.

[0270] In an exemplary embodiment, Figure 35 The display substrate further includes: a first covering structure 641 , a second covering structure 642 , a third covering structure 643 , a fourth covering structure 644 and a fifth covering structure 645 , which are spaced apart from each other.

[0271] The first covering structure 641 is arranged on the side of the composite insulating layer away from the substrate 10 and is in direct contact with the composite insulating layer. The second covering structure 642 is arranged on the side of the isolation column 300 away from the substrate 10. The second covering structures 642 arranged on the two isolation columns 300 with the insulating filling structure 400 filled therebetween are interconnected, and the orthographic projection of the second covering structure 642 on the substrate 10 covers the orthographic projection of the insulating filling structure 400 on the substrate 10. The third covering structure 643 is arranged on the first surface of the first insulating structure 312 of the two isolation columns 300 with the insulating filling structure 400 filled therebetween and on the first surface of the first insulating structure 312 of the two isolation columns 300 without the insulating filling structure 400 provided therebetween. The first surface and the third surface are on a side away from the substrate 10, the fourth covering structure 644 is arranged on the fourth surface of the second insulating structure 314 of the two isolation columns 300 with the insulating filling structure 400 filled therebetween, and the fourth surface and the sixth surface of the second insulating structure 314 of the two isolation columns 300 without the insulating filling structure 400 arranged therebetween are away from the substrate 10, and the fifth covering structure 645 is arranged on the seventh surface of the third insulating structure 316 of the two isolation columns 300 with the insulating filling structure 400 filled therebetween, and the seventh surface and the ninth surface of the third insulating structure 316 of the two isolation columns 300 without the insulating filling structure 400 arranged therebetween are away from the substrate 10.

[0272] In an exemplary embodiment, at least one of the first to fifth covering structures includes: an organic structure and a cathode structure, wherein the orthographic projection of the cathode structure on the substrate coincides with the orthographic projection of the organic structure on the substrate; the organic structure is located in the organic light-emitting layer, and the cathode structure is located in the cathode layer.

[0273] In an exemplary embodiment, Figures 15 to 20 Cut off the power supply at the isolation column. Figures 21 to 29 Perform secondary disconnection at the isolation column position. Figures 30 to 34 Make three disconnections at the isolation column position. Figure 35 Make four disconnections at the isolation column position. Figures 15 to 35 The provided display substrate is disconnected at least once at the position of the isolation column, which can effectively solve the technical problem of poor black spots on the display substrate caused by conductivity in the frame area and improve the display effect of the display substrate.

[0274] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0275] Below through Figure 9 and Figure 13 The manufacturing process of the provided display substrate further illustrates the display substrate provided by the embodiment of the present disclosure.

[0276] (1) Forming a composite insulating layer. In an exemplary embodiment, forming a composite insulating layer includes: sequentially forming a plurality of insulating layers on a substrate, thereby forming a composite insulating layer 20. Figure 36 As shown, Figure 36 Schematic diagram after the composite insulation layer is formed.

[0277] In an exemplary embodiment, the composite insulating layer 20 covers the substrate and is located in the display area and the frame area. For example, the composite insulating layer may include an inorganic insulating layer located on the side of the top source / drain metal layer closer to the substrate, and may include, for example, at least one of the first to sixth insulating layers.

[0278] In an exemplary embodiment, when at least one isolation column includes: at least one isolation structure from the second isolation structure to the K+1th isolation structure, forming a composite insulating layer also includes: forming a composite insulating layer and at least one isolation column: at least one isolation structure from the second isolation structure to the K+1th isolation structure.

[0279] (2) Forming a first isolation structure of at least one isolation column. In an exemplary embodiment, forming a first isolation structure of at least one isolation column includes: depositing a metal film on the composite insulating layer, patterning the metal film through a patterning process, and forming a first isolation structure 310 of at least one isolation column located in the border area. Figure 37 As shown, Figure 37 It is a schematic diagram after forming the first isolation structure.

[0280] In an exemplary embodiment, this step further includes: patterning the metal film through a patterning process to form at least one signal line located in the display area, such as a first power line or a data signal line.

[0281] (3) Forming an insulating filling structure and an isolation dam. In an exemplary embodiment, forming the insulating filling structure includes: forming an insulating filling structure 400 and an isolation dam 510 located between at least two adjacent isolation pillars in the frame area on the composite insulating layer through a patterning process. Figure 38 As shown, Figure 38 Schematic diagram after forming the insulating filling structure.

[0282] In an exemplary embodiment, the first insulating filling structure and the second insulating filling structure may be formed sequentially or simultaneously, and the present disclosure does not impose any limitation thereto.

[0283] In an exemplary embodiment, when the first insulating filling structure is located in the Nth planar layer, the first insulating structure and at least one dam base of at least one isolation dam are formed at the same time; when the first insulating filling structure is located in the pixel definition layer, the first insulating structure and the topmost dam base of at least one isolation dam are formed at the same time.

[0284] under Figures 15 to 20 The preparation process of the provided display substrate further illustrates the embodiments of the present disclosure. Figures 15 to 20 The isolation column in the provided display substrate includes a first conductive structure and a first insulating structure.

[0285] (1) Forming a first isolation insulating layer. Forming the first isolation insulating layer includes: forming a composite insulating layer on a substrate, depositing a metal film on the composite insulating layer, patterning the metal film through a patterning process to form a first original conductive structure 3110, and coating an insulating film on the first original conductive structure to form a first isolation insulating layer 3120. Figure 39 As shown, Figure 39 for Figures 15 to 20 Schematic diagram after forming the first isolation insulating layer.

[0286] In an exemplary embodiment, the sidewalls of the first original conductive structure are straight lines.

[0287] In an exemplary embodiment, the composite insulating layer is all inorganic insulating layers located in the film layer where the first original conductive structure is located and close to the substrate. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes the first insulating layer and the second insulating layer. When the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer, and so on.

[0288] (2) Forming a first insulating structure. Forming the first insulating structure includes: etching the first isolation insulating layer 3120 using a mask to form a first insulating structure 312. Figure 40 As shown, Figure 40 for Figures 15 to 20 Schematic diagram after forming the first insulating structure.

[0289] In an exemplary embodiment, the mask is provided with a via exposing the first isolation insulating layer, and the orthographic projection of the via on the substrate is located within the range of the orthographic projection of the first original conductive structure on the substrate, and the width of the via is smaller than the width of the first original conductive structure, wherein the width is the length extending in a direction parallel to the substrate.

[0290] In an exemplary embodiment, the first insulating structure may be formed after forming the top source / drain metal layer and before forming the first electrode of the light emitting element, which is not limited in the present disclosure.

[0291] (3) Forming a first conductive structure. Forming the first conductive structure includes: etching the first original conductive structure to form a first conductive structure 311. Figure 41 As shown, Figure 41 for Figures 15 to 20 Schematic diagram after forming the first conductive structure.

[0292] In an exemplary embodiment, the sidewall of the first conductive structure 311 is groove-shaped.

[0293] In example embodiments, the first conductive structure 311 may be formed after the first electrode of the light emitting element.

[0294] (4) Forming an insulating filling structure. Forming an insulating filling structure includes: depositing an insulating filling film, patterning the insulating filling film through a patterning process, and forming an insulating filling structure 400. Figure 42 As shown, Figure 42 for Figures 15 to 20 Schematic diagram after forming the insulating filling structure.

[0295] In exemplary embodiments, the insulating filling film may be the same film as a film forming a top planarization layer, or the same film as a film forming a pixel definition layer.

[0296] (5) Forming multiple covering structures. Forming multiple covering structures includes: depositing an organic material layer and a cathode conductive layer, and forming a covering structure including an organic structure and a cathode structure through a patterning process. Figure 43 As shown, Figure 43 for Figures 15 to 20 Schematic diagram after forming multiple covering structures.

[0297] In an exemplary embodiment, the plurality of cover structures includes a first cover structure 611 and a second cover structure 612 .

[0298] under Figures 21 to 29 The preparation process of the provided display substrate further illustrates the embodiments of the present disclosure. Figures 20 to 29 The isolation column in the provided display substrate includes: a first conductive structure, a first insulating structure, a second conductive structure and a second insulating structure.

[0299] (1) Forming a second isolation insulating layer. The formation of the second isolation insulating layer includes: forming a composite insulating layer on a substrate, depositing a first metal film on the composite insulating layer, patterning the first metal film through a patterning process to form a first original conductive structure 3110, coating a first insulating film on the first original conductive structure to form a first isolation insulating layer 3120, depositing a second metal film on the first isolation insulating layer, patterning the second metal film through a patterning process to form a second original conductive structure 3130, and coating a second insulating film on the second original conductive structure to form a second isolation insulating layer 3140. Figure 44 As shown, Figure 44 for Figures 21 to 29 Schematic diagram after forming the second isolation insulating layer.

[0300] In an exemplary embodiment, sidewalls of the first and second original conductive structures are straight lines.

[0301] In an exemplary embodiment, the composite insulating layer is all inorganic insulating layers located in the film layer where the first original conductive structure is located and close to the substrate. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes the first insulating layer and the second insulating layer. When the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer, and so on.

[0302] In an exemplary embodiment, the first isolating insulating layer may be a single-layer structure or a multi-layer structure, and the second isolating insulating layer may be a single-layer structure. The structure of the first isolating insulating layer depends on the film layer in which the first original conductive structure and the second original conductive structure are located. For example, when the film layer in which the first original conductive structure and the film layer in which the second original conductive structure are located are located in adjacent metal layers, the first isolating insulating layer may be a single-layer structure. When another metal layer is provided between the film layer in which the first original conductive structure and the film layer in which the second original conductive structure are located, the first isolating insulating layer may be a multi-layer structure.

[0303] (2) Forming the first insulating structure and the second insulating structure. Forming the first insulating structure and the second insulating structure includes: etching the first insulating layer and the second insulating layer using a mask to form the first insulating structure 312 and the second insulating structure 314. Figure 45 As shown, Figure 45 for Figures 21 to 29 Schematic diagram after the first insulating structure and the second insulating structure are formed.

[0304] In an exemplary embodiment, the mask is provided with a via exposing the second isolation insulating layer, and the orthographic projection of the via on the substrate is located within the range of the orthographic projection of the second original conductive structure on the substrate, and the width of the via is smaller than the width of the second original conductive structure, wherein the width is the length extending in a direction parallel to the substrate.

[0305] In an exemplary embodiment, the first insulating structure and the second insulating structure may be formed after forming the top source / drain metal layer and before forming the first electrode of the light emitting element, which is not limited in the present disclosure.

[0306] (3) Forming the first conductive structure and the second conductive structure. Forming the first conductive structure and the second conductive structure includes: etching the first original conductive structure and the second original conductive structure to form the first conductive structure 311 and the second conductive structure 313. Figure 46 As shown, Figure 46 for Figures 20 to 29 Schematic diagram after forming the first conductive structure and the second conductive structure.

[0307] In an exemplary embodiment, the sidewalls of the first conductive structure 311 and the second conductive structure 313 are groove-shaped.

[0308] In example embodiments, the first conductive structure 311 and the second conductive structure 313 may be formed after the first electrode of the light emitting element.

[0309] (4) Forming an insulating filling structure. Forming an insulating filling structure includes: depositing an insulating filling film, patterning the insulating filling film through a patterning process, and forming an insulating filling structure 400. Figure 47 As shown, Figure 47 for Figures 21 to 29 Schematic diagram after forming the insulating filling structure.

[0310] In exemplary embodiments, the insulating filling film may be the same film as a film forming a top planarization layer, or the same film as a film forming a pixel definition layer.

[0311] (5) Forming multiple covering structures. Forming multiple covering structures includes: depositing an organic material layer and a cathode conductive layer, and forming a covering structure including an organic structure and a cathode structure through a patterning process. Figure 48 As shown, Figure 48 for Figures 21 to 29 Schematic diagram after forming multiple covering structures.

[0312] In an exemplary embodiment, the plurality of cover structures include a first cover structure 621 , a second cover structure 622 , and a third cover structure 623 .

[0313] under Figures 30 to 34The preparation process of the provided display substrate further illustrates the embodiments of the present disclosure. Figures 30 to 34 The isolation column in the provided display substrate includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure and a third insulating structure.

[0314] (1) Forming a third isolation insulating layer. Forming the third isolation insulating layer includes: forming a composite insulating layer on a substrate, depositing a first metal film on the composite insulating layer, patterning the first metal film through a patterning process to form a first original conductive structure 3110, coating a first insulating film on the first original conductive structure to form a first isolation insulating layer 3120, depositing a second metal film on the first isolation insulating layer, patterning the second metal film through a patterning process to form a second original conductive structure 3130, coating a second insulating film on the second original conductive structure to form a second isolation insulating layer 3140, depositing a third metal film on the second isolation insulating layer, patterning the third metal film through a patterning process to form a third original conductive structure 3150, coating a third insulating film on the third original conductive structure to form a third isolation insulating layer 3160. Figure 49 As shown, Figure 49 for Figures 30 to 34 Schematic diagram after forming the third isolation insulating layer.

[0315] In an exemplary embodiment, sidewalls of the first original conductive structure, the second original conductive structure, and the third original conductive structure are straight lines.

[0316] In an exemplary embodiment, the composite insulating layer is all inorganic insulating layers located in the film layer where the first original conductive structure is located and close to the substrate. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes the first insulating layer and the second insulating layer. When the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer, and so on.

[0317] In an exemplary embodiment, the first isolating insulating layer and the second isolating insulating layer may be a single-layer structure, or may be a multi-layer structure, and the third isolating insulating layer is a single-layer structure. The structure of the first isolating insulating layer depends on the film layer where the first original conductive structure and the second original conductive structure are located. For example, when the film layer where the first original conductive structure and the film layer where the second original conductive structure are located are located in adjacent metal layers, the first isolating insulating layer is a single-layer structure. When other metal layers are provided between the film layer where the first original conductive structure and the film layer where the second original conductive structure are located, the first isolating insulating layer is a multi-layer structure. The structure of the second isolating insulating layer depends on the film layer where the second original conductive structure and the third original conductive structure are located. For example, when the film layer where the second original conductive structure and the film layer where the third original conductive structure are located are located in adjacent metal layers, the second isolating insulating layer is a single-layer structure. When other metal layers are provided between the film layer where the second original conductive structure and the film layer where the third original conductive structure are located, the second isolating insulating layer is a multi-layer structure.

[0318] (2) Forming the first insulating structure, the second insulating structure and the third insulating structure. Forming the first insulating structure, the second insulating structure and the third insulating structure includes: etching the first insulating layer, the second insulating layer and the third insulating layer using a mask to form the first insulating structure 312, the second insulating structure 314 and the third insulating structure 316. Figure 50 As shown, Figure 50 for Figures 30 to 34 Schematic diagram after forming the first insulating structure, the second insulating structure and the third insulating structure.

[0319] In an exemplary embodiment, the mask is provided with a via exposing the third isolation insulating layer, and the orthographic projection of the via on the substrate is located within the range of the orthographic projection of the third original conductive structure on the substrate, and the width of the via is smaller than the width of the third original conductive structure, wherein the width is the length extending in a direction parallel to the substrate.

[0320] In an exemplary embodiment, the first insulating structure, the second insulating structure, and the third insulating structure may be formed after forming the top source / drain metal layer and before forming the first electrode of the light emitting element, which is not limited in the present disclosure.

[0321] (3) Forming the first conductive structure, the second conductive structure and the third conductive structure. Forming the first conductive structure, the second conductive structure and the third conductive structure includes: etching the first original conductive structure, the second original conductive structure and the third original conductive structure to form the first conductive structure 311, the second conductive structure 313 and the third conductive structure 315. Figure 51 As shown, Figure 51 for Figures 30 to 34 Schematic diagram after forming the first conductive structure, the second conductive structure and the third conductive structure.

[0322] In an exemplary embodiment, sidewalls of the first conductive structure 311 , the second conductive structure 313 , and the third conductive structure 315 are groove-shaped.

[0323] In example embodiments, the first conductive structure 311 , the second conductive structure 313 , and the third conductive structure 315 may be formed after the first electrode of the light emitting element.

[0324] (4) Forming an insulating filling structure. Forming an insulating filling structure includes: depositing an insulating filling film, patterning the insulating filling film through a patterning process, and forming an insulating filling structure 400, such as Figure 52 As shown, Figure 52 for Figures 30 to 34 Schematic diagram after forming the insulating filling structure.

[0325] In exemplary embodiments, the insulating filling film may be the same film as a film forming a top planarization layer, or the same film as a film forming a pixel definition layer.

[0326] (5) Forming multiple covering structures. Forming multiple covering structures includes: depositing an organic material layer and a cathode conductive layer, and forming a covering structure including an organic structure and a cathode structure through a patterning process. Figure 53 As shown, Figure 53 for Figures 30 to 34 Schematic diagram after forming multiple covering structures.

[0327] In an exemplary embodiment, the plurality of cover structures include a first cover structure 631 , a second cover structure 632 , a third cover structure 633 , and a fourth cover structure 634 .

[0328] under Figure 35 The preparation process of the provided display substrate further illustrates the embodiments of the present disclosure. Figure 35 The isolation column in the provided display substrate includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure, a third insulating structure, a fourth conductive structure and a fourth insulating structure.

[0329] (1) Forming a third isolation insulating layer. Forming the third isolation insulating layer includes: forming a composite insulating layer on a substrate, depositing a first metal film on the composite insulating layer, patterning the first metal film through a patterning process to form a first original conductive structure 3110, coating the first insulating film on the first original conductive structure to form a first isolation insulating layer 3120, depositing a second metal film on the first isolation insulating layer, patterning the second metal film through a patterning process to form a second original conductive structure 3130, coating the second insulating film on the second original conductive structure to form a second isolation insulating layer 3140, depositing a third metal film on the second isolation insulating layer, patterning the third metal film through a patterning process to form a third original conductive structure 3150, coating the third insulating film on the third original conductive structure to form a third isolation insulating layer 3160, depositing a fourth metal film on the third isolation insulating layer, patterning the fourth metal film through a patterning process to form a fourth original conductive structure 3170, coating the fourth insulating film on the third original conductive structure to form a fourth isolation insulating layer 3180, as shown in FIG. Figure 54 As shown, Figure 54 for Figure 35 Schematic diagram after forming the fourth isolation insulating layer.

[0330] In an exemplary embodiment, sidewalls of the first original conductive structure, the second original conductive structure, the third original conductive structure, and the fourth original conductive structure are straight lines.

[0331] In an exemplary embodiment, the composite insulating layer is all inorganic insulating layers located in the film layer where the first original conductive structure is located and close to the substrate. For example, when the first original conductive structure is located in the first gate metal layer, the composite insulating layer includes the first insulating layer and the second insulating layer. When the first original conductive structure is located in the second gate metal layer, the composite insulating layer includes the first insulating layer, the second insulating layer, and the third insulating layer, and so on.

[0332] In an exemplary embodiment, the first isolating insulating layer, the second isolating insulating layer and the third isolating insulating layer may be a single-layer structure, or may be a multi-layer structure, and the third isolating insulating layer may be a single-layer structure. The structure of the first isolating insulating layer depends on the film layer where the first original conductive structure and the second original conductive structure are located. For example, when the film layer where the first original conductive structure and the film layer where the second original conductive structure are located are located in adjacent metal layers, the first isolating insulating layer may be a single-layer structure. When other metal layers are provided between the film layer where the first original conductive structure and the film layer where the second original conductive structure are located, the first isolating insulating layer may be a multi-layer structure. The structure of the second isolating insulating layer depends on the film layer where the second original conductive structure and the third original conductive structure are located. For example, when the film layer where the second original conductive structure and the film layer where the third original conductive structure are located are located in adjacent metal layers, the second isolating insulating layer may be a single-layer structure. When other metal layers are provided between the film layer where the second original conductive structure and the film layer where the third original conductive structure are located, the second isolating insulating layer may be a multi-layer structure.

[0333] (2) Forming a first insulating structure, a second insulating structure, a third insulating structure, and a fourth insulating structure. Forming the first insulating structure, the second insulating structure, the third insulating structure, and the fourth insulating structure includes: etching the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer using a mask to form a first insulating structure 312, a second insulating structure 314, a third insulating structure 316, and a fourth insulating structure 318. Figure 55 As shown, Figure 55 for Figure 35 Schematic diagram after forming the first insulating structure, the second insulating structure, the third insulating structure and the fourth insulating structure.

[0334] In an exemplary embodiment, the mask is provided with a via exposing the fourth isolation insulating layer, and the orthographic projection of the via on the substrate is located within the range of the orthographic projection of the fourth original conductive structure on the substrate, and the width of the via is smaller than the width of the fourth original conductive structure, wherein the width is the length extending in a direction parallel to the substrate.

[0335] In an exemplary embodiment, the first insulating structure, the second insulating structure, the third insulating structure and the fourth insulating structure may be formed after forming the top source-drain metal layer and before forming the first electrode of the light-emitting element, which is not limited in the present disclosure.

[0336] (3) Forming the first conductive structure, the second conductive structure, and the fourth conductive structure. Forming the first conductive structure, the second conductive structure, and the third conductive structure includes: etching the first original conductive structure, the second original conductive structure, the third original conductive structure, and the fourth original conductive structure to form the first conductive structure 311, the second conductive structure 313, the third conductive structure 315, and the fourth conductive structure 317. Figure 56 As shown, Figure 56 for Figure 35 Schematic diagram after forming the first conductive structure, the second conductive structure, the third conductive structure and the fourth conductive structure.

[0337] In an exemplary embodiment, sidewalls of the first conductive structure 311 , the second conductive structure 313 , the third conductive structure 315 , and the fourth conductive structure 317 are groove-shaped.

[0338] In example embodiments, the first conductive structure 311 , the second conductive structure 313 , the third conductive structure 315 , and the fourth conductive structure 317 may be formed after the first electrode of the light emitting element.

[0339] (4) Forming an insulating filling structure. Forming an insulating filling structure includes: depositing an insulating filling film, patterning the insulating filling film through a patterning process, and forming an insulating filling structure 400, such as Figure 57 As shown, Figure 57 for Figure 35 Schematic diagram after forming the insulating filling structure.

[0340] In exemplary embodiments, the insulating filling film may be the same film as a film forming a top planarization layer, or the same film as a film forming a pixel definition layer.

[0341] (5) Forming multiple covering structures. Forming multiple covering structures includes: depositing an organic material layer and a cathode conductive layer, and forming a covering structure including an organic structure and a cathode structure through a patterning process. Figure 58 As shown, Figure 58 for Figure 35 Schematic diagram after forming multiple covering structures.

[0342] In an exemplary embodiment, the plurality of cover structures include a first cover structure 641 , a second cover structure 642 , a third cover structure 643 , a fourth cover structure 644 , and a fifth cover structure 645 .

[0343] Figure 59 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 59 As shown, this embodiment provides a display device 91, including the display substrate 910 provided by any of the above embodiments.

[0344] In an exemplary embodiment, the display substrate 910 may be an OLED display substrate, such as an OLED display substrate with an integrated touch structure. The display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touch and display functions. In an exemplary embodiment, the display device 91 may be a wearable display device, such as one that can be worn on the human body in some manner. For example, the display device 91 may be a smartwatch, a smart bracelet, or the like. However, this embodiment is not limited to this.

[0345] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0346] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: a display area and a hole area, wherein the display area is arranged around the hole area, and the hole area includes: a first area and a second area arranged in sequence away from the display area; a plurality of isolation columns are provided in the first area and the second area, an insulating filling structure is filled between at least two adjacent isolation columns in the first area and the second area, and at least one insulating filling structure at least partially covers side walls of two adjacent isolation columns close to the insulating filling structure; The thickness of at least one first insulating filling structure is less than the thickness of at least one second insulating filling structure, the first insulating filling structure is arranged between adjacent first isolation columns, the first isolation columns are isolation columns located in the first area, and the second insulating filling structure is arranged between adjacent second isolation columns, the second isolation columns are isolation columns located in the second area.

2. The display substrate according to claim 1, wherein: A ratio of a thickness of the second insulating filling structure to a thickness of the first insulating filling structure is between 1.05 and 3.

85.

3. The display substrate according to claim 1, wherein The second insulating filling structure includes: a second sub-filling structure, or includes: a first sub-filling structure and a second sub-filling structure. When the second insulating filling structure includes: the first sub-filling structure and the second sub-filling structure, the first sub-filling structure is located on a side of the second sub-filling structure close to the display area; The thickness of the first sub-filling structure is smaller than the thickness of the second sub-filling structure.

4. The display substrate according to claim 3, wherein: The thickness of the first insulating filling structure is smaller than the thickness of the second sub-filling structure.

5. The display substrate according to claim 1, wherein The display substrate comprises: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, wherein the light-emitting structure layer comprises: an organic light-emitting layer and a cathode layer, and the organic light-emitting layer and the cathode layer extend from the display area to the second area; The organic light emitting layer and the cathode layer located in the first region or the second region are separated by at least one isolation column located in the first region or the second region; The organic light-emitting layer located in the first region or the second region includes: a first organic structure and a second organic structure spaced apart from each other; the cathode layer located in the first region or the second region includes: a first cathode structure and a second cathode structure spaced apart from each other, the first cathode structure corresponding to the first organic structure in a one-to-one manner, and the second cathode structure corresponding to the second organic structure in a one-to-one manner; The first organic structure is arranged between at least part of adjacent isolation columns and at least partly covers at least part of the side walls of adjacent isolation columns. The second organic structure is arranged on the surface of at least one isolation column away from the substrate. The first cathode structure is arranged between at least part of adjacent isolation columns and at least partly covers the side walls of adjacent isolation columns. The second cathode structure is arranged on the side of the second organic structure away from the substrate. The maximum distance between the surface of at least one second organic structure away from the substrate and the substrate is greater than the maximum distance between the surface of the first cathode structure away from the substrate and the substrate.

6. The display substrate according to claim 5, wherein: The second organic structures arranged on the two isolation columns filled with the insulating filling structure are interconnected, and the orthographic projections on the substrate cover the orthographic projections of the insulating filling structure on the substrate. The second cathode structures arranged on the two isolation columns filled with the insulating filling structure are interconnected, and the orthographic projections on the substrate cover the orthographic projections of the insulating filling structure on the substrate.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate comprises: a base and a circuit structure layer provided on the base, wherein the circuit structure layer comprises: M source / drain metal layers, wherein the (m+1)th source / drain metal layer is located on a side of the (m)th source / drain metal layer away from the base, where M≥2 and 1≤m≤M-1; At least one isolation column among the plurality of isolation columns comprises a first isolation structure, and the first isolation structure of the at least one isolation column among the plurality of isolation columns is located in one of the M source / drain metal layers.

8. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate comprises: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, the light-emitting structure layer comprising: a pixel definition layer, and the circuit structure layer comprising: N planar layers sequentially stacked on the base, the n+1th planar layer being located on a side of the nth planar layer away from the base, 1≤N≤M, 1≤n≤N-1; The first insulating filling structure is located in the Nth planarization layer or the pixel definition layer.

9. The display substrate according to claim 3, wherein: The display substrate comprises: a base, and a circuit structure layer and a light-emitting structure layer sequentially stacked on the base, the light-emitting structure layer comprising: a pixel definition layer, and the circuit structure layer comprising: N planar layers sequentially stacked on the base, the n+1th planar layer being located on a side of the nth planar layer away from the base, 1≤N≤M, 1≤n≤N-1; The first sub-filling structure is located in the Nth planar layer or pixel definition layer.

10. The display substrate according to claim 3, wherein: The display substrate comprises: a base and a light emitting structure layer arranged on the base, wherein the light emitting structure layer comprises: a pixel definition layer and a spacer arranged on the pixel definition layer; The second sub-filling structure is arranged in the same layer as the spacer.

11. The display substrate according to claim 7, wherein: The circuit structure layer further includes: K gate metal layers sequentially stacked on the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate; At least one of the plurality of isolation pillars further comprises: at least one isolation structure from the second isolation structure to the K+1th isolation structure, wherein an orthographic projection of at least one of the second isolation structure to the K+1th isolation structure on the substrate overlaps with an orthographic projection of the first isolation structure; The k+1th isolation structure is located in the kth gate metal layer, 1≤k≤K.

12. The display substrate according to claim 1, wherein The hole area further includes: a third area and a fourth area, the third area is located between the first area and the second area, and the fourth area is located on a side of the second area away from the display area; The third region is provided with at least one isolation dam, and the fourth region is provided with a cutting groove or at least one isolation column.

13. The display substrate according to claim 12, wherein: The display substrate includes: a base and a circuit structure layer disposed on the base, the circuit structure layer further including: a plurality of inorganic insulating layers and a plurality of organic insulating layers; the hole region includes: a composite insulating layer, the composite insulating layer including: a plurality of inorganic insulating layers located on a side of the Mth source / drain metal layer close to the base, the inorganic insulating layer extending from the display region to the fourth region; The cutting groove is arranged in the composite insulating layer.

14. The display substrate according to claim 7, wherein: The first isolation structure of at least one isolation column among the plurality of isolation columns comprises: a first isolation portion, a second isolation portion, and a third isolation portion, wherein the first isolation portion is located on a side of the second isolation portion close to the substrate, and the third isolation portion is located on a side of the second isolation portion away from the substrate; The orthographic projection of the surface of the second isolation portion close to the substrate on the substrate is located within the range of the orthographic projection of the surface of the first isolation portion away from the substrate on the substrate, and the orthographic projection of the surface of the second isolation portion away from the substrate on the substrate is located within the range of the orthographic projection of the surface of the third isolation portion close to the substrate on the substrate.

15. The display substrate according to claim 14, wherein: The first insulating filling structure overlaps with an orthographic projection of the third isolation portion of the first isolation column on the substrate, and the second insulating filling structure overlaps with an orthographic projection of the third isolation portion of the second isolation column on the substrate.

16. The display substrate according to any one of claims 1 to 6, characterized in that: include: A substrate, wherein the isolation column is disposed on the substrate, at least one of the isolation columns comprises: L conductive structures and L insulating structures stacked in a stacked manner, the L conductive structures and the L insulating structures being alternately disposed, the lth insulating structure being located on a side of the lth conductive structure away from the substrate, where L is a positive integer greater than or equal to 1; At least one sidewall of the conductive structure is in a groove shape.

17. The display substrate according to claim 16, wherein: When L is greater than or equal to 2, the orthographic projection of the surface of the lth conductive structure close to the substrate on the substrate is located within the range of the orthographic projection of the surface of the l-1th insulating structure far from the substrate on the substrate, and the maximum distance between the side wall of the lth conductive structure and the center line of the isolation column is less than the minimum distance between the side wall of the l-1th insulating structure and the center line of the isolation column.

18. The display substrate according to claim 16, wherein: The isolation column includes: a first conductive structure and a first insulating structure; The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1; The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; The first conductive structure is located in one of the K gate metal layers and the M source / drain metal layers, and the first insulating structure is located in one of the multiple inorganic insulating layers.

19. The display substrate according to claim 16, wherein: The isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure and a second insulating structure; The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1; The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; At least one of the first conductive structure and the second conductive structure is located in two of the K gate metal layers and the M source / drain metal layers, and the first conductive structure and the second conductive structure are located in different layers; the first insulating structure and the second insulating structure are located in two of the multiple inorganic insulating layers, and the first insulating structure and the second insulating structure are located in different layers.

20. The display substrate according to claim 16, wherein The isolation column includes: a first conductive structure, a first insulating structure, a second conductive structure, a second insulating structure, a third conductive structure and a third insulating structure; The display substrate includes: a substrate and a circuit structure layer provided on the substrate, the circuit structure layer including: K gate metal layers and M source / drain metal layers provided on the substrate, the k+1th gate metal layer being located on a side of the kth gate metal layer away from the substrate, the Kth gate metal layer being located on a side of the first source / drain metal layer close to the substrate, and the m+1th source / drain metal layer being located on a side of the mth source / drain metal layer away from the substrate, K ≥ 2, 1 ≤ k ≤ K-1, M ≥ 2, and 1 ≤ m ≤ M-1; The circuit structure layer further includes: a plurality of inorganic insulating layers and a plurality of organic insulating layers, at least one insulating layer is provided between adjacent gate metal layers, between adjacent source and drain metal layers, and between the Kth gate metal layer and the first source and drain metal layer; The first conductive structure, the second conductive structure and the third conductive structure are located in three of the K gate metal layers and the M source / drain metal layers, and the first conductive structure, the second conductive structure and the third conductive structure are located in different layers; the first insulating structure, the second insulating structure and the third insulating structure are located in three of the multiple inorganic insulating layers, and the first insulating structure, the second insulating structure and the third insulating structure are located in different layers.

21. The display substrate according to claim 12, wherein: The display substrate comprises: a base, and a circuit structure layer and a light emitting structure layer sequentially stacked on the base, wherein the light emitting structure layer comprises: a pixel definition layer, and the circuit structure layer comprises: a plurality of flat layers sequentially stacked on the base; At least one isolation dam includes: a plurality of dam bases stacked in sequence in a direction away from the substrate, at least one of the plurality of dam bases is located on at least one flat layer, and at least one of the plurality of dam bases is located on a pixel definition layer.

22. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 21.

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