Reference signal generation circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a reference signal generating circuit, a chip and electronic equipment, the reference signal generating circuit comprises an operational amplifier module, a mirror image module and a reference signal adjusting module, a current adjusting unit is connected with a voltage feedback unit in parallel, so that the voltage at the two ends of the current adjusting unit is equal to the voltage at the two ends of the voltage feedback unit; therefore, under the condition that the feedback voltage and the reference voltage output by the voltage feedback unit are not changed, the initial current can be adjusted through the current adjusting unit, and then all the reference currents can be synchronously calibrated, so that the reference voltage or the reference current can be independently adjusted; and the calibration efficiency of the reference current is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a reference signal generating circuit, chip, and electronic equipment. Background Art

[0002] A bandgap reference (BGR) circuit generates an output voltage that is independent of the supply voltage and temperature and is widely used in various analog circuits. A bandgap reference circuit adds a voltage that is proportional to absolute temperature to a voltage that is inversely related to absolute temperature, resulting in a temperature-independent output voltage.

[0003] A voltage negatively correlated with absolute temperature is typically created by the base-emitter voltage generated by current flowing through a transistor. A voltage positively correlated with absolute temperature is typically created by subtracting the base-emitter voltages generated by current flowing through two transistors. The output voltage of a bandgap reference circuit is clamped by a unity-gain buffer to generate a corresponding reference voltage. This reference voltage is then divided by the feedback resistor to generate the corresponding reference current.

[0004] However, during the adjustment process, the reference voltage and the reference current change synchronously, which makes it impossible to adjust the reference voltage or the reference current independently, thereby reducing the accuracy of the reference voltage or the reference current. Utility Model Content

[0005] In view of the above problems, embodiments of the present application provide a reference signal generating circuit, chip, and electronic device to solve the technical problem that the reference voltage or reference current cannot be adjusted individually.

[0006] In a first aspect, an embodiment of the present application provides a reference signal generating circuit, which includes an operational amplifier module, a mirror module, and a reference signal adjustment module. The first input terminal of the operational amplifier module is used to access a reference voltage, the second input terminal of the operational amplifier module is used to access a feedback voltage, and the output terminal of the operational amplifier module is used to output an operational amplifier signal; the control terminal of the mirror module is connected to the output terminal of the operational amplifier module, and the mirror module is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror out at least one reference current based on the initial current; the reference signal adjustment module includes a voltage feedback unit and a current adjustment unit, the current adjustment unit is connected in parallel with the voltage feedback unit, and the voltage feedback unit is connected to the operational amplifier module and the mirror module to output a reference voltage based on the initial current.

[0007] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned reference signal generating circuit.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned reference signal generating circuit or chip provided in the device body.

[0009] The reference signal generating circuit, chip and electronic device provided in the embodiments of the present application are connected in parallel with the voltage feedback unit through a current adjustment unit, so that the voltage across the current adjustment unit is equal to the voltage across the voltage feedback unit. Therefore, without changing the feedback voltage and the reference voltage output by the voltage feedback unit, the initial current can be adjusted through the current adjustment unit, and then all reference currents can be synchronously calibrated, which not only realizes the separate adjustment of the reference voltage or the reference current, but also improves the calibration efficiency of the reference current.

[0010] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A first principle block diagram of a reference signal generating circuit provided in an embodiment of the present application is shown.

[0013] Figure 2 Shows the principle block diagram of the mirror module.

[0014] Figure 3 A first circuit principle diagram of the initial current generating branch is shown.

[0015] Figure 4 A second circuit principle diagram of the initial current generating branch is shown.

[0016] Figure 5 FIG. 4 shows a circuit schematic diagram of the mirror current branch.

[0017] Figure 6 A first circuit schematic diagram of a voltage feedback unit is shown.

[0018] Figure 7 A second circuit schematic diagram of the voltage feedback unit is shown.

[0019] Figure 8 FIG. 4 shows a circuit diagram of a current adjustment unit.

[0020] Figure 9 A first circuit schematic diagram of a reference signal generating circuit provided in an embodiment of the present application is shown.

[0021] Figure 10A second circuit schematic diagram of the reference signal generating circuit provided in an embodiment of the present application is shown.

[0022] Figure 11 A third circuit schematic diagram of the reference signal generating circuit provided in an embodiment of the present application is shown.

[0023] Figure 12 A fourth circuit schematic diagram of the reference signal generating circuit provided in an embodiment of the present application is shown.

[0024] Figure 13 A schematic diagram of a chip provided in an embodiment of the present application is shown.

[0025] Figure 14 A schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0027] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0029] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0030] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0031] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0032] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0033] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0034] After a bandgap reference circuit is calibrated, it typically outputs a reference voltage that is independent of the power supply voltage and temperature. When the output reference voltage is required to be greater than or less than the reference voltage, scaling is typically performed using a unity-gain buffer (operational amplifier) and resistor dividers. Changing the divider ratio changes the output reference voltage, and the current flowing through the divider resistors is output as the reference current.

[0035] When a high-precision reference current is required to be output, the reference current needs to be calibrated. Usually, the calibration is performed by adding or reducing multiple current mirror branches in parallel. This method can only calibrate the reference current output of one path at a time. The accuracy of the reference current output of other paths is still not high, and the calibration efficiency of the reference current is also low.

[0036] Based on this, the embodiment of the present application provides a reference signal generating circuit 100, such as Figure 1 As shown, the reference signal generating circuit 100 includes an operational amplifier module 10, a mirror module 20 and a reference signal adjustment module 30. The reference signal adjustment module 30 includes a voltage feedback unit 31 and a current adjustment unit 32. The current adjustment unit 32 is connected in parallel with the voltage feedback unit 31, so that the voltage across the current adjustment unit 32 is equal to the voltage across the voltage feedback unit 31. Therefore, without changing the feedback voltage VFB output by the voltage feedback unit 31 and the reference voltage VREF, the initial current can be adjusted by the current adjustment unit 32, and then all reference currents IREF can be synchronously calibrated, which not only realizes the separate adjustment of the reference voltage VREF or the reference current IREF, but also improves the calibration efficiency of the reference current IREF.

[0037] The present invention provides a reference signal generating circuit 100. Figures 1 to 12 ,like Figure 1 As shown, the reference signal generating circuit 100 includes an operational amplifier module 10, a mirror module 20 and a reference signal adjustment module 30. The first input terminal of the operational amplifier module 10 is used to access the reference voltage VBG, the second input terminal of the operational amplifier module 10 is used to access the feedback voltage VFB, and the output terminal of the operational amplifier module 10 is used to output the corresponding operational amplifier signal; the control terminal of the mirror module 20 is connected to the output terminal of the operational amplifier module 10, and the mirror module 20 is used to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror out at least one reference current IREF of a corresponding proportion according to the initial current; the reference signal adjustment module 30 includes a voltage feedback unit 31 and a current adjustment unit 32. The voltage feedback unit 31 is connected in parallel with the current adjustment unit 32. The voltage feedback unit 31 is connected to the operational amplifier module 10 and the mirror module 20 to output the reference voltage VREF according to the initial current.

[0038] It can be understood that the reference signal generating circuit 100 provided in the embodiment of the present application is connected in parallel with the voltage feedback unit 31 through the current adjustment unit 32, so that the voltage across the current adjustment unit 32 is equal to the voltage across the voltage feedback unit 31. Therefore, without changing the feedback voltage VFB and the reference voltage VREF output by the voltage feedback unit 31, the initial current can be adjusted through the current adjustment unit 32, and then all reference currents IREF can be synchronously calibrated, which not only realizes the separate adjustment of the reference voltage VREF or the reference current IREF, but also improves the calibration efficiency of the reference current IREF.

[0039] It should be noted that the operational amplifier module 10 is used to output a corresponding operational amplifier signal according to the comparison result between the reference voltage VBG and the feedback voltage VFB. The current adjustment unit 32 is used to adjust the initial current to calibrate at least one reference current IREF when the reference voltage VREF remains unchanged.

[0040] Alternatively, as Figure 2 As shown, the mirror module 20 includes an initial current generating branch 21 and a current mirror branch 22. The initial current generating branch 21 is used to generate an initial current; the current mirror branch 22 is connected to the initial current generating branch 21 and is used to mirror at least one reference current according to the initial current.

[0041] It should be noted that the initial current generating branch 21 can be connected to the operational amplifier module 10 to generate an initial current according to the output signal of the operational amplifier module 10, and the current mirror branch 22 can mirror at least one reference current according to the initial current through a current mirror relationship.

[0042] Alternatively, as Figure 3 As shown, the initial current generating branch 21 includes a first transistor M1, the control electrode of the first transistor M1 is connected to the output end of the operational amplifier OP1, the first electrode of the first transistor M1 is connected to the power supply end VDD, and the second electrode of the first transistor M1 is connected to the voltage feedback unit 31 and the current adjustment unit 32.

[0043] It should be noted that the initial current generating branch 21 can generate the corresponding initial current through the first transistor M1 , which simplifies the circuit structure of the initial current generating branch 21 .

[0044] Alternatively, as Figure 4 As shown, the initial current generating branch 21 includes a first transistor M1 and a second transistor M3, the first electrode of the first transistor M1 is connected to the power supply terminal VDD, and the control electrode of the first transistor M1 is connected to the second electrode of the first transistor M1; the first electrode of the second transistor M3 is connected to the second electrode of the first transistor M1, the second electrode of the second transistor M3 is connected to the voltage feedback unit 31 and the current adjustment unit 32, and the control electrode of the second transistor M3 is connected to the output end of the operational amplifier module 10.

[0045] It should be noted that the initial current generating branch 21 generates the corresponding initial current through the first transistor M1 and the second transistor M3, which is beneficial to improving the accuracy of the initial current.

[0046] Alternatively, as Figure 5As shown, the current mirror branch 22 includes at least one third transistor M2, the control electrode of the at least one third transistor M2 is connected to the control electrode of the first transistor M1, the first electrode of the at least one third transistor M2 is connected to the power supply terminal VDD, and the second electrode of the at least one third transistor M2 is used to output at least one reference current IREF.

[0047] It should be noted that since the first transistor M1 and at least one third transistor M2 can form a mirror structure, the current flowing through the first transistor M1 is the initial current, and the current flowing through the third transistor M2 is the reference current IREF. As the initial current changes, each reference current IREF will change accordingly to synchronize and calibrate each reference current IREF.

[0048] Alternatively, as Figure 6 As shown, the voltage feedback unit 31 includes a first adjustable resistor R1 and a second resistor R2, one end of the first adjustable resistor R1 is connected to the operational amplifier module 10 and the mirror module 20, and the other end of the first adjustable resistor R1 is used to output the reference voltage VREF; one end of the second resistor R2 is connected to the other end of the first adjustable resistor R1, and the other end of the second resistor R2 is connected to the ground terminal GND.

[0049] It should be noted that the reference voltage VREF can be adjusted by changing the resistance of the first adjustable resistor R1 , wherein the reference voltage VREF is smaller than the base voltage VBG.

[0050] In some other embodiments, such as Figure 6 As shown, one end of the first adjustable resistor R1 is connected to the operational amplifier module 10 and the initial current generating branch 21 .

[0051] Alternatively, as Figure 7 As shown, the voltage feedback unit 31 includes a first adjustable resistor R1 and a second resistor R2, one end of the first adjustable resistor R1 is connected to the mirror module 20 and outputs the reference voltage VREF, and the other end of the first adjustable resistor R1 is connected to the operational amplifier module 10; one end of the second resistor R2 is connected to the other end of the first adjustable resistor R1, and the other end of the second resistor R2 is connected to the ground terminal GND.

[0052] It should be noted that the reference voltage VREF can be adjusted by changing the resistance of the first adjustable resistor R1 , wherein the reference voltage VREF is greater than the base voltage VBG.

[0053] In some other embodiments, such as Figure 6 As shown, one end of the first adjustable resistor R1 is connected to the initial current generating branch 21 , and the other end of the first adjustable resistor R1 is connected to the second input end of the operational amplifier OP1 .

[0054] Alternatively, as Figure 8 As shown, the current adjustment unit 32 includes a third adjustable resistor R3, one end of the third adjustable resistor R3 is connected to one end of the first adjustable resistor R1 and the mirror module 20, and the other end of the third adjustable resistor R3 is connected to the other end of the second resistor R2 and the ground terminal GND.

[0055] It should be noted that the third adjustable resistor R3 may be a sliding resistor or a resistor array to achieve adjustable resistance.

[0056] Alternatively, as Figure 9 、 Figure 10 、 Figure 11 as well as Figure 12 As shown, the reference signal generating circuit 100 further includes a bandgap reference module 60 , which is connected to the operational amplifier module 10 .

[0057] It should be noted that the bandgap reference module 60 is used to output a reference voltage VBG. The bandgap reference module 60 can be a bandgap reference circuit that can trim the output reference voltage VBG. The bandgap reference module 60 is connected to the operational amplifier OP1 to provide a corresponding reference voltage VBG.

[0058] The operational amplifier module 10 includes an operational amplifier OP1 , a first input terminal of the operational amplifier OP1 is connected to a feedback voltage VFB, a second input terminal of the operational amplifier OP1 is connected to a reference voltage VBG, and an output terminal of the operational amplifier OP1 outputs an operational amplifier signal.

[0059] exist Figure 9 、 Figure 11 In FIG, the first input terminal of the operational amplifier OP1 is a non-inverting input terminal, and the second input terminal of the operational amplifier OP1 is a negative input terminal. Figure 10 、 Figure 12 In the embodiment, the first input terminal of the operational amplifier OP1 is an inverting input terminal, and the second input terminal of the operational amplifier OP1 is a non-inverting input terminal.

[0060] like Figure 9 As shown, the reference voltage VREF output by the reference signal generating circuit 100 is lower than the reference voltage VBG. After the bandgap reference is calibrated, the bandgap reference module 60 of the reference signal generating circuit 100 outputs a reference voltage VBG that is independent of the process, power supply voltage, and temperature. The operational amplifier OP1, the second transistor M3, the first adjustable resistor R1, the second resistor R2, and the third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the positive input terminal and the inverting input terminal of the operational amplifier OP1 are virtually shorted, that is, the potential of the positive input terminal of the operational amplifier OP1 is equal to the potential of its inverting input terminal. Therefore, the magnitude of the reference voltage VREF can be expressed as the following calculation formula:

[0061] VREF=VFB×R2÷(R1+R2)=VBG×R2÷(R1+R2) (1)

[0062] Wherein, VREF represents the voltage value of the reference voltage VREF. VFB represents the potential of the inverting input terminal of the operational amplifier OP1. R1 represents the resistance value of the first adjustable resistor R1. R2 represents the resistance value of the second resistor R2. VBG represents the voltage value of the reference voltage VBG.

[0063] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor. The gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by forming the first transistor M1 and the third transistor M2 with a corresponding number of minimum units of the same width-to-length ratio to ensure the accuracy of the current mirror. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is an arbitrary number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0064] IM3=VFB÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3] (2)

[0065] Wherein, R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)||R3 represents the equivalent resistance of the first adjustable resistor R1 connected in series with the second resistor R2 and then connected in parallel with the third adjustable resistor R3.

[0066] Since the first transistor M1 and the second transistor M3 are both connected in series with the equivalent resistor in the same branch, the current flowing through the equivalent resistor, i.e., IM3, is equal to the current flowing through the first transistor M1 and the current flowing through the second transistor M3. The reference current IREF can be expressed as follows:

[0067] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3] (3)

[0068] Wherein, IREF represents the current value of the reference current IREF, and M is an adjustable coefficient, which is determined by the first transistor M1 and the third transistor M2.

[0069] When the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance of the third adjustable resistor R3. Figure 10 The calculation formulas for the reference voltage VREF and the reference current IREF can be calculated using the above calculation formulas (1) and (3).

[0070] Figure 11 The reference voltage VREF output by the reference signal generating circuit 100 is higher than the reference voltage VBG. After the bandgap reference is calibrated, a reference voltage VBG is output that is independent of the process, power supply voltage, and temperature. The operational amplifier OP1, the second transistor M3, the first adjustable resistor R1, the second resistor R2, and the third adjustable resistor R3 form a negative feedback loop. Under the action of the feedback loop, the positive and negative input terminals of the operational amplifier OP1 are virtually shorted, that is, the potential of the positive input terminal of the operational amplifier OP1 is equal to the potential of its negative input terminal. Therefore, the magnitude of the reference voltage VREF can be expressed as the following calculation formula:

[0071] VREF=VFB×(1+R1 / R2)=VBG×(1+R1 / R2) (4)

[0072] Wherein, VREF represents the voltage value of the reference voltage VREF. VFB represents the potential of the inverting input terminal of the operational amplifier OP1. R1 represents the resistance value of the first adjustable resistor R1. R2 represents the resistance value of the second resistor R2. VBG represents the voltage value of the reference voltage VBG.

[0073] The drain current of the first transistor M1 is equal to the sum of the currents flowing through the first adjustable resistor R1 and the third resistor. The gate-source voltage, gate length, and gate width of the third transistor M2 are respectively equal to the gate-source voltage, gate length, and gate width of the first transistor M1. This can be achieved by forming the first transistor M1 and the third transistor M2 with a corresponding number of minimum units of the same width-to-length ratio to ensure the accuracy of the current mirror. The reference current IREF (i.e., the drain current of the third transistor M2) is M times the initial current (i.e., the drain current of the first transistor M1), where M is an arbitrary number greater than 0. Therefore, the sum of the currents flowing through the first adjustable resistor R1 and the third adjustable resistor R3, i.e., IM3, can be expressed as the following calculation formula:

[0074] IM3=VREF÷[(R1+R2)∥R3]=VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (5)

[0075] Wherein, R3 represents the resistance value of the third adjustable resistor R3. (R1+R2)||R3 represents the equivalent resistance of the first adjustable resistor R1 connected in series with the second resistor R2 and then connected in parallel with the third adjustable resistor R3.

[0076] Since the first transistor M1 and the second transistor M3 are both connected in series with the equivalent resistor in the same branch, the current flowing through the equivalent resistor, i.e., IM3, is equal to the current flowing through the first transistor M1 and the current flowing through the second transistor M3. The reference current IREF can be expressed as follows:

[0077] IREF=M×IM3=M×VBG÷[(R1+R2)∥R3]×(1+R1 / R2) (6)

[0078] Here, IREF represents the current value of the reference current IREF.

[0079] When the output reference voltage VREF is determined, the reference current IREF can be calibrated by changing the resistance of the third adjustable resistor R3. Figure 12 The calculation formulas for the reference voltage VREF and the reference current IREF can be calculated using the above calculation formulas (4) and (6).

[0080] Therefore, the present application can be used to adjust the output reference voltage VREF by adjusting the resistance of the first adjustable resistor R1. Once the output reference voltage VREF is determined, the output reference current IREF can be calibrated by adjusting the resistance of the third adjustable resistor R3 without changing the output reference voltage VREF.

[0081] The embodiment of the present application further provides a chip 200, such as Figure 13 As shown, the chip 200 includes the aforementioned reference signal generating circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0082] It can be understood that since the chip 200 provided in the embodiment of the present application includes the above-mentioned reference signal generating circuit 100, it can also be connected in parallel with the voltage feedback unit 31 through the current adjustment unit 32, so that the voltage across the current adjustment unit 32 is equal to the voltage across the voltage feedback unit 31, so that without changing the feedback voltage VFB and the reference voltage VREF output by the voltage feedback unit 31, the initial current can be adjusted through the current adjustment unit 32, and then all reference currents IREF can be synchronously calibrated, which not only realizes the separate adjustment of the reference voltage VREF or the reference current IREF, but also improves the calibration efficiency of the reference current IREF.

[0083] The embodiment of the present application also provides an electronic device 300, such as Figure 14As shown, the electronic device 300 includes a device body and the above-mentioned reference signal generating circuit 100 or chip 200 provided in the device body. The electronic device 300 can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0084] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned reference signal generating circuit 100 or chip 200, it can also be connected in parallel with the voltage feedback unit 31 through the current adjustment unit 32, so that the voltage across the current adjustment unit 32 is equal to the voltage across the voltage feedback unit 31, so that without changing the feedback voltage VFB and the reference voltage VREF output by the voltage feedback unit 31, the initial current can be adjusted through the current adjustment unit 32, and then all reference currents IREF can be synchronously calibrated, which not only realizes the separate adjustment of the reference voltage VREF or the reference current IREF, but also improves the calibration efficiency of the reference current IREF.

[0085] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A reference signal generating circuit, characterized in that: The reference signal generating circuit comprises: An operational amplifier module, wherein a first input terminal of the operational amplifier module is used to access a reference voltage, a second input terminal of the operational amplifier module is used to access a feedback voltage, and an output terminal of the operational amplifier module is used to output an operational amplifier signal; a mirror module, wherein a control end of the mirror module is connected to an output end of the operational amplifier module, and the mirror module is configured to generate a corresponding initial current under the control of the operational amplifier signal, and to mirror at least one reference current according to the initial current; A reference signal adjustment module includes a voltage feedback unit and a current adjustment unit, wherein the current adjustment unit is connected in parallel with the voltage feedback unit; the voltage feedback unit is connected to the operational amplifier module and the mirror module to output a reference voltage according to the initial current.

2. The reference signal generating circuit according to claim 1, wherein: The mirror module includes: an initial current generating branch, wherein the initial current generating branch is used to generate the initial current; A current mirror branch is connected to the initial current generating branch and is used to mirror at least one reference current according to the initial current.

3. The reference signal generating circuit according to claim 2, wherein: The initial current generating branch includes a first transistor, the control electrode of the first transistor is connected to the output end of the operational amplifier module, the first electrode of the first transistor is connected to the power supply end, and the second electrode of the first transistor is connected to the voltage feedback unit and the current adjustment unit.

4. The reference signal generating circuit according to claim 2, wherein: The initial current generating branch comprises: a first transistor, wherein a first electrode of the first transistor is connected to a power supply terminal, and a control electrode of the first transistor is connected to a second electrode of the first transistor; A second transistor, wherein the first electrode of the second transistor is connected to the second electrode of the first transistor, the second electrode of the second transistor is connected to the voltage feedback unit and the current adjustment unit, and the control electrode of the second transistor is connected to the output end of the operational amplifier module.

5. The reference signal generating circuit according to claim 3 or 4, wherein: The current mirror branch includes at least one third transistor, the control electrode of the at least one third transistor is connected to the control electrode of the first transistor, the first electrode of the at least one third transistor is connected to the power supply end, and the second electrode of the at least one third transistor is used to output the at least one reference current.

6. The reference signal generating circuit according to claim 1, wherein: The voltage feedback unit includes: a first adjustable resistor, one end of which is connected to the mirror module and the operational amplifier module, and the other end of which is used to output the reference voltage; a second resistor, one end of the second resistor being connected to the other end of the first adjustable resistor, and the other end of the second resistor being connected to the ground.

7. The reference signal generating circuit according to claim 1, wherein: The voltage feedback unit includes: a first adjustable resistor, one end of which is connected to the mirror module and outputs the reference voltage, and the other end of which is connected to the operational amplifier module; a second resistor, one end of the second resistor being connected to the other end of the first adjustable resistor, and the other end of the second resistor being connected to the ground.

8. The reference signal generating circuit according to claim 6 or 7, wherein: The current adjustment unit includes a third adjustable resistor, one end of the third adjustable resistor is connected to one end of the first adjustable resistor and the mirror module, and the other end of the third adjustable resistor is connected to the other end of the second resistor and the ground end.

9. A chip, characterized in that: The chip includes the reference signal generating circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes a device body and the chip according to claim 9 provided in the device body.

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