Current mirror circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a current mirror circuit, a chip and electronic equipment, the current mirror circuit comprises a current mirror module, the current mirror module comprises a first transistor and a second transistor, the control end of the first transistor is connected with the control end of the second transistor, and the first end of the first transistor is equal to the first end voltage of the second transistor; the second end of the first transistor is used as an input node, and the second end of the second transistor is used as an output node; and the level displacement module controls the control end of the first transistor and the second end of the first transistor to maintain a first preset voltage difference. The first preset voltage difference is kept between the control end of the first transistor and the second end of the first transistor under the control of the level shift module, so that the voltage drop consumed by the current mirror can be reduced, and finally, the source circuit of the input current can obtain more voltage drops to improve the performance or integrate more functional circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a current mirror circuit, a chip, and an electronic device. Background Art

[0002] A current mirror is a widely used circuit structure in analog integrated circuits. It "replicates" the output current proportionally to the input current and is often used as a bias current source or active load. Typical current mirror structures consume a power supply voltage drop equal to at least a threshold voltage and an overdrive voltage. In low-voltage circuits, this voltage drop consumed by the current mirror results in a very small voltage drop across the connected circuits, severely impacting various performance factors, such as the output impedance and mismatch of the input current source circuit, which in turn affects the overall power supply rejection ratio (PSR) and mirroring accuracy of the current mirror. Therefore, reducing the voltage drop consumed by the current mirror has become a major concern for those skilled in the art. Utility Model Content

[0003] In view of the above problems, embodiments of the present application provide a current mirror circuit, a chip, and an electronic device to solve the above technical problems.

[0004] In a first aspect, an embodiment of the present application provides a current mirror circuit, comprising:

[0005] A current mirror module, the current mirror module includes a first transistor and a second transistor, the control end of the first transistor is connected to the control end of the second transistor, the first end of the first transistor and the first end of the second transistor have the same voltage, the second end of the first transistor is used as an input node, and the second end of the second transistor is used as an output node;

[0006] a level shift module connected between the control terminal of the first transistor and the second terminal of the first transistor;

[0007] The level shift module controls the control terminal of the first transistor and the second terminal of the first transistor to maintain a first preset voltage difference, so as to increase the voltage swing of the input node while ensuring the normal operation of the first transistor and the second transistor.

[0008] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned current mirror circuit.

[0009] In a third aspect, an embodiment of the present application further provides an electronic device comprising the above-mentioned chip or current mirror circuit.

[0010] The present application controls the first transistor's control terminal and the second terminal of the first transistor to maintain a first preset voltage difference through a level shift module, which is beneficial for reducing the voltage drop consumed by the current mirror while ensuring that the first transistor and the second transistor operate in the saturation region, and ultimately enables the source circuit of the input current to obtain more voltage drop to improve performance or integrate more functional circuits. For example, when the second terminal (i.e., the input node) of the first transistor inputs an excessively high voltage, the level shift module can reduce the control terminal voltage of the first transistor and the second transistor, thereby reducing the voltage drop consumed by the current mirror when the voltage of the input node is too high, and ensuring that the first transistor and the second transistor of the current mirror operate in the saturation region, ultimately avoiding the problem of the current mirror's voltage drop being too high and limiting its application.

[0011] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram showing a circuit structure of a current mirror in related technology

[0014] Figure 2 A schematic diagram of a current mirror circuit in an embodiment of the present application is shown.

[0015] Figure 3 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0016] Figure 4 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0017] Figure 5 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0018] Figure 6 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0019] Figure 7 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0020] Figure 8 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0021] Figure 9Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0022] Figure 10 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0023] Figure 11 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0024] Figure 12 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0025] Figure 13 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown.

[0026] Among them, the current mirror module 10, the level shift module 20, the voltage bias module 30, and the voltage step-down module 40;

[0027] A first transistor M1, a second transistor M2, a first current source I1, a third transistor M3, a first node m1, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first resistor R1, a second current source I2, a third current source I3, and a second node m2. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0029] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0030] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0031] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0032] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0033] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0034] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0035] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0036] Current mirror is a circuit structure widely used in analog integrated circuits, such as Figure 1 As shown, Figure 1A schematic diagram of a circuit structure of a current mirror in the related art is shown, wherein the current mirror includes a PMOS transistor MP1 and a PMOS transistor MP2. The sources of the PMOS transistors MP1 and MP2 are both connected to the power supply terminal VDD, and the gates of the PMOS transistors MP1 and MP2 are connected to each other. At the same time, the drain and gate of the PMOS transistor MP1 are short-circuited. The input current Iin flows through the PMOS transistor MP1, generating a voltage drop VSG1 on the PMOS transistor MP1. Since VSG1=VSG2, if the PMOS transistors MP1 and MP2 are in the same operating region, the drain of the PMOS transistor MP2 outputs a mirror current Iout. The mirror ratio is the ratio of the width-to-length ratio of MP2 to MP1.

[0037] Assuming that the threshold voltage of the PMOS tube MP1 is Vth, and the overdrive voltage of the PMOS tube MP1 working in the saturation state is Vov, the power voltage drop consumed by the PMOS tube MP1 is

[0038] VSG1=|Vth|+|Vov|

[0039] Then the remaining power supply voltage drop of other circuit structures connected to the PMOS tube MP1 is

[0040] VDD-VSG1=VDD-|Vth|-|Vov|

[0041] As can be seen, because the current mirror consumes a certain amount of voltage drop, the voltage drop available to the circuit connected to the current mirror becomes very small. In low-voltage circuits, the insufficient remaining power supply voltage drop will affect the key performance of other circuits, such as the output impedance and mismatch of the current mirror source circuit. Therefore, how to reduce the voltage drop consumed by the current mirror has become a solution that those skilled in the art are striving for.

[0042] To this end, the present application provides a current mirror circuit, a chip, and an electronic device, which are described in detail below.

[0043] First, see Figure 2 , Figure 2 A schematic diagram of a current mirror circuit in an embodiment of the present application is shown, wherein the current mirror circuit includes a current mirror module 10 and a level shift module 20 .

[0044] Specifically, the current mirror module 10 includes a first transistor M1 and a second transistor M2. The control end of the first transistor M1 and the control end of the second transistor M2 are connected to each other. The voltage of the first end of the first transistor M1 and the first end of the second transistor M2 are equal. Therefore, the first transistor M1 and the second transistor M2 mirror each other, so that the second end of the first transistor M1 can be used as an input node and the second end of the second transistor M2 can be used as an output node. When the input node inputs or outputs the corresponding current Iin, the output node can also input or output the corresponding mirror current Iout in a certain proportion.

[0045] It should be pointed out that the transistors used in the embodiments of the present application may be MOS tubes, triodes, JFET tubes, etc. The control end of each transistor is a general term for the gate or base. For example, when the transistor is a MOS tube, the control end of the transistor refers to the gate of the MOS tube; for another example, when the transistor is a triode, the control end of the transistor refers to the base of the triode. In addition, the first pole / first end of each transistor is one of the source and the drain (or one of the emitter and the collector), and the second pole / second end of each transistor is the other of the source and the drain (or the other of the emitter and the collector). Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0046] At the same time, it should be noted that the first transistor M1 and the second transistor M2 of the present application can be P-type transistors or N-type transistors. Figure 2 In the embodiment, the first transistor M1 and the second transistor M2 are PMOS transistors. In this case, the current mirror circuit of the present application mirrors the output current. Figure 3 , Figure 3 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are NMOS tubes. In this case, the current mirror circuit of the present application mirrors the input current.

[0047] The level shift module 20 is connected between the control terminal of the first transistor M1 and the second terminal of the first transistor M1. The level shift module 20 can control the control terminal of the first transistor M1 and the second terminal of the first transistor M1 to maintain a first preset voltage difference, so as to ensure that the power supply voltage drop consumed by the current mirror is reduced when the first transistor M1 and the second transistor M2 operate in the saturation region.

[0048] In some embodiments of the present application, for example, in an embodiment where the first transistor M1 and the second transistor M2 are P-type transistors, the level shift module 20 can control the voltage at the second terminal of the first transistor M1 to be greater than the voltage at the control terminal of the first transistor M1. That is, at this time, the level shift module 20 controls the voltage difference between the second terminal of the first transistor M1 and the control terminal of the first transistor M1 to be maintained at a positive voltage, which is recorded as ΔV0.

[0049] For example, see Figure 2 For an embodiment in which the first transistor M1 and the second transistor M2 are PMOS transistors, during the operation of the current mirror circuit, in order to ensure that the first transistor M1 and the second transistor M2 operate in a saturated state, the following formula needs to be satisfied:

[0050] VSD1=VDD-[VDD-VSG1+ΔV0]=|Vth1|+|Vov1|-ΔV0≥|Vov1|

[0051] |Vth1|≥ΔV0

[0052] Wherein, VSD1 is the voltage difference between the first terminal and the second terminal of the first transistor M1, VSG1 is the voltage difference between the first terminal and the control terminal of the first transistor M1, Vth1 is the threshold voltage of the first transistor M1, Vov1 is the overdrive voltage of the first transistor M1, and VDD is the power supply voltage (at Figure 2 where is the source voltage of the first transistor).

[0053] Under the condition that the above relationship between Vth1 and ΔV0 is satisfied, the minimum power supply voltage drop consumed by the current mirror is only |Vov1|, so the input node voltage is:

[0054] VIN=VDD-VSG1+ΔV0

[0055] It can be seen that for the embodiment in which the first transistor M1 and the second transistor M2 are PMOS transistors, when the level shift module 20 controls the control terminal voltage of the first transistor M1 to be less than the second terminal voltage of the first transistor M1, so that there is a positive voltage difference between the second terminal of the first transistor M1 and the control terminal of the first transistor M1, it can be ensured that the input voltage of the current mirror circuit is increased when the first transistor M1 and the second transistor M2 operate in a saturated state, and the source circuit of the input current Iin is able to obtain more voltage drop to improve its output impedance and other performance.

[0056] In some embodiments of the present application, for example, in an embodiment where the first transistor M1 and the second transistor M2 are N-type transistors, the level shift module 20 can control the voltage at the second terminal of the first transistor M1 to be lower than the voltage at the control terminal of the first transistor M1. That is, at this time, the level shift module 20 controls the voltage difference between the second terminal of the first transistor M1 and the control terminal of the first transistor M1 to be maintained at a negative voltage, which is recorded as -ΔV0.

[0057] For example, see Figure 3 For an embodiment in which the first transistor M1 and the second transistor M2 are NMOS transistors, during the operation of the current mirror circuit, in order to ensure that the first transistor M1 and the second transistor M2 operate in a saturated state, the following formula needs to be satisfied:

[0058] VDS1=VGS1-ΔV0=|Vth1|+|Vov1|-ΔV0≥|Vov1|

[0059] |Vth1|≥ΔV0

[0060] Under the condition that the above relationship between Vth1 and ΔV0 is satisfied, the minimum power supply voltage drop consumed by the current mirror is only |Vov1|, so the input node voltage is:

[0061] VIN=VGS1-ΔV0

[0062] The voltage drop that can be obtained by the source circuit of the input current Iin is:

[0063] VDD-VIN=VDD-VGS1+ΔV0

[0064] It can be seen that for the embodiment in which the first transistor M1 and the second transistor M2 are NMOS transistors, when the level shift module 20 controls the control terminal voltage of the first transistor M1 to be greater than the second terminal voltage of the first transistor M1, so that there is a negative voltage difference between the control terminal of the first transistor M1 and the second terminal of the first transistor M1, the input voltage of the current mirror circuit can be reduced while ensuring that the first transistor M1 and the second transistor M2 operate in a saturated state, thereby allowing the source circuit of the input current Iin to obtain more voltage drop to improve its output impedance and other performance.

[0065] In some embodiments of the present application, during operation of the current mirror circuit, the current output by the level shift module 20 to the second terminal of the first transistor M1 is significantly smaller than the current Iin and the current Iout. In other words, when the level shift module 20 controls the control terminal of the first transistor M1 to maintain a first predetermined voltage difference with the second terminal of the first transistor M1, virtually no current is input to the input node. This avoids the problem of the level shift module 20 inputting current to the input node and thus affecting the current mirror current replication accuracy.

[0066] In some embodiments of the present application, the level shift module 20 includes a first current source I1 and a third transistor M3, and the first current source and the third transistor M3 are connected in series between the power supply terminal VDD and the ground terminal GND; the control terminal of the first transistor M1 is connected to the first node m1 between the first current source I1 and the third transistor M3, and the control terminal of the third transistor M3 is connected to the second terminal of the first transistor M1.

[0067] For example, see Figure 4 , Figure 4 Another schematic diagram of a current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are PMOS transistors, the second end of the third transistor M3 is connected to the power supply terminal VDD, the first end of the third transistor M3 is connected to the input terminal of the first current source I1, and the second end of the first current source I1 is connected to the ground terminal GND. The third transistor M3 is an NMOS transistor. When the third transistor M3 is in the on state, the first preset voltage difference between the input node and the first node m1 is:

[0068] △V0=VGS3

[0069] Wherein, VGS3 is a voltage difference between the control terminal and the first terminal of the third transistor M3.

[0070] For example, see Figure 5 , Figure 5 Another schematic diagram of a current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are NMOS transistors, the second end of the third transistor M3 is connected to the ground terminal GND, the first end of the third transistor M3 is connected to the output end of the first current source I1, and the second end of the first current source I1 is connected to the power supply terminal VDD. The third transistor M3 is a PMOS transistor. When the third transistor M3 is in the on state, the first preset voltage difference between the input node and the first node m1 is:

[0071] -△V0=-VSG3

[0072] VSG3 is the voltage difference between the first terminal and the control terminal of the third transistor M3.

[0073] It can be seen that, through the first current source I1 and the third transistor M3, not only can the first preset voltage difference between the control terminal of the first transistor M1 and the second terminal of the first transistor M1 be controlled, but also, since no current is conducted between the first node m1 and the control terminal of the third transistor M3 (the gate current of the MOS tube is usually in the order of fA to pA, and when the input and output current is above the order of nA, the gate current is approximately zero), the level shift module 20 hardly inputs current to the input node, thereby ensuring the current mirror accuracy of the current mirror circuit of the present application.

[0074] In some embodiments of the present application, the difference between the threshold voltage of the first transistor M1 and the threshold voltage of the third transistor M3 is greater than or equal to the overdrive voltage of the third transistor M3, that is, the following formula is satisfied:

[0075] |Vth1|≥ΔV0=VGS3=|Vth3|+|Vov3|

[0076] |Vth1|-|Vth3|≥|Vov3|

[0077] When the difference between the threshold voltage of the first transistor M1 and the threshold voltage of the third transistor M3 is greater than or equal to the overdrive voltage of the third transistor M3, the first transistor M1 and the second transistor M2 can operate in a saturated state and realize the current mirror function of the current mirror circuit.

[0078] In some embodiments of the present application, the current mirror module 10 further includes a fourth transistor M4 and a fifth transistor M5, and the current mirror circuit further includes a voltage bias module 30; a first end of the fourth transistor M4 is connected to the power supply terminal VDD or the ground terminal GND, and a second end of the fourth transistor M4 is connected to the first end of the first transistor M1; a first end of the fifth transistor M5 is connected to the power supply terminal VDD or the ground terminal GND, and a second end of the fifth transistor M5 is connected to the first end of the second transistor M2; the voltage bias module 30 is connected to the control end of the fourth transistor M4, and the voltage bias module 30 is connected to the control end of the fifth transistor M5, so that the voltage bias module 30 outputs a bias voltage and controls the fourth transistor M4 and the fifth transistor M5.

[0079] For example, see Figure 6 , Figure 6 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are PMOS transistors, the fourth transistor M4 and the fifth transistor M5 are PNP transistors, the first end of the fourth transistor M4 is connected to the power supply terminal VDD, and the first end of the fifth transistor M5 is connected to the power supply terminal VDD. For another example, see Figure 7 , Figure 7Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are NMOS transistors, the fourth transistor M4 and the fifth transistor M5 are NPN transistors, the first end of the fourth transistor M4 is connected to the ground terminal GND, and the first end of the fifth transistor M5 is connected to the ground terminal GND.

[0080] It should be noted that in the above embodiment, the fourth transistor M4 and the fifth transistor M5 are bipolar junction transistors (BJTs). Compared with MOS transistor current mirrors, bipolar transistors have lower low-frequency noise. Therefore, the current mirror composed of bipolar transistors can achieve better noise performance. Therefore, the present application outputs a bias voltage through the voltage bias module 30 to control the control terminals of the fourth transistor M4 and the fifth transistor M5, which not only improves the noise performance of the current mirror, but also avoids the influence of the base current of the fourth transistor M4 and the fifth transistor M5 on the current replication accuracy.

[0081] In some embodiments of the present application, the voltage bias module 30 includes a sixth transistor M6 and a seventh transistor M7; a first end of the sixth transistor M6 is connected to the power supply terminal VDD or the ground terminal GND, a second end of the sixth transistor M6 is connected to the first end of the seventh transistor M7, and a control end of the sixth transistor M6 is connected to the second end; a second end of the seventh transistor M7 is connected to the power supply terminal VDD or the ground terminal GND, a control end of the seventh transistor M7 is connected to the control end of the first transistor M1, and the control ends of the fourth transistor M4 and the fifth transistor M5 are connected to the control end of the sixth transistor M6.

[0082] For example, see Figure 8 , Figure 8 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are PMOS transistors, the sixth transistor M6 is a PNP transistor, and the seventh transistor M7 is a PMOS transistor. The first end of the sixth transistor M6 is connected to the power supply terminal VDD, and the second end of the seventh transistor M7 is connected to the ground terminal GND.

[0083] For example, see Figure 9 , Figure 9 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the first transistor M1 and the second transistor M2 are NMOS transistors, the sixth transistor M6 is an NPN transistor, and the seventh transistor M7 is an NMOS transistor. The first end of the sixth transistor M6 is connected to the ground terminal GND, and the second end of the seventh transistor M7 is connected to the power supply terminal VDD.

[0084] It can be seen that in Figure 8 as well as Figure 9In the embodiment, since the control terminal of the sixth transistor M6 is connected to the second terminal, and the control terminals of the fourth transistor M4 and the fifth transistor M5 are connected to the control terminal of the sixth transistor M6, the base currents of the fourth transistor M4 and the fifth transistor M5 can flow into the ground terminal GND through the path where the sixth transistor M6 and the seventh transistor M7 are located, thereby preventing the base currents of the fourth transistor M4 and the fifth transistor M5 from flowing into their paths and affecting the accuracy of the current mirror.

[0085] In some embodiments of the present application, for example, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are triodes, see Figure 10 as well as Figure 11 , Figure 10 as well as Figure 11 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown. The current mirror circuit also includes a buck module 40, which is connected between the control terminal and the second terminal of the sixth transistor M6 to control the control terminal of the sixth transistor M6 and the second terminal of the sixth transistor M6 to maintain a second preset voltage difference.

[0086] It should be noted that in the related art, the base and collector of the transistor are usually directly connected. Figure 8 For example, Figure 8 The divided voltage of the sixth transistor M6 in the branch is:

[0087] VEC6=VEB6≥V ECSAT

[0088] Wherein, VEC6 is the voltage difference between the first terminal and the second terminal of the sixth transistor M6, VEB6 is the voltage difference between the first terminal and the control terminal of the sixth transistor M6, V ECSAT is the saturation operating voltage of the sixth transistor M6.

[0089] The fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 have the same voltage drop. Therefore, the minimum operating voltage of the power supply terminal VDD is:

[0090] VDDmin=VEB4+VSG1+VI1

[0091] VEB4 is the voltage difference between the first terminal and the control terminal of the fourth transistor M4 , and VI1 is the minimum voltage drop required for the first current source I1 to maintain normal operation.

[0092] For example, assuming that VEB4 = 0.7V, |Vov1| = 0.2V, |Vth1 = 0.7V, and VI1 = 0.2V, then the minimum operating voltage VDDmin of the power supply terminal VDD is 1.8V.

[0093] In the above embodiment, since the voltage reduction module 40 can control the second preset voltage difference between the control terminal of the sixth transistor M6 and the second terminal of the sixth transistor M6 , the minimum operating voltage VDDmin of the power supply terminal VDD can be further reduced.

[0094] For example, Figure 10 For example, the divided voltage of the sixth transistor M6 in the branch is:

[0095] VEC6=VEB6-△V1

[0096] ΔV1 is a second preset voltage difference between the second terminal and the control terminal of the sixth transistor M6 .

[0097] Therefore, the minimum operating voltage of the power supply terminal VDD is:

[0098] VDDmin=VEB4+VSG1+VI1-△V1

[0099] It can be seen that, when other conditions remain unchanged, assuming △V1 = 0.5V, then the minimum operating voltage VDDmin of the power supply terminal VDD is 1.3V, so that the current mirror circuit of the present application can use a lower voltage power supply and be suitable for more application scenarios.

[0100] Meanwhile, it should be noted that, since the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 have the same voltage drop, the output voltage Vout of the output node satisfies the following relationship:

[0101] Vout=VDD-VEC5-VSD2

[0102] VEC5 is a voltage difference between the first terminal and the second terminal of the fifth transistor M4 , and VSD2 is a voltage difference between the first terminal and the second terminal of the second transistor M2 .

[0103] It can be seen from the above formula that due to the existence of the second preset voltage difference ΔV1 between the second terminal and the control terminal of the sixth transistor M6, not only the minimum operating voltage VDDmin of the power supply terminal VDD is reduced, but also the output voltage Vout of the output node can be raised, thereby improving the output voltage swing of the current mirror circuit of the present application.

[0104] In some embodiments of the present application, the step-down module 40 includes a first resistor R1 and a second current source I2; the first end of the first resistor R1 is connected to the control end of the sixth transistor M6, and the second end of the first resistor R1 is connected to the second end of the sixth transistor M6; the second current source I2 is connected to the first end of the first resistor R1, and the second current source I2 is used to provide current to the first resistor R1 to control the control end of the sixth transistor M6 and the second end of the sixth transistor M6 to maintain a second preset voltage difference.

[0105] For example, see Figure 12 , Figure 12 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the input end of the second current source I2 is connected to the control end of the sixth transistor M6, the output end of the second current source I2 is connected to the ground end GND, and the second current source I2 obtains a portion of the collector current of the sixth transistor M6 via the first resistor R1. Therefore, a corresponding voltage drop of approximately ΔV1=R1*I2 is generated across the first resistor R1, thereby controlling the control end of the sixth transistor M6 and the second end of the sixth transistor M6 to maintain a second preset voltage difference.

[0106] For example, see Figure 13 , Figure 13 Another schematic diagram of the current mirror circuit in an embodiment of the present application is shown, wherein the input end of the second current source I2 is connected to the power supply end VDD, the output end of the second current source I2 is connected to the control end of the sixth transistor M6, and the second current source I2 provides the required portion of the collector current to the sixth transistor M6 via the first resistor R1. Therefore, a corresponding voltage drop across the first resistor R1 is approximately △V1=R1*I2, thereby controlling the control end of the sixth transistor M6 and the second end of the sixth transistor M6 to maintain a second preset voltage difference.

[0107] It can be seen that the second current source I2 and the first resistor R1 can cause a corresponding voltage drop to be generated at the control terminal of the sixth transistor M6 relative to the second terminal, and ultimately help reduce the minimum operating voltage VDDmin of the power supply terminal VDD.

[0108] In some embodiments of the present application, the step-down module 40 further includes a third current source I3; the third current source I3 is used to inject current into the second node m2 between the sixth transistor M6 and the seventh transistor M7, or the third current source I3 is used to extract current from the second node m2 between the sixth transistor M6 and the seventh transistor M7.

[0109] For example, see Figure 12The input end of the third current source I3 is connected to the power supply end VDD, and the output end of the third current source I3 is connected to the second node m2. The third current source I3 can inject current into the second node m2 between the sixth transistor M6 and the seventh transistor M7, thereby compensating for the current of the branch where the seventh transistor M7 is located, thereby avoiding the phenomenon that the seventh transistor M7 cannot work normally due to too small current.

[0110] For example, see Figure 13 The input end of the third current source I3 is connected to the second node m2, and the output end of the third current source I3 is connected to the ground end GND. The third current source I3 can extract the current of the second node m2 between the sixth transistor M6 and the seventh transistor M7, thereby avoiding the phenomenon that the current of the branch where the seventh transistor M7 is located is too small and cannot work normally.

[0111] It should be noted that the above content about the current mirror circuit is intended to clearly illustrate the implementation verification process of this application. Those skilled in the art can also make equivalent modified designs under the guidance of this application. For example, Figure 6 or Figure 7 The fourth transistor M4 and the fifth transistor M5 are modified into MOS transistors, or more transistors controlled by bias voltage are provided.

[0112] The present application also provides a chip including the aforementioned current mirror circuit. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a system-on-chip (SOC) chip or a system-in-package (SIP) chip. Because the chip includes the current mirror circuit described in the aforementioned embodiment, it possesses all the beneficial effects of the current mirror circuit in the aforementioned embodiment, and further description thereof will not be given here.

[0113] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablet computers, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A current mirror circuit, characterized in that: include: a current mirror module, the current mirror module comprising a first transistor and a second transistor, wherein a control terminal of the first transistor is connected to a control terminal of the second transistor, a first terminal of the first transistor and a first terminal of the second transistor have the same voltage, a second terminal of the first transistor serves as an input node, and a second terminal of the second transistor serves as an output node; a level shift module connected between the control terminal of the first transistor and the second terminal of the first transistor; The level shift module controls the control terminal of the first transistor and the second terminal of the first transistor to maintain a first preset voltage difference.

2. The current mirror circuit according to claim 1, wherein: The first transistor and the second transistor are P-type transistors or N-type transistors; When the first transistor and the second transistor are P-type transistors, the level shift module controls the voltage of the control terminal of the first transistor to be lower than the voltage of the second terminal of the first transistor; When the first transistor and the second transistor are N-type transistors, the level shift module controls the voltage of the control terminal of the first transistor to be greater than the voltage of the second terminal of the first transistor.

3. The current mirror circuit according to claim 1, wherein: The level shift module includes a first current source and a third transistor, wherein the first current source and the third transistor are connected in series between a power supply terminal and a ground terminal; The control terminal of the first transistor is connected to a first node between the first current source and the third transistor, and the control terminal of the third transistor is connected to the second terminal of the first transistor.

4. The current mirror circuit according to claim 3, wherein: A difference between a threshold voltage of the first transistor and a threshold voltage of the third transistor is greater than or equal to an over-driving voltage of the third transistor.

5. The current mirror circuit according to claim 1, wherein: The current mirror module further includes a fourth transistor and a fifth transistor, and the current mirror circuit further includes a voltage bias module; A first terminal of the fourth transistor is connected to a power supply terminal or a ground terminal, and a second terminal of the fourth transistor is connected to a first terminal of the first transistor; A first terminal of the fifth transistor is connected to the power supply terminal or the ground terminal, and a second terminal of the fifth transistor is connected to the first terminal of the second transistor; The voltage bias module is connected to the control end of the fourth transistor, and the voltage bias module is connected to the control end of the fifth transistor, so that the voltage bias module outputs a bias voltage and controls the fourth transistor and the fifth transistor.

6. The current mirror circuit according to claim 5, wherein: The voltage bias module includes a sixth transistor and a seventh transistor; The first end of the sixth transistor is connected to the power supply end or the ground end, the second end of the sixth transistor is connected to the first end of the seventh transistor, and the control end of the sixth transistor is connected to the second end; The second end of the seventh transistor is connected to the power supply end or the ground end, the control end of the seventh transistor is connected to the control end of the first transistor, and the control ends of the fourth transistor and the fifth transistor are connected to the control end of the sixth transistor.

7. The current mirror circuit according to claim 6, wherein: The fourth transistor, the fifth transistor and the sixth transistor are triodes; The current mirror circuit further includes a step-down module connected between the control terminal and the second terminal of the sixth transistor to control the control terminal of the sixth transistor and the second terminal of the sixth transistor to maintain a second preset voltage difference.

8. The current mirror circuit according to claim 7, wherein: The step-down module includes a first resistor and a second current source; A first end of the first resistor is connected to the control end of the sixth transistor, and a second end of the first resistor is connected to the second end of the sixth transistor; The second current source is connected to the first end of the first resistor, and is used to provide current to the first resistor to control a second preset voltage difference between the control end of the sixth transistor and the second end of the sixth transistor.

9. The current mirror circuit according to claim 8, wherein: The step-down module further includes a third current source; The third current source is used to inject current into a second node between the sixth transistor and the seventh transistor, or the third current source is used to draw current from the second node between the sixth transistor and the seventh transistor.

10. A chip, characterized in that: The device comprises a current mirror circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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