Testing device capable of automatically monitoring service life

Abstract

The utility model provides a testing device capable of automatically monitoring the service life, which can avoid adverse effects caused by aging of a testing seat and improve the correctness of a testing result. The testing device comprises a processor, a plurality of testing seats, a plurality of counting modules and a plurality of display modules. The plurality of test sockets are coupled to the processor. The plurality of counting modules are respectively coupled to the plurality of test seats and the processor. The plurality of display modules are respectively coupled to the plurality of counting modules. The processor is used for receiving a test instruction and generating and outputting a test signal according to the test instruction. The plurality of test seats are respectively used for testing the tested assembly based on the test signal. The plurality of counting modules are respectively used for progressively increasing the counting value by one after receiving the test signal, and generating and outputting a counting signal according to the counting value. The plurality of display modules are respectively used for receiving the counting signals and displaying counting values based on the counting signals.

Description

Technical Field

[0001] The utility model relates to a testing device, in particular to a testing device capable of self-monitoring service life. Background Art

[0002] Generally speaking, testers use test equipment to perform reliability tests on components under test (for example, electronic components such as flash memory chips) to detect whether the components have quality problems. However, the physical wear and tear caused by long-term use of the test equipment can affect the accuracy of the test results. Utility Model Content

[0003] The utility model provides a testing device capable of self-monitoring service life, which can improve the accuracy of test results.

[0004] The utility model provides a test device capable of self-monitoring service life, comprising a processor, a plurality of test sockets, a plurality of counting modules and a plurality of display modules. The plurality of test sockets are coupled to the processor. The plurality of counting modules are respectively coupled to the plurality of test sockets and the processor. The plurality of display modules are respectively coupled to the plurality of counting modules. The processor is used to receive a test instruction, and to generate and output a test signal according to the test instruction. The plurality of test sockets are respectively used to test the tested components based on the test signal. The plurality of counting modules are respectively used to increment a count value by one after receiving the test signal, and to generate and output a count signal according to the count value. The plurality of display modules are respectively used to receive the count signal, and to display the count value based on the count signal.

[0005] In an embodiment of the present invention, the test instruction is used to instruct at least one test socket among the plurality of test sockets to perform the test.

[0006] In an embodiment of the present invention, each of the plurality of counting modules includes a pulse trigger circuit and a plurality of counters. A first counter among the plurality of counters is coupled to the pulse trigger circuit, and the plurality of counters are sequentially connected to each other. The pulse trigger circuit is configured to receive the test signal and the clock signal from the processor, and when both the test signal and the clock signal are at a high level, the pulse trigger circuit is further configured to generate and output a pulse signal. The plurality of counters are configured to increment the count value by one according to the pulse signal, and to generate and output the count signal according to the count value.

[0007] In an embodiment of the present invention, each of the plurality of display modules includes a plurality of decoders and a plurality of display devices. The plurality of display devices are respectively coupled to the plurality of decoders. The plurality of decoders are configured to receive the count signal and generate and output a display signal based on the count signal. The plurality of display devices are configured to display the count value based on the display signal.

[0008] In an embodiment of the present invention, each of the display devices is an LED digital tube.

[0009] In an embodiment of the present invention, the testing device further includes a storage device coupled to the processor and configured to store a plurality of counting information corresponding to the plurality of counting modules, wherein the plurality of counting information respectively indicates a plurality of preset counting values of the plurality of counting modules.

[0010] In an embodiment of the present invention, the processor is further configured to obtain the plurality of counting information from the plurality of counting modules and store the plurality of counting information in the storage device. When the test device is restarted, the processor is further configured to obtain the plurality of counting information from the storage device, generate a plurality of control signals based on the plurality of counting information, and output the plurality of control signals to the plurality of counting modules.

[0011] In an embodiment of the present invention, the plurality of counting modules are respectively used to set a plurality of initial counting values according to the plurality of control signals, generate a plurality of initial counting signals according to the plurality of initial counting values, and output the plurality of initial counting signals to the plurality of display modules.

[0012] In an embodiment of the present invention, the testing device further includes a plurality of comparison modules and a plurality of early warning modules. The plurality of early warning modules are respectively coupled to the plurality of comparison modules. The plurality of comparison modules are respectively configured to receive the count signal and a setting signal from the processor, and to generate and output an indication signal based on the count signal and the setting signal. The plurality of early warning modules are respectively configured to receive the indication signal and to determine whether to output an alarm notification based on the indication signal.

[0013] In an embodiment of the present invention, each comparison module includes a plurality of XNOR gate circuits, an AND gate circuit, and a latch. The AND gate circuit is coupled to the plurality of XNOR gate circuits. The latch is coupled to the AND gate circuit. The plurality of XNOR gate circuits are configured to receive the count signal and the setting signal, and to generate and output a plurality of comparison signals based on the count signal and the setting signal. The AND gate circuit is configured to receive the plurality of comparison signals, and to generate and output a result signal based on the plurality of comparison signals. The latch is configured to receive the result signal, and to generate and output the indication signal based on the result signal.

[0014] Based on the above, the test device capable of self-monitoring the service life of the present invention can record the triggering times of the test socket through the counting module to avoid adverse effects caused by aging of the test socket and improve the accuracy of the test results.

[0015] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a schematic diagram of a testing device capable of self-monitoring service life according to an embodiment of the present utility model;

[0017] Figure 2 is a schematic diagram of a display module and a counting module according to an embodiment of the present utility model;

[0018] Figure 3 is a schematic diagram of a comparison module and an early warning module according to an embodiment of the present utility model;

[0019] Figure 4 1 is a schematic diagram of a testing device capable of self-monitoring service life according to an embodiment of the present utility model;

[0020] Figure 5 It is a schematic diagram of a display module and a counting module according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, like reference numerals are used in the drawings and the description to refer to like or similar parts.

[0022] Figure 1 This is a schematic diagram of a testing device capable of self-monitoring service life according to an embodiment of the present invention. Figure 1The testing device 100 includes a processor 110, test sockets 120-1 to 120-N, counting modules 130-1 to 130-N, display modules 140-1 to 140-N, comparison modules 150-1 to 150-N, and early warning modules 160-1 to 160-N. The processor 110 is coupled to the test sockets 120-1 to 120-N and the counting modules 130-1 to 130-N. The test sockets 120-1 to 120-N, the counting modules 130-1 to 130-N, and the display modules 140-1 to 140-N are coupled to each other accordingly. The display modules 140-1 to 140-N are respectively coupled to the counting modules 130-1 to 130-N. The comparison modules 150-1 to 150-N are respectively coupled to the counting modules 130-1 to 130-N and the processor 110. The warning modules 160-1 to 160-N are coupled to the comparison modules 150-1 to 150-N, respectively. The number of test sockets 120-1 to 120-N, counting modules 130-1 to 130-N, display modules 140-1 to 140-N, comparison modules 150-1 to 150-N, and warning modules 160-1 to 160-N is the same, and can be designed based on actual needs. This invention is not limited to this.

[0023] In this embodiment, the processor 110 can receive a test instruction and generate and output a test signal ST based on the test instruction. Specifically, the processor 110 can receive the test instruction from a host computer, wherein the test instruction is used to indicate the test sockets (e.g., test socket 120-1, test socket 120-4, and test socket 120-N) among the test sockets 120-1 to 120-N that need to be tested (e.g., reliability tested). The processor 110 can generate the test signal ST based on the test instruction and output the test signal ST to the test sockets 120-1, 120-4, and 120-N and the counting modules 130-1, 130-4, and 130-N via a general-purpose input / output interface (not shown). In this embodiment, the test signal ST is, for example, a high-level pulse signal.

[0024] Accordingly, the test socket 120 - 1 (or the test socket 120 - 4 and the test socket 120 -N) can test the connected device under test (not shown) based on the test signal ST.

[0025] On the other hand, after counting module 130-1 (or, counting module 130-4 and counting module 130-N) receives test signal ST, counting module 130-1 (or, counting module 130-4 and counting module 130-N) may increment its count value by one and generate a count signal based on the count value. Counting module 130-1 (or, counting module 130-4 and counting module 130-N) may output the count signal to display module 140-1 (or, display module 140-4 and display module 140-N). Accordingly, display module 140-1 (or, display module 140-4 and display module 140-N) may display the count value of counting module 130-1 (or, counting module 130-4 and counting module 130-N) based on the count signal.

[0026] That is, counting module 130-1 (or, counting module 130-4 and counting module 130-N) can count the number of times test socket 120-1 (or, test socket 120-4 and test socket 120-N) executes a test (i.e., a count value) and output the count value via display module 140-1 (or, display module 140-4 and display module 140-N). In this way, testers can know the number of times test sockets 120-1 to 120-N execute a test (i.e., the number of triggers), thereby avoiding using test sockets with more severe physical wear (i.e., higher count values) for testing, thereby maintaining the accuracy of test results.

[0027] For further explanation, please also refer to Figure 1 and Figure 2 , taking the counting module 130 - 1 and the display module 140 - 1 as an example, Figure 2 1 is a schematic diagram of a display module and a counting module according to an embodiment of the present invention. In this embodiment, the counting module 130 - 1 includes counters 131 - 134 and a pulse trigger circuit 135 . Figure 2 The counting module 130 - 1 shown has four decimal counters 131 - 134 for recording times from 0 to 9999. The number and type of counters in the counting module can be designed according to actual needs and are not limited by the present invention.

[0028] In this embodiment, the counters 131-134 can be, for example, 74LS192 counters. Specifically, pins Q0-Q3 of the counters 131-134 are output pins, pins D0-D3 are preset input pins, and pins Preset enable pin, pin CP U For the addition count input pin, pin CP D For the subtraction count input pin, pin For the carry output pin, pin The pin CR is a clear pin, the pin GND is a ground pin for connecting to a ground terminal (not shown), and the pin VCC is a power pin for connecting to a reference high voltage (not shown).

[0029] As mentioned above, the counters 131 to 134 are decimal counters. In this embodiment, the counters 131 to 134 can be fed back by the carry output pin of the previous counter. Coupled to the next counter's add count input pin CP U The method is to realize that after the current counter (for example, counter 131) counts to 9, its carry output pin Output signal to the count up input pin CP of the counter 132 U Specifically, the first counter 131 of the counters 131 to 134 is coupled to the pulse trigger circuit 135, and the counters 131 to 134 are connected to each other in sequence. The pin CP of the counter 131 U The output terminal of the pulse trigger circuit 135 and the pin of the counter 131 are coupled The pin CP coupled to the counter 132 U , pins of counter 132 The pin CP coupled to the counter 133 U And the pin of counter 133 The pin CP coupled to the counter 134 U .

[0030] In this embodiment, the pulse trigger circuit 135 can be, for example, a two-input AND gate circuit. The truth table of the two-input AND gate circuit is shown in Table 1.

[0031] Input #1 Input #2 Output 0 0 0 0 1 0 1 0 0 1 1 1

[0032] Table 1

[0033] It can be seen from Table 1 that when the input terminal #1 and the input terminal #2 of the AND gate circuit are both at high levels, the pulse trigger circuit 135 can generate a high-level pulse signal.

[0034] When a tester wishes to use the test socket 120-1 to test the connected component under test (not shown), he or she may transmit a test instruction to the test apparatus 100 via a host computer (not shown). Accordingly, the processor 110 may generate and output a high-level test signal ST to the tester 120-1 and the counting module 130-1 according to the test instruction, thereby triggering the tester 120-1 to perform a test and triggering the counting module 130-1 to perform a count.

[0035] In this embodiment, the pulse trigger circuit 135 in the counting module 130-1 can receive the test signal ST from the processor 110 through the input terminal #1 and the clock signal CLK from the processor 110 through the input terminal #2. As shown in Table 1, when the test signal ST and the clock signal CLK are both high, the pulse trigger circuit 135 can generate and output the pulse signal SP, and output the pulse signal SP to the pin CP of the counter 131. U , so that the counters 131 - 134 can increase the count value of the counting module 130 - 1 by one according to the pulse signal SP, and generate and output a counting signal to the display module 140 - 1 according to the count value.

[0036] In this embodiment, the display module 140-1 includes decoders 141-144 and display devices 145-148. The display devices 145-148 are coupled to the decoders 141-144, respectively. The display devices 145-148 may be, for example, LED digital tubes, the same number of which as the decoders 141-144, respectively configured to display the numerical values represented by the display signals SD1-SD4 transmitted by the decoders 141-144. The decoders 141-144 may be, for example, 74LS47 decoding chips, the same number of which as the counters 131-134, respectively configured to receive and interpret the counting signals from the counters 131-134. In detail, pins A to D in the decoders 141 to 144 are input pins, pins OA to OG are output pins, pin GND is a ground pin for connecting to a ground terminal (not shown), pin VCC is a power pin for connecting to a reference high voltage (not shown), pin LT is a test light input pin, pin RBI is a zero-extinguishing input pin, pin BI is a light-extinguishing input, and pin RBO, which is set together with pin BI, is a zero-extinguishing output pin.

[0037] In this embodiment, the counting signals include counting signals SC10-SC13 output by counter 131, counting signals SC20-SC23 output by counter 132, counting signals SC30-SC33 output by counter 133, and counting signals SC40-SC43 output by counter 134. Counter 131 transmits counting signals SC10-SC13 to input pins A-D of decoder 141 via output pins Q0-Q3, respectively. Similarly, counter 132 (or, counters 133 and 134) transmits counting signals SC20-SC23 (or, counting signals SC30-SC33 and counting signals SC40-SC43) to input pins A-D of decoder 142 (or, decoders 143 and 144), respectively, via output pins Q0-Q3. Accordingly, the decoders 141 - 144 can respectively generate and output display signals SD1 - SD4 to the display devices 145 - 148 according to the counting signal SC, so that the display devices 145 - 148 can display the counting value of the counting module 130 - 1 .

[0038] As described above, the count values of counting modules 130-1 to 130-N represent the number of times test sockets 120-1 to 120-N have been triggered. The test device 100 of the present invention can display the count values of counting modules 130-1 to 130-N on display modules 140-1 to 140-N, respectively, allowing testers to know the number of times test sockets 120-1 to 120-N have been triggered. This helps prevent inaccurate testing caused by aging of test sockets 120-1 to 120-N, thereby improving the accuracy of test results.

[0039] On the other hand, in this embodiment, the comparison modules 160-1 to 160-N can be used to receive counting signals from the counting modules 130-1 to 130-N and setting signals from the processor 110, respectively, and generate and output indication signals to the early warning modules 170-1 to 170-N based on the counting signals and the setting signals, respectively, wherein the indication signals are used to indicate whether the early warning modules 170-1 to 170-N need to output an alarm notification.

[0040] For example, the set signal received by comparison modules 160-1 to 160-N can be used to represent a warning threshold. Comparison modules 160-1 to 160-N can determine the count values of counting modules 130-1 to 130-N based on the count signals of counting modules 130-1 to 130-N, respectively, and determine whether the count values of counting modules 130-1 to 130-N are greater than the warning threshold indicated by the set signal received from processor 110. For example, if comparison module 160-1 determines that the count value of counting module 130-1 is greater than the warning threshold indicated by the set signal, comparison module 160-1 can generate and output an indication signal to warning module 170-1 indicating the need to output an alarm notification, so that warning module 170-1 can output an alarm notification to notify test personnel to repair test device 100 and / or notify test personnel to avoid using test socket 120-1 for testing. Therefore, the problem of inaccurate testing caused by aging of the test socket 120 - 1 can be avoided, thereby improving the accuracy of the test result.

[0041] For example, Figure 3 As shown, Figure 3 This is a schematic diagram illustrating a comparison module and a warning module according to an embodiment of the present invention. In this embodiment, taking comparison module 160-1 and warning module 170-1 as examples, comparison module 160-1 includes XNOR gates X0-X3, an AND gate A0, and a latch L0. AND gate A0 is coupled to XNOR gates X0-X3. Latch L0 is coupled to AND gate A0. The truth table for XNOR gates X0-X3 is shown in Table 2.

[0042] Input #1 Input #2 Output 0 0 1 0 1 0 1 0 0 1 1 1

[0043] Table 2

[0044] As shown in Table 2, when input terminals #1 and #2 of the XOR gates X0-X3 are identical, the XOR gates X0-X3 generate high-level pulse signals. For example, input terminals #1 of the XOR gates X0-X3 are respectively coupled to output pins Q0-Q3 of the counter 131 and are respectively configured to receive count signals SC10-SC13 from the counter 131. For example, input terminals #2 of the XOR gates X0-X3 are respectively coupled to the processor 110 and are respectively configured to receive set signals SS0-SS3 from the counter 131.

[0045] Next, XNOR gates X0-X3 generate and output comparison signals R0-R3 to AND gate A0 based on count signals SC10-SC13 and set signals SS0-SS3, respectively. In this embodiment, AND gate A0 is a four-input AND gate circuit that outputs a high-level pulse signal only when all four inputs are high. AND gate A0 generates and outputs a result signal RT to latch L0 based on comparison signals R0-R3.

[0046] In this embodiment, latch L0 may be, for example, an SR latch. The S terminal of latch L0 is coupled to the output terminal of AND gate A0, the Q terminal of latch L0 is coupled to early warning module 170-1, and the R terminal of latch L0 is coupled to processor 110 for receiving a set signal SS from processor 110. Latch L0 may generate and output an indication signal SI to early warning module 170-1 based on result signal RT, indicating whether early warning module 170-1 should output an alarm notification. If indication signal SI indicates that an alarm notification is required, early warning module 170-1 may, for example, output the alarm notification to a terminal device (not shown) belonging to a tester, thereby notifying the tester to repair test device 100 to improve the accuracy of the test results.

[0047] Figure 4 1 is a schematic diagram of a testing device capable of self-monitoring service life according to an embodiment of the present utility model; Figure 5 This is a schematic diagram of a display module and a counting module according to an embodiment of the present invention. Figure 4 and Figure 5 .

[0048] In this embodiment, in addition to the processor 310, the test sockets 320-1 to 320-N, the counting modules 330-1 to 330-N, the display modules 340-1 to 340-N, the comparison modules 350-1 to 350-N and the warning modules 360-1 to 360-N, the test device 300 also includes a storage device 370 coupled to the processor 310.

[0049] In this embodiment, storage device 370 is a non-volatile memory device. Storage device 370 is used, for example, to store a plurality of counting information corresponding to counting modules 330-1 through 330-N, where the plurality of counting information indicates a plurality of preset count values for each of counting modules 330-1 through 330-N. Specifically, before testing device 300 is shut down or after the count value of at least one of counting modules 330-1 through 330-N is updated, processor 310 can retrieve the plurality of counting information from counting modules 330-1 through 330-N and store the plurality of counting information in storage device 370.

[0050] Accordingly, when the testing apparatus 300 is restarted, the processor 310 can retrieve a plurality of counting information from the storage device 370 and generate a plurality of control signals CON1-CONN based on the plurality of counting information. The plurality of control signals CON1-CONN are output to the counting modules 330-1-330-N, respectively. The counting modules 330-1-330-N can respectively set a plurality of preset counting values based on the plurality of control signals CON1-CONN, generate a plurality of preset counting signals SCI1-SCIN based on the plurality of preset counting values, and output the plurality of preset counting signals SCI1-SCIN to the display modules 340-1-340-N, so that the display modules 340-1-340-N display the preset counting values of the counting modules 330-1-330-N.

[0051] Further explanation, such as Figure 5 As shown, taking counting module 330-1 and display module 340-1 as examples, counting module 330-1 includes counters 331-334 and pulse trigger circuit 135, while display module 340-1 includes decoders 341-344 and display devices 345-348. Counters 331-334 can be, for example, 74LS192 counters. Decoders 341-344 can be, for example, 74LS47 decoding chips.

[0052] The processor 310 can transmit the control signal CON1 to the preset input pins D0 to D3 and the preset enable pins of the counters 331 to 334. The counters 331-334 can set the preset count values of the counting module 330-1 according to the plurality of control signals CON1. Subsequently, the counters 331-334 can generate the preset count signal SCI1 according to the preset count values of the counting module 330-1. Specifically, the preset count signal SCI1 is composed of preset count signals SCI10-SCI13, preset count signals SCI20-SCI23, preset count signals SCI30-SCI33, and preset count signals SCI40-SCI43. The counters 331-334 can generate the preset count signals SCI10-SCI13, preset count signals SCI20-SCI23, preset count signals SCI30-SCI33, and preset count signals SCI40-SCI43, respectively, according to the preset count values.

[0053] Counter 331 can transmit preset count signals SCI10-SCI13 to input pins A-D of decoders 341-344 via output pins Q0-Q3, respectively. Similarly, counter 332 (or, counters 333 and 334) can transmit preset count signals SCI20-SCI23 (or, preset count signals SCI30-SCI33 and preset count signals SCI40-SCI43) to input pins A-D of decoder 342 (or, decoder 343 and decoder 344) via output pins Q0-Q3, respectively. In this way, the decoders 341-344 can respectively generate and output the preset display signals SDI1-SDI4 to the display devices 345-348 according to the preset counting signals SCI10-SCI13, the preset counting signals SCI20-SCI23, the preset counting signals SCI30-SCI33, and the preset counting signals SCI40-SCI43, so that the display devices 345-348 can display the preset counting values belonging to the counting module 130-1.

[0054] According to the above, the testing device 300 of the present invention can store the counting information of the counting modules 330-1 to 330-N through the non-volatile storage device 370, so that after the testing device 300 is restarted, the preset counting values of the counting modules 330-1 to 330-N can be set, and the service life of the testing device 300 can be accurately recorded, thereby avoiding the problem of inaccurate testing and effectively improving the accuracy of the test results.

[0055] In summary, the utility model provides a test device that can self-monitor its service life. The counting module can record the number of times the test socket is triggered to avoid adverse effects caused by aging of the test socket, thereby improving the accuracy of the test results, and output alarm notifications through the comparison module and the early warning module to instruct the tester to repair the test device.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A testing device capable of self-monitoring service life, characterized in that: include: A processor, configured to receive a test instruction, and generate and output a test signal according to the test instruction; a plurality of test sockets, coupled to the processor, and respectively used to test the components under test based on the test signals; a plurality of counting modules, respectively coupled to the plurality of test sockets and the processor, and respectively configured to increment a count value by one after receiving the test signal, and to generate and output a count signal according to the count value; as well as A plurality of display modules are respectively coupled to the plurality of counting modules and respectively used for receiving the counting signals and displaying the counting values based on the counting signals.

2. The testing device according to claim 1, wherein: The test instruction is used to instruct at least one test socket among the plurality of test sockets to perform the test.

3. The testing device according to claim 1, wherein: Each of the plurality of counting modules comprises: a pulse trigger circuit, configured to receive the test signal and the clock signal from the processor, and to generate and output a pulse signal when both the test signal and the clock signal are at a high level; and Multiple counters, wherein the first counter among the multiple counters is coupled to the pulse trigger circuit, and the multiple counters are connected to each other in sequence, wherein the first counter is used to receive the pulse signal, and the multiple counters are used to increment the count value by one according to the pulse signal, and generate and output the count signal according to the count value.

4. The testing device according to claim 1, wherein: Each of the plurality of display modules comprises: a plurality of decoders for receiving the counting signal, and generating and outputting a display signal according to the counting signal; and A plurality of display devices are respectively coupled to the plurality of decoders and used for displaying the counting value according to the display signal.

5. The testing device according to claim 4, characterized in that: Each of the display devices is an LED digital tube.

6. The testing device according to claim 1, wherein: Also includes: The storage device is coupled to the processor and is used to store a plurality of counting information corresponding to the plurality of counting modules respectively, wherein the plurality of counting information is used to indicate a plurality of preset counting values of the plurality of counting modules respectively.

7. The testing device according to claim 6, characterized in that: The processor is further configured to obtain the plurality of counting information from the plurality of counting modules and store the plurality of counting information in the storage device, and When the testing device is restarted, the processor is further configured to obtain the plurality of counting information from the storage device, generate a plurality of control signals according to the plurality of counting information, and output the plurality of control signals to the plurality of counting modules respectively.

8. The testing device according to claim 7, characterized in that: The plurality of counting modules are respectively used for setting the plurality of preset counting values according to the plurality of control signals, generating a plurality of preset counting signals according to the plurality of preset counting values, and outputting the plurality of preset counting signals to the plurality of display modules.

9. The testing device according to claim 1, wherein: Also includes: a plurality of comparison modules, respectively coupled to the plurality of counting modules and the processor, and respectively configured to receive the counting signals and the setting signals from the processor, and generate and output indication signals based on the counting signals and the setting signals; as well as A plurality of warning modules are respectively coupled to the plurality of comparison modules and respectively used to receive the indication signal and determine whether to output an alarm notification based on the indication signal.

10. The testing device according to claim 9, characterized in that: Each of the comparison modules comprises: a plurality of XNOR gate circuits, configured to receive the counting signal and the setting signal, and generate and output a plurality of comparison signals according to the counting signal and the setting signal; an AND gate circuit coupled to the plurality of XNOR gate circuits, configured to receive the plurality of comparison signals and generate and output a result signal according to the plurality of comparison signals; and The latch is coupled to the AND gate circuit, and is used for receiving the result signal, and generating and outputting the indication signal according to the result signal.

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