Shift register, gate drive circuit and display panel

Abstract

The utility model provides a shift register, a gate drive circuit and a display panel, relates to the technical field of display, and is used for solving the problems of secondary steps and miscellaneous peaks existing in gate drive signals output by an existing shift register. In the shift register, a first node control circuit is respectively coupled with a first node, a first initial signal input end, a first clock signal input end, a first level signal input end and a second level signal input end; the second node control circuit is respectively coupled with the second node, the third node, the first gate driving signal output end, the first level signal input end and the second level signal input end; the first output control circuit is respectively coupled with a first gate driving signal output end, a first node, a second node, a first level signal input end and a second level signal input end; the third node control circuit is coupled with the third node, the fourth node, the first clock signal input end, the first level signal input end and the second level signal input end.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and people's requirements for display quality are becoming increasingly higher. To better realize narrow-bezel display products, display products adopt GOA (Gate On Array) technology. This technology directly integrates the gate drive circuit on the array substrate. The gate drive circuit uses the various stages of shift registers included in the gate drive circuit to drive the sub-pixel rows in the display area, thereby realizing the display function of the display product. However, the gate drive signal output by the existing shift registers suffers from two-stage steps and noise peaks. Utility Model Content

[0003] The purpose of the utility model is to provide a shift register, a gate driving circuit and a display panel, which are used to solve the problems of secondary steps and miscellaneous peaks existing in the gate driving signal output by the existing shift register.

[0004] In order to achieve the above purpose, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a shift register, comprising:

[0006] a first node control circuit, coupled to the first node, the first start signal input terminal, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; and configured to control, under control of a first start signal inputted to the first start signal input terminal and a first clock signal inputted to the first clock signal input terminal, to make or break an electrical connection between the first node and the first level signal input terminal, and to make or break an electrical connection between the first node and the second level signal input terminal;

[0007] a second node control circuit, coupled to the second node, the third node, the first gate drive signal output terminal, the first level signal input terminal, and the second level signal input terminal, respectively; and configured to control, under control of the potential of the third node and the first gate drive signal outputted from the first gate drive signal output terminal, to switch on or off the electrical connection between the second node and the first level signal input terminal, and to switch on or off the electrical connection between the second node and the second level signal input terminal;

[0008] a first output control circuit, coupled to the first gate drive signal output terminal, the first node, the second node, a first level signal input terminal, and a second level signal input terminal, respectively; and configured to control, under control of the potential of the first node and the potential of the second node, to switch on or off the electrical connection between the first gate drive signal output terminal and the first level signal input terminal, and to switch on or off the electrical connection between the first gate drive signal output terminal and the second level signal input terminal;

[0009] a third node control circuit, coupled to the third node, the fourth node, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; and configured to control, under control of the potential of the fourth node and the first clock signal input terminal, to switch on or off the electrical connection between the third node and the first level signal input terminal, and to switch on or off the electrical connection between the third node and the second level signal input terminal;

[0010] The fourth node control circuit is coupled to the fourth node, the first start signal input terminal, the first level signal input terminal and the second level signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the fourth node and the first level signal input terminal, and the conduction or disconnection of the electrical connection between the fourth node and the second level signal input terminal under the control of the first start signal input terminal.

[0011] Optionally, the first node control circuit includes a first control subcircuit and a second control subcircuit;

[0012] The first control subcircuit is coupled to the first start signal input terminal, the second level signal input terminal, the fifth node, and the first node, respectively; and is configured to control the electrical connection between the first node and the second level signal input terminal to be opened or closed, and the electrical connection between the first node and the fifth node to be opened or closed, under the control of the first start signal input terminal.

[0013] The second control subcircuit is coupled to the first clock signal input terminal, the second level signal input terminal, the first node, the fifth node, and the first level signal input terminal, respectively; and is configured to control the electrical connection between the second level signal input terminal and the first node and the electrical connection between the first level signal input terminal and the fifth node to be opened or opened under the control of the first clock signal input terminal.

[0014] The second node control circuit controls a third control subcircuit and a fourth control subcircuit;

[0015] The third control subcircuit is coupled to the third node, the second level signal input terminal, the sixth node, and the second node, respectively; and is configured to control, under the control of the potential of the third node, to switch on or off the electrical connection between the second level signal input terminal and the second node, and to switch on or off the electrical connection between the sixth node and the second node;

[0016] The fourth control subcircuit is coupled to the first gate drive signal output terminal, the second level signal input terminal, the second node, the sixth node, and the first level signal input terminal, respectively; and is configured to control, under the control of the first gate drive signal output by the first gate drive signal output terminal, to conduct or disconnect the electrical connection between the second level signal input terminal and the second node, and to conduct or disconnect the electrical connection between the sixth node and the first level signal input terminal;

[0017] The first output control circuit includes a fifth control subcircuit and a sixth control subcircuit;

[0018] The fifth control subcircuit is coupled to the first node, the second level signal input terminal, the first gate drive signal output terminal, and the seventh node, respectively; and is configured to control, under the control of the potential of the first node, to switch on or off the electrical connection between the second level signal input terminal and the first gate drive signal output terminal, and to switch on or off the electrical connection between the seventh node and the first gate drive signal output terminal;

[0019] The sixth control subcircuit is coupled to the second node, the second level signal input terminal, the first gate drive signal output terminal, the seventh node, and the first level signal input terminal, respectively; and is configured to control, under the control of the potential of the second node, to switch on or off the electrical connection between the second level signal input terminal and the first gate drive signal output terminal, and to switch on or off the electrical connection between the seventh node and the first level signal input terminal;

[0020] The third node control circuit includes a seventh control subcircuit and an eighth control subcircuit;

[0021] The seventh control subcircuit is coupled to the fourth node, the second-level signal input terminal, the third node, and the eighth node, respectively; and is configured to control, under the control of the potential of the fourth node, to switch on or off the electrical connection between the second-level signal input terminal and the third node, and to switch on or off the electrical connection between the third node and the eighth node;

[0022] The eighth control subcircuit is coupled to the first clock signal input terminal, the second level signal input terminal, the third node, the eighth node and the first level signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the third node, and to control the conduction or disconnection of the electrical connection between the eighth node and the first level signal input terminal under the control of the first clock signal input into the first clock signal input terminal.

[0023] Optionally, the first control subcircuit includes a first transistor and a third transistor; the gate of the first transistor is coupled to the first start signal input terminal, the first electrode of the first transistor is coupled to the second level signal input terminal, and the second electrode of the first transistor is coupled to the first node; the gate of the third transistor is coupled to the first start signal input terminal, the first electrode of the third transistor is coupled to the fifth node, and the second electrode of the third transistor is coupled to the first node;

[0024] The second control subcircuit includes a second transistor and a fourth transistor; a gate of the second transistor is coupled to the first clock signal input terminal, a first electrode of the second transistor is coupled to the second level signal input terminal, and a second electrode of the second transistor is coupled to the first node; a gate of the fourth transistor is coupled to the first clock signal input terminal, a first electrode of the fourth transistor is coupled to the first level signal input terminal, and a second electrode of the fourth transistor is coupled to the fifth node;

[0025] The third control subcircuit includes a thirteenth transistor and a fifteenth transistor; a gate of the thirteenth transistor is coupled to the third node, a first electrode of the thirteenth transistor is coupled to the second-level signal line, and a second electrode of the thirteenth transistor is coupled to the second node; a gate of the fifteenth transistor is coupled to the third node, a first electrode of the fifteenth transistor is coupled to the sixth node, and a second electrode of the fifteenth transistor is coupled to the second node;

[0026] The fourth control subcircuit includes a fourteenth transistor and a sixteenth transistor; a gate of the fourteenth transistor is coupled to the first gate drive signal output terminal, a first electrode of the fourteenth transistor is coupled to the second level signal input terminal, and a second electrode of the fourteenth transistor is coupled to the second node; a gate of the sixteenth transistor is coupled to the first gate drive signal output terminal, a first electrode of the sixteenth transistor is coupled to the first level signal input terminal, and a second electrode of the sixteenth transistor is coupled to the sixth node;

[0027] The fifth control subcircuit includes a fifth transistor and a seventh transistor, wherein the gate of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the second level signal input terminal, and the second electrode of the fifth transistor is coupled to the first gate drive signal output terminal; the gate of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the seventh node, and the second electrode of the seventh transistor is coupled to the first gate drive signal output terminal;

[0028] The sixth control subcircuit includes a sixth transistor and an eighth transistor, wherein a gate of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is coupled to the second level signal input terminal, and a second electrode of the sixth transistor is coupled to the first gate drive signal output terminal; a gate of the eighth transistor is coupled to the second node, a first electrode of the eighth transistor is coupled to the first level signal input terminal, and a second electrode of the eighth transistor is coupled to the seventh node;

[0029] The seventh control subcircuit includes a ninth transistor and an eleventh transistor, wherein a gate of the ninth transistor is coupled to the fourth node, a first electrode of the ninth transistor is coupled to the second-level signal input terminal, and a second electrode of the ninth transistor is coupled to the third node; a gate of the eleventh transistor is coupled to the fourth node, a first electrode of the eleventh transistor is coupled to the eighth node, and a second electrode of the eleventh transistor is coupled to the third node;

[0030] The eighth control subcircuit includes a tenth transistor and a twelfth transistor, wherein a gate of the tenth transistor is coupled to the first clock signal input terminal, a first electrode of the tenth transistor is coupled to the second level signal input terminal, and a second electrode of the tenth transistor is coupled to the third node; a gate of the twelfth transistor is coupled to the first clock signal input terminal, a first electrode of the twelfth transistor is coupled to the first level signal input terminal, and a second electrode of the twelfth transistor is coupled to the eighth node;

[0031] The fourth node control circuit includes a seventeenth transistor and an eighteenth transistor, wherein a gate of the seventeenth transistor is coupled to the first start signal input terminal, a first electrode of the seventeenth transistor is coupled to the second level signal input terminal, and a second electrode of the seventeenth transistor is coupled to the fourth node; a gate of the eighteenth transistor is coupled to the first start signal input terminal, a first electrode of the eighteenth transistor is coupled to the first level signal input terminal, and a second electrode of the eighteenth transistor is coupled to the fourth node;

[0032] The first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor and the fourteenth transistor include P-type transistors; the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor and the sixteenth transistor include N-type transistors.

[0033] Based on the technical solution of the above-mentioned shift register, the second aspect of the present invention provides a gate drive circuit, comprising a plurality of the above-mentioned shift registers in cascade; the first start signal input terminal coupled to the first stage shift register is coupled to the first frame start signal line; the first start signal input terminal coupled to the n+1 stage shift register is coupled to the first gate drive signal output terminal of the n stage shift register, where n is an integer greater than or equal to 1.

[0034] Based on the technical solution of the above-mentioned gate drive circuit, the third aspect of the present invention provides a display panel, including the above-mentioned gate drive circuit, and the display panel also includes a first clock signal line, and the positive projection of at least part of the shift register in the gate drive circuit on the base substrate of the display panel at least partially overlaps with the positive projection of the first clock signal line on the base substrate.

[0035] Optionally, the display panel further includes a second shift register, and the second shift register includes:

[0036] a second output control circuit, coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal, and the second gate drive signal output terminal, respectively; and configured to control the electrical connection between the first level signal input terminal and the second gate drive signal output terminal to be conducted or disconnected under the common control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal;

[0037] a third output control circuit, coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal, and the second gate drive signal output terminal, respectively; and configured to control the electrical connection between the second level signal input terminal and the second gate drive signal output terminal to be conducted or disconnected under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal;

[0038] The voltage stabilizing circuit is coupled to the ground signal input terminal and the second gate driving signal output terminal respectively.

[0039] Optionally, the second output control circuit includes:

[0040] a ninth control subcircuit, coupled to the third clock signal input terminal, the ninth node, and the second gate drive signal output terminal, respectively, and configured to control, under control of a third clock signal inputted from the third clock signal input terminal, to switch on or off the electrical connection between the ninth node and the second gate drive signal output terminal;

[0041] a tenth control subcircuit, coupled to the second clock signal input terminal, the ninth node, and the tenth node, respectively, and configured to control the electrical connection between the ninth node and the tenth node to be opened or closed under the control of the second clock signal input terminal;

[0042] an eleventh control subcircuit, coupled to the second start signal input terminal, the tenth node, and the first level signal input terminal, respectively, for controlling, under the control of a second start signal inputted by the second start signal input terminal, to switch on or off the electrical connection between the tenth node and the first level signal input terminal;

[0043] a twelfth control sub-circuit, coupled to the third clock signal input terminal, the eleventh node, and the second gate drive signal output terminal, respectively, and configured to control the electrical connection between the eleventh node and the second gate drive signal output terminal to be turned on or off under the control of a third clock signal inputted from the third clock signal input terminal;

[0044] a thirteenth control sub-circuit, coupled to the second clock signal input terminal, the eleventh node, and the twelfth node, respectively, for controlling, under the control of the second clock signal inputted from the second clock signal input terminal, to switch on or off the electrical connection between the eleventh node and the twelfth node;

[0045] A fourteenth control sub-circuit is coupled to the second start signal input terminal, the twelfth node and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the twelfth node and the second level signal input terminal under the control of the second start signal input terminal.

[0046] Optionally, the ninth control subcircuit includes a nineteenth transistor, a gate of the nineteenth transistor is coupled to the third clock signal input terminal, a first electrode of the nineteenth transistor is coupled to the ninth node, and a second electrode of the nineteenth transistor is coupled to the second gate drive signal output terminal;

[0047] The tenth control sub-circuit includes a twentieth transistor, a gate of the twentieth transistor is coupled to the second clock signal input terminal, a first electrode of the twentieth transistor is coupled to the tenth node, and a second electrode of the twentieth transistor is coupled to the ninth node;

[0048] The eleventh control sub-circuit includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the second start signal input terminal, a first electrode of the twenty-first transistor is coupled to the first level signal input terminal, and a second electrode of the twenty-first transistor is coupled to the tenth node;

[0049] The twelfth control sub-circuit includes a twenty-second transistor, a gate of the twenty-second transistor is coupled to the third clock signal input terminal, a first electrode of the twenty-second transistor is coupled to the eleventh node, and a second electrode of the twenty-second transistor is coupled to the second gate drive signal output terminal;

[0050] The thirteenth control sub-circuit includes a twenty-third transistor, a gate of the twenty-third transistor is coupled to the second clock signal input terminal, a first electrode of the twenty-third transistor is coupled to the twelfth node, and a second electrode of the twenty-third transistor is coupled to the eleventh node;

[0051] The fourteenth control sub-circuit includes a twenty-fourth transistor, a gate of the twenty-fourth transistor is coupled to the second start signal input terminal, a first electrode of the twenty-fourth transistor is coupled to the second level signal input terminal, and a second electrode of the twenty-fourth transistor is coupled to the twelfth node;

[0052] The voltage stabilizing circuit includes a capacitor structure, a first end of the capacitor structure is coupled to the ground signal input terminal, and a second end of the capacitor structure is coupled to the second gate drive signal output terminal;

[0053] The nineteenth transistor, the twenty-first transistor, and the twenty-second transistor include P-type transistors, and the twentieth transistor, the twenty-third transistor, and the twenty-fourth transistor include N-type transistors.

[0054] Optionally, the display panel further includes a second clock signal line, a third clock signal line, a fourth clock signal line and a fifth clock signal line;

[0055] The display panel includes a plurality of cascaded second-type shift registers, wherein a second start signal input terminal coupled to a first-stage second-type shift register is coupled to a second frame start signal line in the display panel; a second start signal input terminal coupled to an n+1-th-stage second-type shift register is coupled to a second gate drive signal output terminal of an n-th-stage second-type shift register, where n is an integer greater than or equal to 1;

[0056] The cascaded multiple second-type shift registers are divided into multiple shift register groups, each shift register group includes two adjacent stages of shift registers, and in each shift register group, the second clock signal input terminal coupled to the previous stage shift register is coupled to the second clock signal line, the third clock signal input terminal coupled to the previous stage shift register is coupled to the third clock signal line, the second clock signal input terminal coupled to the next stage shift register is coupled to the fourth clock signal line, and the third clock signal input terminal coupled to the next stage shift register is coupled to the fifth clock signal line.

[0057] Optionally, the orthographic projection of the second shift register on the base substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line and the fifth clock signal line on the base substrate.

[0058] The technical solution provided by this utility model eliminates the secondary steps and noise peaks in the gate drive signal output by the shift register. When this shift register is applied to display products, the display products will not experience bright lines caused by premature pixel row activation after undergoing reliability testing in high temperature and high humidity environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0060] Figure 1 A schematic diagram of a first module of a shift register provided in an embodiment of the present utility model;

[0061] Figure 2 A schematic diagram of a second module of a shift register provided in an embodiment of the present utility model;

[0062] Figure 3 A first circuit diagram of a shift register provided by an embodiment of the present utility model;

[0063] Figure 4 For Figure 3 Corresponding timing diagram;

[0064] Figure 5 A schematic diagram of a first layout of a display panel provided by an embodiment of the present utility model;

[0065] Figure 6 A schematic diagram of the layout of the shift register and signal lines of the display panel provided by an embodiment of the present utility model;

[0066] Figure 7 A schematic diagram of a third module of the shift register provided in an embodiment of the present utility model;

[0067] Figure 8 A schematic diagram of a fourth module of a shift register provided in an embodiment of the present utility model;

[0068] Figure 9 A schematic diagram of a fifth module of a shift register provided in an embodiment of the present utility model;

[0069] Figure 10 A schematic diagram of a sixth module of a shift register provided in an embodiment of the present utility model;

[0070] Figure 11 A second circuit diagram of a shift register provided by an embodiment of the present utility model;

[0071] Figure 12 A third circuit diagram of a shift register provided by an embodiment of the present utility model;

[0072] Figure 13 For Figure 11 and Figure 12 Corresponding timing diagram. DETAILED DESCRIPTION

[0073] In order to further illustrate the shift register, gate driving circuit and display panel provided by the embodiments of the present invention, a detailed description is given below with reference to the accompanying drawings.

[0074] See also Figure 1 , an embodiment of the utility model provides a shift register, comprising:

[0075] The first node control circuit 10 is coupled to the first node n1, the first start signal input terminal STV1, the first clock signal input terminal CLK, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; and is configured to control the electrical connection between the first node n1 and the first level signal input terminal VGL and the electrical connection between the first node n1 and the second level signal input terminal VGH to be opened or closed under the control of the first start signal input terminal STV1 and the first clock signal input terminal CLK;

[0076] a second node control circuit 20, coupled to the second node n2, the third node n3, the first gate drive signal output terminal OUT1, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; and configured to control, under the control of the potential of the third node n3 and the first gate drive signal output from the first gate drive signal output terminal OUT1, to connect or disconnect the electrical connection between the second node n2 and the first level signal input terminal VGL, and to connect or disconnect the electrical connection between the second node n2 and the second level signal input terminal VGH;

[0077] a first output control circuit 50, coupled to the first gate drive signal output terminal OUT1, the first node n1, the second node n2, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; and configured to control the electrical connection between the first gate drive signal output terminal OUT1 and the first level signal input terminal VGL and the electrical connection between the first gate drive signal output terminal OUT1 and the second level signal input terminal VGH to be opened or closed, under the control of the potential of the first node n1 and the potential of the second node n2;

[0078] a third node control circuit 30 coupled to the third node n3, the fourth node n4, the first clock signal input terminal CLK, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; and configured to control, under control of the potential of the fourth node n4 and the first clock signal inputted by the first clock signal input terminal CLK, to make or break the electrical connection between the third node n3 and the first level signal input terminal VGL, and to make or break the electrical connection between the third node n3 and the second level signal input terminal VGH;

[0079] The fourth node control circuit 40 is coupled to the fourth node n4, the first start signal input terminal STV1, the first level signal input terminal VGL and the second level signal input terminal VGH, respectively; and is used to control the conduction or disconnection of the electrical connection between the fourth node n4 and the first level signal input terminal VGL, and to control the conduction or disconnection of the electrical connection between the fourth node n4 and the second level signal input terminal VGH, under the control of the first start signal input terminal STV1.

[0080] like Figure 4 As shown, exemplarily, the period of the first clock signal inputted by the first clock signal input terminal CLK is 4H, and the pulse width of the first clock signal is 2H, but it is not limited thereto.

[0081] Exemplarily, the first level signal input to the first level signal input terminal VGL is a low level signal, and the second level signal input to the second level signal input terminal VGH is a high level signal, but the present invention is not limited thereto.

[0082] According to the specific structure of the shift register described above, in the shift register provided by the embodiment of the present invention, the first start signal inputted through the first start signal input terminal STV1 and the first clock signal inputted through the first clock signal input terminal CLK can control the first node control circuit 10, thereby controlling the potential of the first node n1; the first clock signal and the fourth node n4 can control the third node control circuit, thereby controlling the potential of the third node n3; the first gate drive signal outputted from the third node n3 and the first gate drive signal output terminal OUT1 can control the second node control circuit, thereby controlling the potential of the second node n2; the first node n1 and the second node n2 can control the first output control circuit, thereby controlling the first gate drive signal output terminal OUT1 to output a stable first gate drive signal. The various circuit structures included in the shift register can be implemented using transistors without the need to introduce a capacitor structure, thereby avoiding the secondary steps and noise peak problems caused by the capacitor structure. In this way, when the shift register provided by the embodiment of the present invention is applied to a display product, since the first gate drive signal does not have secondary steps and noise peaks, after the display product undergoes reliability tests such as high temperature and high humidity, even if the transistor in the pixel circuit has a threshold voltage drift, the first gate drive signal will not cause the pixel row to be turned on prematurely, thereby avoiding the problem of bright lines on the display.

[0083] Moreover, the shift register provided in the above embodiment only needs to be connected to one clock signal input terminal (the first clock signal input terminal CLK), that is, only one clock signal line connected to the clock signal input terminal is needed to provide the clock signal. This not only helps to simplify the layout complexity and border width of the display product to which the shift register is applied, but also can reduce signal interference and product power consumption.

[0084] like Figure 2 As shown, in some embodiments, the first node control circuit 10 includes a first control subcircuit 101 and a second control subcircuit 102;

[0085] The first control sub-circuit 101 is coupled to the first start signal input terminal STV1, the second level signal input terminal VGH, the fifth node n5, and the first node n1, respectively; and is configured to control the electrical connection between the first node n1 and the second level signal input terminal VGH, and the electrical connection between the first node n1 and the fifth node n5, under the control of the first start signal input terminal STV1.

[0086] The second control sub-circuit 102 is coupled to the first clock signal input terminal CLK, the second level signal input terminal VGH, the first node n1, the fifth node n5, and the first level signal input terminal VGL, respectively. The second control sub-circuit 102 is configured to control the electrical connection between the second level signal input terminal VGH and the first node n1 and the electrical connection between the first level signal input terminal VGL and the fifth node n5 under the control of the first clock signal input terminal CLK.

[0087] The second node control circuit 20 controls a third control subcircuit 201 and a fourth control subcircuit 202;

[0088] The third control sub-circuit 201 is coupled to the third node n3, the second level signal input terminal VGH, the sixth node n6, and the second node n2, respectively; and is configured to control the electrical connection between the second level signal input terminal VGH and the second node n2 and the electrical connection between the sixth node n6 and the second node n2 under the control of the potential of the third node n3.

[0089] The fourth control sub-circuit 202 is coupled to the first gate drive signal output terminal OUT1, the second level signal input terminal VGH, the second node n2, the sixth node n6, and the first level signal input terminal VGL, respectively; and is configured to control the electrical connection between the second level signal input terminal VGH and the second node n2 and the electrical connection between the sixth node n6 and the first level signal input terminal VGL under the control of the first gate drive signal output by the first gate drive signal output terminal OUT1.

[0090] The first output control circuit 50 includes a fifth control subcircuit 501 and a sixth control subcircuit 502;

[0091] The fifth control sub-circuit 501 is coupled to the first node n1, the second level signal input terminal VGH, the first gate drive signal output terminal OUT1, and the seventh node n7, respectively; and is configured to control, under the control of the potential of the first node n1, to connect or disconnect the electrical connection between the second level signal input terminal VGH and the first gate drive signal output terminal OUT1, and to connect or disconnect the electrical connection between the seventh node n7 and the first gate drive signal output terminal OUT1;

[0092] The sixth control sub-circuit 502 is coupled to the second node n2, the second level signal input terminal VGH, the first gate drive signal output terminal OUT1, the seventh node n7, and the first level signal input terminal VGL, respectively; and is configured to control, under the control of the potential of the second node n2, to connect or disconnect the electrical connection between the second level signal input terminal VGH and the first gate drive signal output terminal OUT1, and to connect or disconnect the electrical connection between the seventh node n7 and the first level signal input terminal VGL;

[0093] The third node control circuit 30 includes a seventh control subcircuit 301 and an eighth control subcircuit 302;

[0094] The seventh control sub-circuit 301 is coupled to the fourth node n4, the second level signal input terminal VGH, the third node n3, and the eighth node n8, respectively; and is configured to control, under the control of the potential of the fourth node n4, to connect or disconnect the electrical connection between the second level signal input terminal VGH and the third node n3, and to connect or disconnect the electrical connection between the third node n3 and the eighth node n8;

[0095] The eighth control sub-circuit 302 is coupled to the first clock signal input terminal CLK, the second level signal input terminal VGH, the third node n3, the eighth node n8 and the first level signal input terminal VGL, respectively; and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal VGH and the third node n3, and to control the conduction or disconnection of the electrical connection between the eighth node n8 and the first level signal input terminal VGL, under the control of the first clock signal input by the first clock signal input terminal CLK.

[0096] like Figure 2 and Figure 3 As shown, illustratively, the first control sub-circuit 101 includes a first transistor T1 and a third transistor T3; the gate of the first transistor T1 is coupled to the first start signal input terminal STV1, the first electrode of the first transistor T1 is coupled to the second level signal input terminal VGH, and the second electrode of the first transistor T1 is coupled to the first node n1; the gate of the third transistor T3 is coupled to the first start signal input terminal STV1, the first electrode of the third transistor T3 is coupled to the fifth node n5, and the second electrode of the third transistor T3 is coupled to the first node n1;

[0097] The second control subcircuit 102 includes a second transistor T2 and a fourth transistor T4; a gate of the second transistor T2 is coupled to the first clock signal input terminal CLK, a first electrode of the second transistor T2 is coupled to the second level signal input terminal VGH, and a second electrode of the second transistor T2 is coupled to the first node n1; a gate of the fourth transistor T4 is coupled to the first clock signal input terminal CLK, a first electrode of the fourth transistor T4 is coupled to the first level signal input terminal VGL, and a second electrode of the fourth transistor T4 is coupled to the fifth node n5;

[0098] The third control subcircuit 201 includes a thirteenth transistor T13 and a fifteenth transistor T15; a gate of the thirteenth transistor T13 is coupled to the third node n3, a first electrode of the thirteenth transistor T13 is coupled to the second level signal line, and a second electrode of the thirteenth transistor T13 is coupled to the second node n2; a gate of the fifteenth transistor T15 is coupled to the third node n3, a first electrode of the fifteenth transistor T15 is coupled to the sixth node n6, and a second electrode of the fifteenth transistor T15 is coupled to the second node n2;

[0099] The fourth control sub-circuit 202 includes a fourteenth transistor T14 and a sixteenth transistor T16; a gate of the fourteenth transistor T14 is coupled to the first gate drive signal output terminal OUT1, a first electrode of the fourteenth transistor T14 is coupled to the second level signal input terminal VGH, and a second electrode of the fourteenth transistor T14 is coupled to the second node n2; a gate of the sixteenth transistor T16 is coupled to the first gate drive signal output terminal OUT1, a first electrode of the sixteenth transistor T16 is coupled to the first level signal input terminal VGL, and a second electrode of the sixteenth transistor T16 is coupled to the sixth node n6;

[0100] The fifth control sub-circuit 501 includes a fifth transistor T5 and a seventh transistor T7, wherein a gate of the fifth transistor T5 is coupled to the first node n1, a first electrode of the fifth transistor T5 is coupled to the second level signal input terminal VGH, and a second electrode of the fifth transistor T5 is coupled to the first gate drive signal output terminal OUT1; a gate of the seventh transistor T7 is coupled to the first node n1, a first electrode of the seventh transistor T7 is coupled to the seventh node n7, and a second electrode of the seventh transistor T7 is coupled to the first gate drive signal output terminal OUT1;

[0101] The sixth control sub-circuit 502 includes a sixth transistor T6 and an eighth transistor T8, wherein a gate of the sixth transistor T6 is coupled to the second node n2, a first electrode of the sixth transistor T6 is coupled to the second level signal input terminal VGH, and a second electrode of the sixth transistor T6 is coupled to the first gate drive signal output terminal OUT1; a gate of the eighth transistor T8 is coupled to the second node n2, a first electrode of the eighth transistor T8 is coupled to the first level signal input terminal VGL, and a second electrode of the eighth transistor T8 is coupled to the seventh node n7;

[0102] The seventh control sub-circuit 301 includes a ninth transistor T9 and an eleventh transistor T11. The gate of the ninth transistor T9 is coupled to the fourth node n4, the first electrode of the ninth transistor T9 is coupled to the second level signal input terminal VGH, and the second electrode of the ninth transistor T9 is coupled to the third node n3. The gate of the eleventh transistor T11 is coupled to the fourth node n4, the first electrode of the eleventh transistor T11 is coupled to the eighth node n8, and the second electrode of the eleventh transistor T11 is coupled to the third node n3.

[0103] The eighth control sub-circuit 302 includes a tenth transistor T10 and a twelfth transistor T12, wherein a gate of the tenth transistor T10 is coupled to the first clock signal input terminal CLK, a first electrode of the tenth transistor T10 is coupled to the second level signal input terminal VGH, and a second electrode of the tenth transistor T10 is coupled to the third node n3; a gate of the twelfth transistor T12 is coupled to the first clock signal input terminal CLK, a first electrode of the twelfth transistor T12 is coupled to the first level signal input terminal VGL, and a second electrode of the twelfth transistor T12 is coupled to the eighth node n8;

[0104] The fourth node control circuit 40 includes a seventeenth transistor T17 and an eighteenth transistor T18, wherein a gate of the seventeenth transistor T17 is coupled to the first start signal input terminal STV1, a first electrode of the seventeenth transistor T17 is coupled to the second level signal input terminal VGH, and a second electrode of the seventeenth transistor T17 is coupled to the fourth node n4; a gate of the eighteenth transistor T18 is coupled to the first start signal input terminal STV1, a first electrode of the eighteenth transistor T18 is coupled to the first level signal input terminal VGL, and a second electrode of the eighteenth transistor T18 is coupled to the fourth node n4;

[0105] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 include P-type transistors; the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, the fifteenth transistor T15, and the sixteenth transistor T16 include N-type transistors.

[0106] The shift register is configured to include the above-mentioned structure, so that the shift register can be formed into a CMOS circuit structure, thereby achieving effects such as strong output capability, good stability, and low power consumption. Moreover, the CMOS circuit structure can usually achieve stronger output capability using transistors with a smaller aspect ratio. While improving the driving effect, it is beneficial to further reduce the layout space occupied by the shift register and further narrow the border width of the display product to which it is applied.

[0107] like Figure 5 As shown, when the shift register is applied to a display panel, the display area AA of the display panel includes sub-pixels distributed in an array, and the shift register may specifically include: EM GOA, N-gate GOA, Rest-P GOA and Rest-H GOA; EM GOA is used to provide a gate drive signal for light-emitting control to the corresponding sub-pixel row; N-gateGOA is used to provide a high-level valid gate drive signal to the corresponding sub-pixel row; Rest-P GOA and Rest-H GOA are used to provide a gate drive signal for resetting to the corresponding sub-pixel row, wherein Rest-P GOA can provide a gate drive signal to a reset transistor for resetting a drive transistor electrode in a sub-pixel drive circuit, and Rest-H GOA can provide a gate drive signal to a reset transistor for resetting an anode in a sub-pixel drive circuit, but is not limited to this.

[0108] like Figure 3 and Figure 4 As shown, the working process of the shift register provided by the above embodiment is as follows:

[0109] In the P1 period, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on. The potential of the first node n1 is the same as the second level signal input by the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on and the fifth transistor T5 is turned off. Since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is low, the fourteenth transistor T14 is controlled to be turned on and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be high, and the eighth transistor T8 is turned on, controlling the potential of the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input by the first level signal input terminal VGL, that is, the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period is low.

[0110] It is worth noting that in the P1 period, since the first start signal input by the first start signal input terminal STV1 has a low level, the seventeenth transistor T17 is turned on and the eighteenth transistor T18 is turned off, and the potential of the fourth node n4 is controlled to be the same as the second level signal input by the second level signal input terminal VGH, that is, the potential of the fourth node n4 is high, thereby controlling the eleventh transistor T11 to be turned on and the ninth transistor T9 to be turned off. Since the first clock signal input by the first clock signal input terminal CLK is high, the twelfth transistor T12 is controlled to be turned on and the tenth transistor T10 is turned off, so that the potential of the third node n3 is the same as the first level signal, that is, the potential of the third node n3 is low, thereby controlling the thirteenth transistor T13 to be turned on and the fifteenth transistor T15 to be turned off, thereby stabilizing the potential of the second node n2 at a high level.

[0111] In the P2 period, the first transistor T1 is turned off, the third transistor T3 is turned on, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. The potential of the first node n1 is the same as the second level signal input by the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on and the fifth transistor T5 is turned off. Since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is low, the fourteenth transistor T14 is controlled to be turned on and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be high, and the eighth transistor T8 is turned on, controlling the potential of the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input by the first level signal input terminal VGL, that is, the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period is low.

[0112] It is worth noting that in the P2 period, since the first start signal input by the first start signal input terminal STV1 has a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, and the potential of the fourth node n4 is controlled to be the same as the first level signal input by the first level signal input terminal VGL, that is, the potential of the fourth node n4 is low, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on. Since the first clock signal input by the first clock signal input terminal CLK is low, the twelfth transistor T12 is controlled to be turned off and the tenth transistor T10 is turned on, so that the potential of the third node n3 is the same as the second level signal, that is, the potential of the third node n3 is high, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on, thereby controlling the potential of the second node n2 to remain the same as the P1 period.

[0113] During the P3 period, the first transistor T1 is turned off and the third transistor T3 is turned on. The potential of the first node n1 is opposite to the first clock signal input by the first clock signal input terminal CLK, that is, the potential of the first node n1 is at a low level, which controls the fifth transistor T5 to be turned on and the seventh transistor T7 to be turned off. At this time, the first gate drive signal output by the first gate drive signal output terminal OUT1 is at a high level.

[0114] It is worth noting that in the P3 period, since the first start signal input by the first start signal input terminal STV1 has a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, and the potential of the fourth node n4 is controlled to be the same as the first level signal input by the first level signal input terminal VGL, that is, the potential of the fourth node n4 is low, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on; since the first clock signal input by the first clock signal input terminal CLK is high, the twelfth transistor T12 is controlled to be turned on and the tenth transistor T10 is turned off, so that the potential of the third node n3 is the same as the second level signal, that is, the potential of the third node n3 is high, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on; since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is low, the fourteenth transistor T14 is controlled to be turned on and the sixteenth transistor T16 is turned off, thereby controlling the potential of the second node n2 to be high and the eighth transistor T8 to be turned on.

[0115] During period P4, the first transistor T1 is turned off, the third transistor T3 is turned on, and the potential of the first node n1 is opposite to the first clock signal inputted by the first clock signal input terminal CLK. That is, the potential of the first node n1 alternates between a high level and a low level, controlling the fifth transistor T5 to alternately turn on and off, and the seventh transistor T7 to alternately turn off and on.

[0116] It is worth noting that in the P4 period, since the first start signal input by the first start signal input terminal STV1 has a high level, the seventeenth transistor T17 is turned off and the eighteenth transistor T18 is turned on, controlling the potential of the fourth node n4 to be the same as the first level signal input by the first level signal input terminal VGL, that is, the potential of the fourth node n4 is low, thereby controlling the eleventh transistor T11 to be turned off and the ninth transistor T9 to be turned on. In this way, even if the first clock signal input by the first clock signal input terminal CLK alternates between a high level and a low level, the potential of the third node n3 can only be the same as the second level signal, that is, the potential of the third node n3 is high, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on; since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is a high level, the fourteenth transistor T14 is controlled to be turned off and the sixteenth transistor T16 is turned on, thereby controlling the potential of the second node n2 to be a low level and the eighth transistor T8 to be turned off. At this time, the first gate drive signal output by the first gate drive signal output terminal OUT1 remains at a high level.

[0117] In the P5 phase, at least one of the working processes of P3 and P4 is repeated, and the first gate driving signal outputted by the first gate driving signal output terminal OUT1 is kept at a high level.

[0118] In the P6 phase, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. The potential of the first node n1 is the same as the second level signal input by the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on and the fifth transistor T5 is turned off. Since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is high, the fourteenth transistor T14 is turned off and the sixteenth transistor T16 is turned on. Since the first start signal input by the first start signal input terminal STV1 is low, the seventeenth transistor T17 is turned on and the eighteenth transistor T18 is turned off, controlling the fourth node n4. The potential of the fourth node n4 is the same as the second-level signal input by the second-level signal input terminal VGH, that is, the potential of the fourth node n4 is high, thereby controlling the eleventh transistor T11 to be turned on and the ninth transistor T9 to be turned off. Since the first clock signal input by the first clock signal input terminal CLK is low, the twelfth transistor T12 is controlled to be turned off and the tenth transistor T10 is turned on, so that the potential of the third node n3 is the same as the second-level signal, that is, the potential of the third node n3 is high, thereby controlling the thirteenth transistor T13 to be turned off and the fifteenth transistor T15 to be turned on, thereby stabilizing the potential of the second node n2 at a low level, the eighth transistor T8 is turned off, and the first gate drive signal output by the first gate drive signal output terminal OUT1 remains at a high level.

[0119] In the P7 period, the first transistor T1 is turned on, the third transistor T3 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on. The potential of the first node n1 is the same as the second level signal input by the second level signal input terminal VGH, that is, the potential of the first node n1 is high. At this time, the seventh transistor T7 is turned on and the fifth transistor T5 is turned off. Since the first gate drive signal output by the first gate drive signal output terminal OUT1 in the previous period is high, the fourteenth transistor T14 is controlled to be turned off and the sixteenth transistor T16 is turned on; since the first start signal input by the first start signal input terminal STV1 is low, the seventeenth transistor T17 is turned on and the eighteenth transistor T18 is turned off, controlling the potential of the fourth node n4 to be the same as the second level signal input by the second level signal input terminal VGH, that is, the fourth The potential of the node n4 is at a high level, thereby controlling the eleventh transistor T11 to be turned on and the ninth transistor T9 to be turned off. Since the first clock signal input by the first clock signal input terminal CLK is at a high level, the twelfth transistor T12 is controlled to be turned on and the tenth transistor T10 is turned off, so that the potential of the third node n3 is the same as the first level signal, that is, the potential of the third node n3 is at a low level, thereby controlling the thirteenth transistor T13 to be turned on and the fifteenth transistor T15 to be turned off, controlling the potential of the second node n2 to be a high level, and turning on the eighth transistor T8, controlling the potential of the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period to be the same as the first level signal input by the first level signal input terminal VGL, that is, the first gate drive signal output by the first gate drive signal output terminal OUT1 in the current period is a low level.

[0120] An embodiment of the present invention also provides a gate drive circuit, comprising a cascade of multiple shift registers provided by the above embodiments; the first start signal input terminal STV1 coupled to the first stage shift register is coupled to the first frame start signal line; the first start signal input terminal STV1 coupled to the n+1 stage shift register is coupled to the first gate drive signal output terminal OUT1 of the n stage shift register, where n is an integer greater than or equal to 1.

[0121] Exemplarily, in the cascaded multiple shift registers, the first clock signal input terminal CLK coupled to each shift register is connected to the same first clock signal line CLK′.

[0122] Exemplarily, in different gate drive circuits formed by cascading different shift registers (such as EM GOA, N-gate GOA, Rest-P GOA and Rest-HGOA), the start signal input terminal coupled to the first-stage shift register in each type of gate drive circuit is coupled to the corresponding first frame start signal line; or the start signal input terminal coupled to the first-stage shift register in each type of gate drive circuit is coupled to the same first frame start signal line.

[0123] In the gate drive circuit provided by the above embodiment, the time width of the shift of the first gate drive signal output by the adjacent level shift register is the low level time width of the first clock signal. By setting the low level time width of the first clock signal to 2H, the time width of the shift of the first gate drive signal output by the adjacent level shift register can be realized to be 2H.

[0124] like Figure 5 and Figure 6 As shown, an embodiment of the present invention also provides a display panel, including the gate drive circuit provided by the above embodiment, and the display panel also includes a first clock signal line, and the positive projection of at least part of the shift register in the gate drive circuit on the base substrate of the display panel at least partially overlaps with the positive projection of the first clock signal line on the base substrate.

[0125] Exemplarily, the display panel includes an active matrix organic light emitting diode display panel, but is not limited thereto.

[0126] Exemplarily, the display panel includes a display area AA and a peripheral area located around the display area AA, the peripheral area including a left border area and a right border area that are relatively arranged, for example: EM GOA and N-gate GOA are located in the left border area, and Rest-P GOA and Rest-H GOA are located in the right border area, but is not limited to this.

[0127] Exemplarily, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the EM GOA on the substrate, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the N-gate GOA on the substrate, the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the Rest-P GOA on the substrate, and the orthographic projection of the first clock signal line CLK' on the substrate at least partially overlaps with the orthographic projection of the Rest-H GOA on the substrate.

[0128] Exemplarily, along the extending direction of the first clock signal line CLK', the EM GOAs and the N-gate GOAs are alternately arranged. Along the extending direction of the first clock signal line CLK', the Rest-P GOAs and the Rest-H GOAs are alternately arranged.

[0129] The display panel can be applied to a display device, which can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0130] The above-mentioned setting of the orthographic projection of at least part of the shift register in the gate drive circuit on the base substrate of the display panel at least partially overlaps with the orthographic projection of the first clock signal line on the base substrate, which is beneficial to reducing the overall layout space occupied by the gate drive circuit and the signal line, and at the same time is beneficial to reducing the difficulty of connecting the gate drive circuit and the signal line.

[0131] like Figure 7 and Figure 8 As shown, in some embodiments, the display panel further includes a second shift register, and the second shift register includes:

[0132] The second output control circuit 60 is coupled to the second start signal input terminal, the second clock signal input terminal (e.g., CK1, CK3), the third clock signal input terminal (e.g., CK2, CK4), the first level signal input terminal VGL, and the second gate drive signal output terminal, respectively; and is configured to control the electrical connection between the first level signal input terminal VGL and the second gate drive signal output terminal under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0133] The third output control circuit 70 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal VGH, and the second gate drive signal output terminal, respectively; and is configured to control the electrical connection between the second level signal input terminal VGH and the second gate drive signal output terminal to be conducted or disconnected under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0134] The voltage stabilizing circuit 80 is coupled to the ground signal input terminal and the second gate driving signal output terminal respectively.

[0135] It should be noted that Figure 7 The figure shows the nth stage shift register, whose second start signal input terminal is connected to the second gate drive signal output terminal gatep-(n-1) of the n-1th stage shift register, and the second gate drive signal output terminal of the nth stage shift register is gatep-(n).

[0136] Figure 8The figure shows the n+1th stage shift register, whose second start signal input terminal is connected to the second gate drive signal output terminal gatep-(n) of the nth stage shift register, and the second gate drive signal output terminal of the n+1th stage shift register is gatep-(n+1).

[0137] Exemplarily, the second shift register includes a P-gate GOA, but is not limited thereto. The P-gate GOA is configured to provide an active-low gate drive signal to the corresponding subpixel row. The P-gate GOAs are arranged sequentially along the extension direction of the first clock signal line. In the left and right border regions, the P-gate GOA is closer to the display area than the other GOAs.

[0138] Exemplarily, the second clock signal inputted by the second clock signal input terminal and the third clock signal inputted by the third clock signal input terminal have the same pulse width and different phases.

[0139] Exemplarily, the period of the second clock signal and the third clock signal is 1H, but is not limited thereto.

[0140] Exemplarily, the first level signal input to the first level signal input terminal VGL is a low level signal, and the second level signal input to the second level signal input terminal VGH is a high level signal, but the present invention is not limited thereto.

[0141] In the second shift register provided in the above embodiment, the second gate drive signal output terminal can be controlled to output the second gate drive signal via the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal. The second shift register provided in the above embodiment is connected to two clock signal input terminals (the second clock signal input terminal and the third clock signal input terminal). When the second shift register is cascaded to form a gate drive circuit, the gate drive circuit can be connected to a total of four clock signal lines, which is beneficial for reducing the loading of the clock signal lines and improving the stability of the output gate drive signal.

[0142] In the second shift register provided by the above embodiment, the voltage stabilizing circuit 80 is provided to further improve the stability of the output gate driving signal.

[0143] like Figures 7 to 10 As shown, in some embodiments, the second output control circuit 60 includes:

[0144] a ninth control sub-circuit 66, coupled to the third clock signal input terminal, the ninth node n9, and the second gate drive signal output terminal, respectively, for controlling, under control of a third clock signal inputted from the third clock signal input terminal, whether to electrically connect or disconnect the ninth node n9 and the second gate drive signal output terminal;

[0145] a tenth control sub-circuit 61, coupled to the second clock signal input terminal, the ninth node n9, and the tenth node n10, respectively, and configured to control the electrical connection between the ninth node n9 and the tenth node n10 to be opened or closed under the control of the second clock signal inputted by the second clock signal input terminal;

[0146] an eleventh control sub-circuit 62, coupled to the second start signal input terminal, the tenth node n10, and the first level signal input terminal VGL, respectively, for controlling, under the control of a second start signal inputted from the second start signal input terminal, to switch on or off the electrical connection between the tenth node n10 and the first level signal input terminal VGL;

[0147] a twelfth control sub-circuit 63, coupled to the third clock signal input terminal, the eleventh node n11, and the second gate drive signal output terminal, respectively, for controlling, under the control of the third clock signal inputted from the third clock signal input terminal, to switch on or off the electrical connection between the eleventh node n11 and the second gate drive signal output terminal;

[0148] a thirteenth control sub-circuit 64, coupled to the second clock signal input terminal, the eleventh node n11, and the twelfth node n12, respectively, for controlling, under the control of the second clock signal inputted from the second clock signal input terminal, to switch on or off the electrical connection between the eleventh node n11 and the twelfth node n12;

[0149] The fourteenth control sub-circuit 65 is coupled to the second start signal input terminal, the twelfth node n12 and the second level signal input terminal VGH, respectively, and is used to control the conduction or disconnection of the electrical connection between the twelfth node n12 and the second level signal input terminal VGH under the control of the second start signal input terminal.

[0150] Exemplarily, the ninth control sub-circuit 66 includes a nineteenth transistor T19, a gate of the nineteenth transistor T19 coupled to the third clock signal input terminal, a first electrode of the nineteenth transistor T19 coupled to the ninth node n9, and a second electrode of the nineteenth transistor T19 coupled to the second gate drive signal output terminal;

[0151] The tenth control sub-circuit 61 includes a twentieth transistor T20, wherein a gate of the twentieth transistor T20 is coupled to the second clock signal input terminal, a first electrode of the twentieth transistor T20 is coupled to the tenth node n10, and a second electrode of the twentieth transistor T20 is coupled to the ninth node n9;

[0152] The eleventh control sub-circuit 62 includes a twenty-first transistor T21, wherein a gate of the twenty-first transistor T21 is coupled to the second start signal input terminal, a first electrode of the twenty-first transistor T21 is coupled to the first level signal input terminal VGL, and a second electrode of the twenty-first transistor T21 is coupled to the tenth node n10;

[0153] The twelfth control sub-circuit 63 includes a twenty-second transistor T22, a gate of the twenty-second transistor T22 is coupled to the third clock signal input terminal, a first electrode of the twenty-second transistor T22 is coupled to the eleventh node n11, and a second electrode of the twenty-second transistor T22 is coupled to the second gate drive signal output terminal;

[0154] The thirteenth control sub-circuit 64 includes a twenty-third transistor T23, a gate of the twenty-third transistor T23 is coupled to the second clock signal input terminal, a first electrode of the twenty-third transistor T23 is coupled to the twelfth node n12, and a second electrode of the twenty-third transistor T23 is coupled to the eleventh node n11;

[0155] The fourteenth control sub-circuit 65 includes a twenty-fourth transistor T24, wherein a gate of the twenty-fourth transistor T24 is coupled to the second start signal input terminal, a first electrode of the twenty-fourth transistor T24 is coupled to the second level signal input terminal VGH, and a second electrode of the twenty-fourth transistor T24 is coupled to the twelfth node n12;

[0156] The voltage stabilizing circuit 80 includes a capacitor structure C, a first end of the capacitor structure C is coupled to the ground signal input terminal, and a second end of the capacitor structure C is coupled to the second gate drive signal output terminal;

[0157] The nineteenth transistor T19 , the twenty-first transistor T21 , and the twenty-second transistor T22 include P-type transistors, and the twentieth transistor T20 , the twenty-third transistor T23 , and the twenty-fourth transistor T24 include N-type transistors.

[0158] Exemplarily, the capacitor structure C may use a capacitor of 10 pC, but is not limited thereto.

[0159] The second shift register is provided to include the above-mentioned structure, so that the second shift register can be formed into a CMOS circuit structure, thereby achieving effects such as strong output capability, good stability, and low power consumption. Moreover, the CMOS circuit structure can usually achieve stronger output capability using transistors with a smaller aspect ratio. While improving the driving effect, it is beneficial to further reduce the layout space occupied by the shift register and further narrow the border width of the display product to which it is used.

[0160] like Figures 11 to 13 As shown, the working process of the shift register provided by the above embodiment is as follows:

[0161] In the m1 stage, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23 are all turned on, the twenty-fourth transistor T24 is turned off, and the second gate drive signal output by the second gate drive signal output terminal (e.g., gatep-(n+1)) is the same as the first level signal input by the first level signal input terminal VGL, that is, the second gate drive signal is a low level.

[0162] In the m2 phase, the nineteenth transistor T19 and the twenty-second transistor T22 are both turned on, the twentieth transistor T20 and the twenty-third transistor T23 are both turned off, and the second gate driving signal maintains a low level.

[0163] In the m3 stage, the nineteenth transistor T19, the twentieth transistor T20, the twenty-fourth transistor T24, the twenty-second transistor T22, and the twenty-third transistor T23 are all turned on, the twenty-first transistor T21 is turned off, and the second gate drive signal output by the second gate drive signal output terminal (e.g., gatep-(n+1)) is the same as the second level signal input by the second level signal input terminal VGH, that is, the second gate drive signal is a high level.

[0164] like Figure 6 As shown, in some embodiments, the display panel further includes a second clock signal line CK1 ', a third clock signal line CK2 ', a fourth clock signal line CK3 ', and a fifth clock signal line CK4 ';

[0165] The display panel includes a plurality of cascaded second-type shift registers, wherein a second start signal input terminal coupled to a first-stage second-type shift register is coupled to a second frame start signal line in the display panel; a second start signal input terminal coupled to an n+1-th-stage second-type shift register is coupled to a second gate drive signal output terminal of an n-th-stage second-type shift register, where n is an integer greater than or equal to 1;

[0166] The cascaded multiple second-type shift registers are divided into multiple shift register groups, each shift register group includes two adjacent stages of shift registers, and in each shift register group, the second clock signal input terminal coupled to the previous stage shift register is coupled to the second clock signal line CK1', the third clock signal input terminal coupled to the previous stage shift register is coupled to the third clock signal line CK2', the second clock signal input terminal coupled to the next stage shift register is coupled to the fourth clock signal line CK3', and the third clock signal input terminal coupled to the next stage shift register is coupled to the fifth clock signal line CK4'.

[0167] Exemplarily, the second clock signal input by the second clock signal line CK1', the third clock signal input by the third clock signal line CK2', the fourth clock signal input by the fourth clock signal line CK3', and the fifth clock signal input by the fifth clock signal line CK4' have the same pulse width and different phases.

[0168] In the gate drive circuit provided by the above embodiment, the time width of the shift of the second gate drive signal output by the adjacent level shift register is the cycle width of the clock signal. By setting the cycle width of the clock signal to 1H, the time width of the shift of the second gate drive signal output by the adjacent level shift register can be realized to be 1H.

[0169] The second shift register provided in the above embodiment is connected to two clock signal input terminals (a second clock signal input terminal and a third clock signal input terminal). When the second shift register is cascaded to form a gate drive circuit, the gate drive circuit can be connected to a total of four clock signal lines, which is beneficial to reducing the loading of the clock signal line and improving the stability of the output gate drive signal.

[0170] In some embodiments, the orthographic projection of the second shift register on the base substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line CK1', the third clock signal line CK2', the fourth clock signal line CK3' and the fifth clock signal line CK4' on the base substrate.

[0171] The above configuration is not only conducive to reducing the overall layout space occupied by the gate drive circuit and signal lines formed by the second type of shift register, but also conducive to reducing the difficulty of connecting the gate drive circuit and the signal lines.

[0172] like Figures 6 to 13 As shown, the embodiment of the present invention further provides a shift register, the shift register comprising:

[0173] The second output control circuit 60 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal VGL, and the second gate drive signal output terminal, respectively; and is configured to control the electrical connection between the first level signal input terminal VGL and the second gate drive signal output terminal to be conducted or disconnected under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0174] The third output control circuit 70 is coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal VGH, and the second gate drive signal output terminal, respectively; and is configured to control the electrical connection between the second level signal input terminal VGH and the second gate drive signal output terminal to be conducted or disconnected under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal.

[0175] The voltage stabilizing circuit 80 is coupled to the ground signal input terminal and the second gate driving signal output terminal respectively.

[0176] In some embodiments, the second output control circuit 60 includes:

[0177] a ninth control sub-circuit 66, coupled to the third clock signal input terminal, the ninth node n9, and the second gate drive signal output terminal, respectively, for controlling, under control of a third clock signal inputted from the third clock signal input terminal, whether to electrically connect or disconnect the ninth node n9 and the second gate drive signal output terminal;

[0178] a tenth control sub-circuit 61, coupled to the second clock signal input terminal, the ninth node n9, and the tenth node n10, respectively, and configured to control the electrical connection between the ninth node n9 and the tenth node n10 to be opened or closed under the control of the second clock signal inputted by the second clock signal input terminal;

[0179] an eleventh control sub-circuit 62, coupled to the second start signal input terminal, the tenth node n10, and the first level signal input terminal VGL, respectively, for controlling, under the control of a second start signal inputted from the second start signal input terminal, to switch on or off the electrical connection between the tenth node n10 and the first level signal input terminal VGL;

[0180] a twelfth control sub-circuit 63, coupled to the third clock signal input terminal, the eleventh node n11, and the second gate drive signal output terminal, respectively, for controlling, under the control of the third clock signal inputted from the third clock signal input terminal, to switch on or off the electrical connection between the eleventh node n11 and the second gate drive signal output terminal;

[0181] a thirteenth control sub-circuit 64, coupled to the second clock signal input terminal, the eleventh node n11, and the twelfth node n12, respectively, for controlling, under the control of the second clock signal inputted from the second clock signal input terminal, to switch on or off the electrical connection between the eleventh node n11 and the twelfth node n12;

[0182] The fourteenth control sub-circuit 65 is coupled to the second start signal input terminal, the twelfth node n12 and the second level signal input terminal VGH, respectively, and is used to control the conduction or disconnection of the electrical connection between the twelfth node n12 and the second level signal input terminal VGH under the control of the second start signal input terminal.

[0183] In some embodiments, the ninth control sub-circuit 66 includes a nineteenth transistor T19, a gate of the nineteenth transistor T19 is coupled to the third clock signal input terminal, a first electrode of the nineteenth transistor T19 is coupled to the ninth node n9, and a second electrode of the nineteenth transistor T19 is coupled to the second gate drive signal output terminal;

[0184] The tenth control sub-circuit 61 includes a twentieth transistor T20, wherein a gate of the twentieth transistor T20 is coupled to the second clock signal input terminal, a first electrode of the twentieth transistor T20 is coupled to the tenth node n10, and a second electrode of the twentieth transistor T20 is coupled to the ninth node n9;

[0185] The eleventh control sub-circuit 62 includes a twenty-first transistor T21, wherein a gate of the twenty-first transistor T21 is coupled to the second start signal input terminal, a first electrode of the twenty-first transistor T21 is coupled to the first level signal input terminal VGL, and a second electrode of the twenty-first transistor T21 is coupled to the tenth node n10;

[0186] The twelfth control sub-circuit 63 includes a twenty-second transistor T22, a gate of the twenty-second transistor T22 is coupled to the third clock signal input terminal, a first electrode of the twenty-second transistor T22 is coupled to the eleventh node n11, and a second electrode of the twenty-second transistor T22 is coupled to the second gate drive signal output terminal;

[0187] The thirteenth control sub-circuit 64 includes a twenty-third transistor T23, a gate of the twenty-third transistor T23 is coupled to the second clock signal input terminal, a first electrode of the twenty-third transistor T23 is coupled to the twelfth node n12, and a second electrode of the twenty-third transistor T23 is coupled to the eleventh node n11;

[0188] The fourteenth control sub-circuit 65 includes a twenty-fourth transistor T24, wherein a gate of the twenty-fourth transistor T24 is coupled to the second start signal input terminal, a first electrode of the twenty-fourth transistor T24 is coupled to the second level signal input terminal VGH, and a second electrode of the twenty-fourth transistor T24 is coupled to the twelfth node n12;

[0189] The voltage stabilizing circuit 80 includes a capacitor structure, a first end of the capacitor structure is coupled to the ground signal input terminal, and a second end of the capacitor structure is coupled to the second gate drive signal output terminal;

[0190] The nineteenth transistor T19 , the twenty-first transistor T21 , and the twenty-second transistor T22 include P-type transistors, and the twentieth transistor T20 , the twenty-third transistor T23 , and the twenty-fourth transistor T24 include N-type transistors.

[0191] In some embodiments, the display panel further includes a second clock signal line, a third clock signal line, a fourth clock signal line, and a fifth clock signal line;

[0192] The display panel includes a plurality of cascaded second-type shift registers, wherein a second start signal input terminal coupled to a first-stage second-type shift register is coupled to a second frame start signal line in the display panel; a second start signal input terminal coupled to an n+1-th-stage second-type shift register is coupled to a second gate drive signal output terminal of an n-th-stage second-type shift register, where n is an integer greater than or equal to 1;

[0193] The cascaded multiple second-type shift registers are divided into multiple shift register groups, each shift register group includes two adjacent stages of shift registers, and in each shift register group, the second clock signal input terminal coupled to the previous stage shift register is coupled to the second clock signal line, the third clock signal input terminal coupled to the previous stage shift register is coupled to the third clock signal line, the second clock signal input terminal coupled to the next stage shift register is coupled to the fourth clock signal line, and the third clock signal input terminal coupled to the next stage shift register is coupled to the fifth clock signal line.

[0194] In some embodiments, the orthographic projection of the second shift register on the base substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line and the fifth clock signal line on the base substrate.

[0195] It should be noted that the "same layer" in the embodiments of the present invention may refer to film layers on the same structural layer. Or, for example, film layers on the same layer may be film layers that are formed using the same film-forming process to form specific patterns, and then patterned using the same mask through a single patterning process to form the film layers. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the resulting layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0196] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present invention.

[0197] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0198] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this utility model belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0199] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0200] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0201] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A shift register, characterized in that: include: A first node control circuit is coupled to the first node, the first start signal input terminal, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal respectively; for controlling, under the control of a first start signal inputted into the first start signal input terminal and a first clock signal inputted into the first clock signal input terminal, to control the electrical connection between the first node and the first level signal input terminal to be conducted or disconnected, and to control the electrical connection between the first node and the second level signal input terminal to be conducted or disconnected; a second node control circuit, coupled to the second node, the third node, the first gate drive signal output terminal, the first level signal input terminal, and the second level signal input terminal, respectively; and configured to control, under control of the potential of the third node and the first gate drive signal outputted from the first gate drive signal output terminal, to switch on or off the electrical connection between the second node and the first level signal input terminal, and to switch on or off the electrical connection between the second node and the second level signal input terminal; a first output control circuit, coupled to the first gate drive signal output terminal, the first node, the second node, a first level signal input terminal, and a second level signal input terminal, respectively; and configured to control, under control of the potential of the first node and the potential of the second node, to switch on or off the electrical connection between the first gate drive signal output terminal and the first level signal input terminal, and to switch on or off the electrical connection between the first gate drive signal output terminal and the second level signal input terminal; a third node control circuit coupled to the third node, the fourth node, the first clock signal input terminal, the first level signal input terminal, and the second level signal input terminal, respectively; for controlling, under the control of the potential of the fourth node and the first clock signal inputted from the first clock signal input terminal, to switch on or off the electrical connection between the third node and the first level signal input terminal, and to switch on or off the electrical connection between the third node and the second level signal input terminal; The fourth node control circuit is coupled to the fourth node, the first start signal input terminal, the first level signal input terminal and the second level signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the fourth node and the first level signal input terminal, and the conduction or disconnection of the electrical connection between the fourth node and the second level signal input terminal under the control of the first start signal input terminal.

2. The shift register according to claim 1, wherein: The first node control circuit includes a first control subcircuit and a second control subcircuit; The first control subcircuit is coupled to the first start signal input terminal, the second level signal input terminal, the fifth node, and the first node, respectively; and is configured to control the electrical connection between the first node and the second level signal input terminal to be opened or closed, and the electrical connection between the first node and the fifth node to be opened or closed, under the control of the first start signal input terminal. The second control subcircuit is coupled to the first clock signal input terminal, the second level signal input terminal, the first node, the fifth node, and the first level signal input terminal, respectively; and is configured to control the electrical connection between the second level signal input terminal and the first node and the electrical connection between the first level signal input terminal and the fifth node to be opened or opened under the control of the first clock signal input terminal. The second node control circuit controls a third control subcircuit and a fourth control subcircuit; The third control subcircuit is coupled to the third node, the second level signal input terminal, the sixth node, and the second node, respectively; and is configured to control, under the control of the potential of the third node, to switch on or off the electrical connection between the second level signal input terminal and the second node, and to switch on or off the electrical connection between the sixth node and the second node; The fourth control subcircuit is coupled to the first gate drive signal output terminal, the second level signal input terminal, the second node, the sixth node, and the first level signal input terminal, respectively; and is configured to control, under the control of the first gate drive signal output by the first gate drive signal output terminal, to conduct or disconnect the electrical connection between the second level signal input terminal and the second node, and to conduct or disconnect the electrical connection between the sixth node and the first level signal input terminal; The first output control circuit includes a fifth control subcircuit and a sixth control subcircuit; The fifth control subcircuit is coupled to the first node, the second level signal input terminal, the first gate drive signal output terminal, and the seventh node, respectively; and is configured to control, under the control of the potential of the first node, to switch on or off the electrical connection between the second level signal input terminal and the first gate drive signal output terminal, and to switch on or off the electrical connection between the seventh node and the first gate drive signal output terminal; The sixth control subcircuit is coupled to the second node, the second level signal input terminal, the first gate drive signal output terminal, the seventh node, and the first level signal input terminal, respectively; and is configured to control, under the control of the potential of the second node, to switch on or off the electrical connection between the second level signal input terminal and the first gate drive signal output terminal, and to switch on or off the electrical connection between the seventh node and the first level signal input terminal; The third node control circuit includes a seventh control subcircuit and an eighth control subcircuit; The seventh control subcircuit is coupled to the fourth node, the second-level signal input terminal, the third node, and the eighth node, respectively; and is configured to control, under the control of the potential of the fourth node, to switch on or off the electrical connection between the second-level signal input terminal and the third node, and to switch on or off the electrical connection between the third node and the eighth node; The eighth control subcircuit is coupled to the first clock signal input terminal, the second level signal input terminal, the third node, the eighth node and the first level signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the third node, and to control the conduction or disconnection of the electrical connection between the eighth node and the first level signal input terminal under the control of the first clock signal input into the first clock signal input terminal.

3. The shift register according to claim 2, wherein: The first control subcircuit includes a first transistor and a third transistor; a gate of the first transistor is coupled to the first start signal input terminal, a first electrode of the first transistor is coupled to the second level signal input terminal, and a second electrode of the first transistor is coupled to the first node; a gate of the third transistor is coupled to the first start signal input terminal, a first electrode of the third transistor is coupled to the fifth node, and a second electrode of the third transistor is coupled to the first node; The second control subcircuit includes a second transistor and a fourth transistor; a gate of the second transistor coupled to the first clock signal input terminal, a first electrode of the second transistor coupled to the second level signal input terminal, and a second electrode of the second transistor coupled to the first node; a gate of the fourth transistor coupled to the first clock signal input terminal, a first electrode of the fourth transistor coupled to the first level signal input terminal, and a second electrode of the fourth transistor coupled to the fifth node; The third control subcircuit includes a thirteenth transistor and a fifteenth transistor; The gate of the thirteenth transistor is coupled to the third node, the first electrode of the thirteenth transistor is coupled to the second level signal input terminal, and the second electrode of the thirteenth transistor is coupled to the second node; the gate of the fifteenth transistor is coupled to the third node, the first electrode of the fifteenth transistor is coupled to the sixth node, and the second electrode of the fifteenth transistor is coupled to the second node; The fourth control subcircuit includes a fourteenth transistor and a sixteenth transistor; The gate of the fourteenth transistor is coupled to the first gate drive signal output terminal, the first electrode of the fourteenth transistor is coupled to the second level signal input terminal, and the second electrode of the fourteenth transistor is coupled to the second node; the gate of the sixteenth transistor is coupled to the first gate drive signal output terminal, the first electrode of the sixteenth transistor is coupled to the first level signal input terminal, and the second electrode of the sixteenth transistor is coupled to the sixth node; The fifth control subcircuit includes a fifth transistor and a seventh transistor, wherein the gate of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the second level signal input terminal, and the second electrode of the fifth transistor is coupled to the first gate drive signal output terminal; the gate of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the seventh node, and the second electrode of the seventh transistor is coupled to the first gate drive signal output terminal; The sixth control subcircuit includes a sixth transistor and an eighth transistor, wherein a gate of the sixth transistor is coupled to the second node, a first electrode of the sixth transistor is coupled to the second level signal input terminal, and a second electrode of the sixth transistor is coupled to the first gate drive signal output terminal; a gate of the eighth transistor is coupled to the second node, a first electrode of the eighth transistor is coupled to the first level signal input terminal, and a second electrode of the eighth transistor is coupled to the seventh node; The seventh control subcircuit includes a ninth transistor and an eleventh transistor, wherein a gate of the ninth transistor is coupled to the fourth node, a first electrode of the ninth transistor is coupled to the second-level signal input terminal, and a second electrode of the ninth transistor is coupled to the third node; a gate of the eleventh transistor is coupled to the fourth node, a first electrode of the eleventh transistor is coupled to the eighth node, and a second electrode of the eleventh transistor is coupled to the third node; The eighth control subcircuit includes a tenth transistor and a twelfth transistor, wherein a gate of the tenth transistor is coupled to the first clock signal input terminal, a first electrode of the tenth transistor is coupled to the second level signal input terminal, and a second electrode of the tenth transistor is coupled to the third node; a gate of the twelfth transistor is coupled to the first clock signal input terminal, a first electrode of the twelfth transistor is coupled to the first level signal input terminal, and a second electrode of the twelfth transistor is coupled to the eighth node; The fourth node control circuit includes a seventeenth transistor and an eighteenth transistor, wherein a gate of the seventeenth transistor is coupled to the first start signal input terminal, a first electrode of the seventeenth transistor is coupled to the second level signal input terminal, and a second electrode of the seventeenth transistor is coupled to the fourth node; a gate of the eighteenth transistor is coupled to the first start signal input terminal, a first electrode of the eighteenth transistor is coupled to the first level signal input terminal, and a second electrode of the eighteenth transistor is coupled to the fourth node; The first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, the tenth transistor, the thirteenth transistor and the fourteenth transistor include P-type transistors; the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the fifteenth transistor and the sixteenth transistor include N-type transistors.

4. A gate drive circuit, characterized in that: It comprises a plurality of cascaded shift registers as described in any one of claims 1 to 3; the first start signal input terminal coupled to the first stage shift register is coupled to the first frame start signal line; the first start signal input terminal coupled to the n+1 stage shift register is coupled to the first gate drive signal output terminal of the n stage shift register, where n is an integer greater than or equal to 1.

5. A display panel, characterized in that: Including the gate drive circuit as described in claim 4, the display panel also includes a first clock signal line, and the positive projection of at least part of the shift register in the gate drive circuit on the base substrate of the display panel at least partially overlaps with the positive projection of the first clock signal line on the base substrate.

6. The display panel according to claim 5, wherein: The display panel further includes a second shift register, and the second shift register includes: a second output control circuit, coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the first level signal input terminal, and the second gate drive signal output terminal, respectively; and configured to control the electrical connection between the first level signal input terminal and the second gate drive signal output terminal to be conducted or disconnected under the common control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal; a third output control circuit, coupled to the second start signal input terminal, the second clock signal input terminal, the third clock signal input terminal, the second level signal input terminal, and the second gate drive signal output terminal, respectively; and configured to control the electrical connection between the second level signal input terminal and the second gate drive signal output terminal to be conducted or disconnected under the joint control of the second start signal input terminal, the second clock signal input terminal, and the third clock signal input terminal; The voltage stabilizing circuit is coupled to the ground signal input terminal and the second gate driving signal output terminal respectively.

7. The display panel according to claim 6, wherein: The second output control circuit includes: a ninth control subcircuit, coupled to the third clock signal input terminal, the ninth node, and the second gate drive signal output terminal, respectively, and configured to control, under control of a third clock signal inputted from the third clock signal input terminal, to switch on or off the electrical connection between the ninth node and the second gate drive signal output terminal; a tenth control subcircuit, coupled to the second clock signal input terminal, the ninth node, and the tenth node, respectively, and configured to control the electrical connection between the ninth node and the tenth node to be opened or closed under the control of the second clock signal input terminal; an eleventh control subcircuit, coupled to the second start signal input terminal, the tenth node, and the first level signal input terminal, respectively, for controlling, under the control of a second start signal inputted by the second start signal input terminal, to switch on or off the electrical connection between the tenth node and the first level signal input terminal; a twelfth control sub-circuit, coupled to the third clock signal input terminal, the eleventh node, and the second gate drive signal output terminal, respectively, and configured to control the electrical connection between the eleventh node and the second gate drive signal output terminal to be turned on or off under the control of a third clock signal inputted from the third clock signal input terminal; a thirteenth control sub-circuit, coupled to the second clock signal input terminal, the eleventh node, and the twelfth node, respectively, for controlling, under the control of the second clock signal inputted from the second clock signal input terminal, to switch on or off the electrical connection between the eleventh node and the twelfth node; A fourteenth control sub-circuit is coupled to the second start signal input terminal, the twelfth node and the second level signal input terminal, respectively, and is used to control the conduction or disconnection of the electrical connection between the twelfth node and the second level signal input terminal under the control of the second start signal input terminal.

8. The display panel according to claim 7, wherein: The ninth control sub-circuit includes a nineteenth transistor, a gate of the nineteenth transistor is coupled to the third clock signal input terminal, a first electrode of the nineteenth transistor is coupled to the ninth node, and a second electrode of the nineteenth transistor is coupled to the second gate drive signal output terminal; The tenth control sub-circuit includes a twentieth transistor, a gate of the twentieth transistor is coupled to the second clock signal input terminal, a first electrode of the twentieth transistor is coupled to the tenth node, and a second electrode of the twentieth transistor is coupled to the ninth node; The eleventh control sub-circuit includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the second start signal input terminal, a first electrode of the twenty-first transistor is coupled to the first level signal input terminal, and a second electrode of the twenty-first transistor is coupled to the tenth node; The twelfth control sub-circuit includes a twenty-second transistor, a gate of the twenty-second transistor is coupled to the third clock signal input terminal, a first electrode of the twenty-second transistor is coupled to the eleventh node, and a second electrode of the twenty-second transistor is coupled to the second gate drive signal output terminal; The thirteenth control sub-circuit includes a twenty-third transistor, a gate of the twenty-third transistor is coupled to the second clock signal input terminal, a first electrode of the twenty-third transistor is coupled to the twelfth node, and a second electrode of the twenty-third transistor is coupled to the eleventh node; The fourteenth control sub-circuit includes a twenty-fourth transistor, a gate of the twenty-fourth transistor is coupled to the second start signal input terminal, a first electrode of the twenty-fourth transistor is coupled to the second level signal input terminal, and a second electrode of the twenty-fourth transistor is coupled to the twelfth node; The voltage stabilizing circuit includes a capacitor structure, a first end of the capacitor structure is coupled to the ground signal input terminal, and a second end of the capacitor structure is coupled to the second gate drive signal output terminal; The nineteenth transistor, the twenty-first transistor, and the twenty-second transistor include P-type transistors, and the twentieth transistor, the twenty-third transistor, and the twenty-fourth transistor include N-type transistors.

9. The display panel according to claim 7, wherein: The display panel further includes a second clock signal line, a third clock signal line, a fourth clock signal line and a fifth clock signal line; The display panel includes a plurality of cascaded second-type shift registers, wherein a second start signal input terminal coupled to a first-stage second-type shift register is coupled to a second frame start signal line in the display panel; a second start signal input terminal coupled to an n+1-th-stage second-type shift register is coupled to a second gate drive signal output terminal of an n-th-stage second-type shift register, where n is an integer greater than or equal to 1; The cascaded multiple second-type shift registers are divided into multiple shift register groups, each shift register group includes two adjacent stages of shift registers, and in each shift register group, the second clock signal input terminal coupled to the previous stage shift register is coupled to the second clock signal line, the third clock signal input terminal coupled to the previous stage shift register is coupled to the third clock signal line, the second clock signal input terminal coupled to the next stage shift register is coupled to the fourth clock signal line, and the third clock signal input terminal coupled to the next stage shift register is coupled to the fifth clock signal line.

10. The display panel according to claim 9, wherein: The orthographic projection of the second shift register on the base substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the second clock signal line, the third clock signal line, the fourth clock signal line and the fifth clock signal line on the base substrate.

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