Display substrate, mother board, liquid crystal display panel and display device

Abstract

The embodiment of the utility model provides a display substrate, a mother board, a liquid crystal display panel and a display device, and belongs to the technical field of display. The display substrate comprises a substrate body and a first wire located on the substrate body, the first wire comprises a first isolation section and a first connection section which are connected in sequence, the first isolation section intersects with the contour line of the substrate body, and the first isolation section is used for preventing water and oxygen from entering the first connection section. According to the embodiment of the invention, the probability of abnormal display can be reduced, and the reliability of the display substrate is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a motherboard, a liquid crystal display panel, and a display device. Background Art

[0002] With the development of display technology, display devices are widely used in people's daily lives, such as laptops, smartphones, and tablet computers. Display substrates are an important component of display devices. Display substrates can be obtained by cutting motherboards.

[0003] In related art, when a motherboard is cut to produce a display substrate, the wires located along the cut lines are also cut. After cutting, the cross-section of the wires is exposed to the outside world. The wires at this exposed cross-section are highly susceptible to corrosion from external water and oxygen. This external water and oxygen can also enter the interior of the display substrate along the wires, further corroding the internal wiring of the display substrate, leading to display anomalies and compromising the reliability of the display substrate. Utility Model Content

[0004] The embodiments of the present disclosure provide a display substrate, a motherboard, a liquid crystal display panel, and a display device, which can reduce the probability of display abnormalities and improve the reliability of the display substrate. The technical solution is as follows:

[0005] On the one hand, a display substrate is provided, comprising a base substrate and a first conductive line located on the base substrate, wherein the first conductive line comprises a first isolation segment and a first connecting segment connected in sequence, the first isolation segment intersecting with a contour line of the base substrate, and the first isolation segment being used to prevent water and oxygen from entering the first connecting segment.

[0006] Optionally, the first isolation segment includes a plurality of first sub-conductors arranged side by side and spaced apart, each of the plurality of first sub-conductors intersects with a contour line of the substrate, and each of one end of the plurality of first sub-conductors is connected to one end of the first connection segment.

[0007] Optionally, a minimum distance between an end of the first sub-conductor away from a contour line of the base substrate and the contour line of the base substrate is greater than 200 μm and less than or equal to 400 μm.

[0008] Optionally, a line width of the first sub-conductor is smaller than a line width of the first connecting segment.

[0009] Optionally, a line width of the first sub-conductor is 5 μm to 15 μm; and / or a distance between two adjacent first sub-conductors is 5 μm to 15 μm.

[0010] Optionally, the first isolation segment and the first connection segment are both metal wires.

[0011] Optionally, the thickness of the first isolation segment is 0.3 μm to 0.4 μm.

[0012] Optionally, the first isolation segment is a metal oxide wire, and the first connection segment is a metal wire.

[0013] Optionally, the thickness of the first isolation segment is 0.6 μm to 0.8 μm.

[0014] Optionally, the first isolation segment and the first connection segment are in different layers, and the first isolation segment and the first connection segment are connected through a via.

[0015] Optionally, the first connecting segment is located in a source / drain metal layer or a gate metal layer.

[0016] On the other hand, a motherboard is provided, comprising a second conductive line and a plurality of display substrates, wherein at least one of the plurality of display substrates is any of the aforementioned display substrates; the motherboard has an area to be cut and a plurality of array areas arranged in an array, the area to be cut being located between adjacent array areas and at the periphery of the plurality of array areas, and each of the display substrates being located in a corresponding array area; the second conductive line is located in the area to be cut, the second conductive line is connected to the first isolation segment, and intersects with a cutting line, and the cutting line is the boundary line between the area to be cut and the array area.

[0017] Optionally, the second conductive wire includes a second isolation segment and a second connecting segment connected in sequence, and an end of the second isolation segment away from the second connecting segment is connected to the first isolation segment; the minimum distance between an end of the second isolation segment away from the cutting line and the cutting line is greater than 200 μm and less than or equal to 400 μm.

[0018] Optionally, the motherboard further includes a first alignment mark located in the area to be cut, and the second conductive line is located on a side of the first alignment mark close to the array area.

[0019] On the other hand, a liquid crystal display panel is provided, comprising an array substrate, a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is any of the aforementioned display substrates.

[0020] On the other hand, a display device is provided, comprising a backlight module and the aforementioned liquid crystal display panel, wherein the backlight module provides a light source for the liquid crystal display panel.

[0021] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0022] In the disclosed embodiment, the first conductive line includes a first isolation segment and a first connecting segment, which are sequentially connected. The first isolation segment intersects the outline of the base substrate. Thus, the cross-section of the first isolation segment is exposed to the outside world. Because the first isolation segment prevents water and oxygen from entering the first connecting segment, the probability of water and oxygen corroding the first connecting segment and corroding the internal wiring of the display substrate along the first connecting segment is reduced, thereby reducing the probability of display anomalies and improving the reliability of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 is a structural diagram of a motherboard provided by an embodiment of the present disclosure;

[0025] Figure 2 is a schematic diagram of a partial structure of a display substrate provided by an embodiment of the present disclosure;

[0026] Figure 3 is a partially enlarged structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0027] Figure 4 is a partially enlarged structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram of a partially enlarged structure of a motherboard provided by an embodiment of the present disclosure;

[0029] Figure 6 is a partially enlarged structural schematic diagram of another motherboard provided by an embodiment of the present disclosure;

[0030] Figure 7 is a schematic structural diagram of another motherboard provided by an embodiment of the present disclosure;

[0031] Figure 8 Schematic diagram of the structure of a liquid crystal display panel provided by an embodiment of the present disclosure.

[0032] Legend:

[0033] 1. Area to be cut 1a, cutting line 2, array area

[0034] 3. Display area 4, peripheral area 100, motherboard

[0035] 1000, display substrate 2000, color filter substrate 3000, liquid crystal layer

[0036] 10. Base substrate 11. Contour line

[0037] 20, first conductor 21, first isolation segment 211, first sub-conductor

[0038] 212, first connecting portion 22, first connecting section

[0039] 30. Connecting electrodes 31. Testing electrodes

[0040] 40, second conductor 41, second isolation segment 411, second sub-conductor

[0041] 412, second connecting portion 42, second connecting section

[0042] 50. First alignment mark DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0044] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar terms used in the patent specification and claims of this disclosure do not denote any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not denote a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" and "comprise" mean that the elements or objects listed before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. Furthermore, "A and / or B" indicates the existence of three situations: A, B, and A and B.

[0045] To facilitate understanding of the embodiments of the present disclosure, the relationship between the motherboard and the display substrate will be described below with reference to the accompanying drawings.

[0046] Figure 1 Schematic diagram of the structure of a motherboard provided by an embodiment of the present disclosure. Figure 1As shown, the motherboard 100 includes multiple display substrates 1000. The motherboard 100 has a to-be-cut area 1 and multiple array areas 2 arranged in an array. The to-be-cut area 1 is located between adjacent array areas 2 and around the periphery of the multiple array areas 2. Each display substrate 1000 is located in a corresponding array area 2. The boundary between the to-be-cut area 1 and the array area 2 is a cutting line 1a. The display substrate 1000 can be obtained by cutting the motherboard 100 along the cutting line 1a.

[0047] Figure 2 It is a schematic diagram of the partial structure of a display substrate provided by an embodiment of the present disclosure. Figure 2 Can be Figure 1 Schematic diagram of the local structure in . Figure 2 As shown, the display substrate includes a base substrate 10 and a first conductive line 20 located on the base substrate 10. The first conductive line 20 includes a first isolation segment 21 and a first connecting segment 22 connected in sequence. The first isolation segment 21 intersects with the contour line 11 of the base substrate 10. The first isolation segment 21 is used to prevent water and oxygen from entering the first connecting segment 22.

[0048] In the disclosed embodiment, the first conductive line 20 includes a first isolation segment 21 and a first connecting segment 22, which are connected in sequence. The first isolation segment 21 intersects the outline 11 of the base substrate 10. Thus, the cross-section of the first isolation segment 21 is exposed to the outside world. Because the first isolation segment 21 is used to block water and oxygen from entering the first connecting segment 22, the probability of external water and oxygen corroding the first connecting segment 22 and corroding the internal wiring of the display substrate along the first connecting segment 22 is reduced, thereby reducing the probability of display anomalies and improving the reliability of the display substrate.

[0049] Optionally, the first wire 20 may be a test wire, which is used to conduct a test signal to the inside of the display substrate to be cut before cutting the motherboard, so as to test the display effect of the display substrate to be cut.

[0050] In other embodiments, the first wire 20 may also be a wire that conducts other functional signals, which is not limited in the present disclosure.

[0051] like Figure 2As shown, the first isolation segment 21 includes multiple first sub-conductors 211 arranged side by side and spaced apart. Each of the multiple first sub-conductors 211 intersects the outline 11 of the base substrate 10, and one end of each of the multiple first sub-conductors 211 is connected to one end of the first connecting segment 22. Thus, the cross-section of the multiple first sub-conductors 211 is exposed to the outside world. Because the cross-sectional area of ​​the first sub-conductors 211 is relatively small, the contact area between the cross-sectional area of ​​the first isolation segment 21 and external water and oxygen can be effectively reduced, thereby reducing the probability of external water and oxygen corroding the first isolation segment 21 at the exposed cross-sectional area and corroding the internal wiring of the display substrate along the first conductors 20.

[0052] Figure 3 This is a schematic diagram of a partially enlarged structure of a display substrate provided by an embodiment of the present disclosure. Figure 3 Can be Figure 2 The schematic diagram of the partially enlarged structure at the dotted box A is shown in the figure. Figure 3 As shown, the minimum distance D1 between the end of the first sub-conductor 211 away from the outline 11 of the substrate 10 and the outline 11 of the substrate 10 is greater than 200 μm and less than or equal to 400 μm. Here, the minimum distance D1 refers to the minimum distance between the end of the first sub-conductor 211 away from the outline 11 of the substrate 10 and the outline 11 of the substrate 10, that is, the vertical distance. If D1 is too small, the first connecting segment 22 may be too close to the outline 11 of the substrate 10, that is, too close to external water and oxygen, and thus corroded by external water and oxygen. If D1 is too large, the first sub-conductor 211 may occupy a large area, affecting the display area ratio of the display substrate. Within this range, D1 can ensure that the display area ratio of the display substrate is high while ensuring that the first connecting segment 22 is far away from external water and oxygen. This effectively reduces the probability of external water and oxygen corroding the first connecting segment 22 through the first sub-conductor 211, as well as the probability of corrosion of the internal wiring of the display substrate along the first connecting segment 22.

[0053] For example, the minimum distance D1 between the end of the first sub-conductor 211 away from the outline 11 of the substrate 10 and the outline 11 of the substrate 10 may be 350 μm to 400 μm. For example, the minimum distance D1 between the end of the first sub-conductor 211 away from the outline 11 of the substrate 10 and the outline 11 of the substrate 10 may be 350 μm, 370 μm, or 400 μm, etc.

[0054] Optionally, the line width W1 of the first sub-conductor 211 is smaller than the line width W2 of the first connecting segment 22. In this way, the cross-sectional area of ​​the first sub-conductor 211 can be ensured to be smaller than the cross-sectional area of ​​the first connecting segment 22, thereby effectively reducing the contact area between the cross-sectional area of ​​the first sub-conductor 211 and external water and oxygen.

[0055] Optionally, the line width W1 of the first sub-conductor 211 is 5 μm to 15 μm. If the line width W1 of the first sub-conductor 211 is too small, the impedance of the first sub-conductor 211 may be too large, affecting the conduction of electrical signals in the first sub-conductor 211. If the line width W1 of the first sub-conductor 211 is too large, the contact area between the cross section of the first sub-conductor 211 and external water and oxygen may be too large, affecting the barrier effect of the first sub-conductor 211 against water and oxygen. When the line width W1 of the first sub-conductor 211 is within this range, the impedance of the first sub-conductor 211 can be kept low while effectively reducing the contact area between the cross section of the first sub-conductor 211 and external water and oxygen at the contour line 11 of the base substrate 10, thereby reducing the probability of display anomalies and improving the reliability of the display substrate.

[0056] For example, the line width W1 of the first sub-conductor 211 may be 5 μm, 10 μm, or 15 μm.

[0057] Exemplarily, the line width W2 of the first connecting segment 22 is the maximum line width of the first conductive line 20. For the first isolation segment 21 including multiple first sub-conductors 211, the maximum line width refers to the maximum distance between the two outermost first sub-conductors 211 in the first isolation segment 21.

[0058] Optionally, the maximum line width of the first conductive line 20 is 100 μm to 200 μm. In this way, the overall cross-sectional area of ​​the first conductive line 20 can be ensured to be larger, thereby reducing the impedance of the first conductive line 20.

[0059] For example, the maximum line width of the first conductive line 20 may be 100 μm, 150 μm, or 200 μm.

[0060] Optionally, the distance D2 between two adjacent first sub-conductors 211 is 5 μm to 15 μm. If the distance D2 between two adjacent first sub-conductors 211 is too small, external water and oxygen may enter the first connecting segment 22 through the closely spaced first sub-conductors 211, causing corrosion. If the distance D2 between two adjacent first sub-conductors 211 is too large, the maximum line width and impedance of the first isolation segment 21 may be affected. If the distance D2 between two adjacent first sub-conductors 211 is within this range, the maximum line width and impedance of the first isolation segment 21 can be kept small, while the impedance is high, and the probability of external water and oxygen corroding the first sub-conductors 211 is reduced.

[0061] For example, the distance D2 between two adjacent first sub-conducting wires 211 may be 5 μm, 10 μm, or 15 μm.

[0062] In one possible implementation, the line width W1 of the first sub-conductor 211 is equal to the distance D2 between two adjacent first sub-conductors 211. For example, the line width W1 of the first sub-conductor 211 is 10 μm, and the distance D2 between two adjacent first sub-conductors 211 is 10 μm.

[0063] In other embodiments, the line width W1 of the first sub-conductor 211 and the distance D2 between two adjacent first sub-conductors 211 may not be equal. For example, the line width W1 of the first sub-conductor 211 may be greater than the distance D2 between two adjacent first sub-conductors 211; or the line width W1 of the first sub-conductor 211 may be less than the distance D2 between two adjacent first sub-conductors 211, and this disclosure is not limited thereto.

[0064] Optionally, the display substrate can be an array substrate of a liquid crystal (LC) display panel, an organic light-emitting diode (OLED) display substrate, a quantum dot light-emitting diode (QLED) display substrate, or a micro light-emitting diode (Micro LED) display substrate.

[0065] The embodiments of the present disclosure are described by taking the display substrate as an array substrate as an example.

[0066] Exemplarily, the display substrate further includes a driving circuit layer, a passivation layer, and a transparent conductive layer sequentially stacked on the base substrate 10 .

[0067] Exemplarily, the driving circuit layer includes a gate metal layer, a gate insulating layer, an active layer, and a source-drain metal layer sequentially stacked on the base substrate 10 .

[0068] Exemplarily, the driving circuit layer further includes a plurality of pixel driving circuits, each of which includes at least one thin film transistor (TFT), and each TFT includes a gate, a source, and a drain. The gate is located in the gate metal layer, and the source and drain are located in the source-drain metal layer.

[0069] Exemplarily, the base substrate 10 may be a transparent substrate, such as glass, plastic, etc.

[0070] Illustratively, the gate metal layer may be made of one or more of molybdenum, copper, and aluminum.

[0071] Illustratively, the gate insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0072] For example, the active layer may be made of a low-temperature polysilicon material or a metal oxide semiconductor material such as Indium Gallium Zinc Oxide (IGZO).

[0073] Exemplarily, the source-drain metal layer can be a single-layer metal film such as aluminum, molybdenum, copper, or titanium, or a multi-layer metal film such as a molybdenum layer, an aluminum layer, and a molybdenum layer stacked in sequence, or a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0074] For example, the passivation layer may be a silicon oxide layer or a silicon nitride layer.

[0075] For example, the transparent conductive layer may be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0076] It should be noted that the film layer structure of the array substrate can be adjusted according to actual needs, and the embodiments of the present disclosure do not limit this.

[0077] Figure 3 In the figure, the first isolation segment 21 and the first connecting segment 22 are both metal wires. By setting the metal wire of the first isolation segment 21 as multiple first sub-wires 211, the contact area between the cross section of the first isolation segment 21 and external water and oxygen can be effectively reduced, thereby reducing the probability of external water and oxygen corroding the first isolation segment 21 at the exposed cross-section position and corroding the internal wiring of the display substrate along the first wire 20.

[0078] Optionally, the first isolation segment 21 is located in the source / drain metal layer or the gate metal layer, and the first connection segment 22 is located in the source / drain metal layer or the gate metal layer. By being in the same layer as the gate metal layer or the source / drain metal layer, the manufacturing process can be simplified.

[0079] In other embodiments, depending on the film layer structure of the array substrate, the first isolation segment 21 and the first connection segment 22 may also be located in other metal layers, which is not limited in the present disclosure.

[0080] In one possible embodiment, the first isolation segment 21 and the first connecting segment 22 are both metal conductors and are located in different layers. The first isolation segment 21 and the first connecting segment 22 are connected via a via. Thus, by arranging the first isolation segment 21 and the first connecting segment 22 in different layers, static electricity on the longer first conductor 20 can be released, thereby reducing the chance of static electricity entering the interior of the display substrate and causing a short circuit. For example, the first isolation segment 21 may be located in the source / drain metal layer, the first connecting segment 22 may be located in the gate metal layer, and the first isolation segment 21 may be connected to the first connecting segment 22 via a via in the passivation layer. Alternatively, the first isolation segment 21 may be located in the gate metal layer, the first connecting segment 22 may be located in the source / drain metal layer, and the first connecting segment 22 may be connected to the first isolation segment 21 via a via in the passivation layer.

[0081] In another possible embodiment, the first isolation segment 21 and the first connection segment 22 are both metal wires and are located in the same layer. For example, the first isolation segment 21 and the first connection segment 22 can both be located in the source / drain metal layer; or the first isolation segment 21 and the first connection segment 22 can both be located in the gate metal layer.

[0082] Optionally, the first isolation segment 21 is a metal wire, and the thickness of the first isolation segment 21 is 0.3 μm to 0.4 μm. In this way, the cross-sectional area of ​​the first isolation segment 21 can be reduced, thereby reducing the probability of the first isolation segment 21 being corroded by external water and oxygen.

[0083] Exemplarily, the first isolation segment 21 is a metal wire, and the thickness of the first isolation segment 21 may be 0.3 μm, 0.35 μm, or 0.4 μm.

[0084] Figure 4 It is a schematic diagram of a partially enlarged structure of another display substrate provided in an embodiment of the present disclosure. Figure 4 Can be Figure 2 Schematic diagram of the local enlarged structure at the dotted box A in the middle. Figure 4 In the embodiment, the first isolation segment 21 is a metal oxide conductor, and the first connecting segment 22 is a metal conductor. For example, each first sub-conductor 211 in the first isolation segment 21 is a metal oxide conductor. Due to the low activity of metal oxides, metal oxide conductors are not easily corroded by external water and oxygen, effectively isolating them from external water and oxygen. Furthermore, the layer-switching arrangement facilitates the dissipation of static electricity on the longer first conductors 20, thereby reducing the chance of static electricity entering the interior of the display substrate and causing a short circuit.

[0085] Exemplarily, the first isolation segment 21 is a metal oxide wire located in the transparent conductive layer, the first connection segment 22 is a metal wire located in the source / drain metal layer or the gate metal layer, the first isolation segment 21 and the first connection segment 22 are in different layers, and the first isolation segment 21 and the first connection segment 22 are connected through a via.

[0086] like Figure 4As shown, the first isolation segment 21 further includes a first connecting portion 212, through which one end of each of the plurality of first sub-conductors 211 is connected to one end of the first connecting segment 22. For example, the first isolation segment 21 is located in the transparent conductive layer, and the first connecting segment 22 is located in the source / drain metal layer. One end of each of the first sub-conductors 211 in the first isolation segment 21 is connected to the first connecting portion 212, and the first connecting portion 212 is connected to one end of the first connecting segment 22 through a via in the passivation layer.

[0087] In a possible implementation, the first connecting portion 212 may not be provided, and one end of each first sub-conductor 211 in the first isolation segment 21 is connected to one end of the first connecting segment 22 through a via in the passivation layer.

[0088] In another possible embodiment, the first isolation segment 21 is a metal oxide conductive wire located in the transparent conductive layer, and the plurality of first sub-conductors 211 are not provided. The first connecting segment 22 is a metal conductive wire located in the source / drain metal layer. Because metal oxides have a certain barrier effect against water and oxygen, they can also reduce the probability of external water and oxygen corroding the first connecting segment 22 and corroding the internal wiring of the display substrate along the first connecting segment 22.

[0089] Optionally, the first isolation segment 21 is a metal oxide wire, and the thickness of the first isolation segment 21 is 0.6 μm to 0.8 μm. In this way, the cross-sectional area of ​​the first isolation segment 21 can be reduced, thereby reducing the probability of the first isolation segment 21 being corroded by external water and oxygen.

[0090] Exemplarily, the first isolation segment 21 is a metal oxide wire, and the thickness of the first isolation segment 21 may be 0.6 μm, 0.7 μm, or 0.8 μm.

[0091] The present disclosure also provides a motherboard. Figure 1 As shown, the motherboard 100 includes a second conductive line 40 and a plurality of display substrates 1000, at least one of which is the aforementioned display substrate. The motherboard 100 has a to-be-cut region 1 and a plurality of array regions 2 arranged in an array. The to-be-cut region 1 is located between adjacent array regions 2 and around the plurality of array regions. Each display substrate 1000 is located in a corresponding array region 2.

[0092] Figure 5 This is a partially enlarged structural diagram of a motherboard provided by an embodiment of the present disclosure. Figure 1 and Figure 5 The second conductive line 40 is located in the area to be cut 1 , is connected to the first isolation segment 21 , and intersects with the cutting line 1 a , which is the boundary line between the area to be cut 1 and the array area 2 .

[0093] In the embodiment of the present disclosure, when the motherboard 100 is cut along the cutting line 1a, the exposed cross-section is the cross-section of the first isolation segment 21, which can reduce the probability of external water and oxygen corroding the first connecting segment 22 and corroding the internal wiring of the display substrate 1000 along the first connecting segment 22, thereby reducing the probability of display abnormalities and improving the reliability of the display substrate 1000.

[0094] Exemplarily, the second conductive line 40 includes a second isolation segment 41 and a second connecting segment 42 connected in sequence, and one end of the second isolation segment 41 away from the second connecting segment 42 is connected to the first isolation segment 21 .

[0095] Optionally, a minimum distance D3 between the end of the second isolation segment 41 away from the cutting line 1a and the cutting line 1a is greater than 200 μm and less than or equal to 400 μm. Since the cutting accuracy of the motherboard 100 along the cutting line 1a is generally 200 μm, D3 within this range can ensure that the cross section exposed after cutting is the cross section of the first isolation segment 21 or the second isolation segment 41, which is beneficial for blocking water and oxygen.

[0096] For example, the minimum distance D3 between the end of the second isolation segment 41 away from the cutting line 1a and the cutting line 1a can be 350 μm to 400 μm. For example, the minimum distance D3 between the end of the second isolation segment 41 away from the cutting line 1a and the cutting line 1a can be 350 μm, 370 μm, or 400 μm.

[0097] Optionally, the second wire 40 is a test wire.

[0098] like Figure 1 As shown, the display substrate 1000 has a display area 3 and a peripheral area 4 located outside the display area 3 . Each display substrate 1000 further includes two connecting electrodes 30 . The connecting electrodes 30 are located in the peripheral area 4 and connected to the first wires 20 .

[0099] Exemplarily, the connecting electrode 30 is connected to the first connecting section of the first conductive line 20 .

[0100] Exemplarily, the connecting electrode 30 is a metal electrode, and is located in the source / drain metal layer or the gate metal layer.

[0101] Optionally, the motherboard 100 further includes test electrodes 31 , which are arranged in pairs and located in the to-be-cut area 1 .

[0102] Exemplarily, the test electrode 31 is connected to the second connecting section of the second lead 40 .

[0103] Exemplarily, the test electrode 31 is a metal electrode, located in a source / drain metal layer or a gate metal layer.

[0104] like Figure 1 As shown, two pairs of test electrodes 31 are located in the upper and lower regions of the motherboard 100, respectively. In both the upper and lower regions, one test electrode 31 is located at the edge of the upper left corner of the area 1 to be cut, and the other test electrode 31 is located at the edge of the lower right corner of the area 1 to be cut. In the upper region, two rows and two columns of display substrates 1000 are arranged. Both test electrodes 31 are connected to the second conductive wire 40, and the second conductive wire 40 is connected to the first conductive wire 20 of each display substrate 1000 to form the closed loop required for testing. In the lower region, three rows and two columns of display substrates 1000 are arranged. Both test electrodes 31 are connected to the second conductive wire 40, and the second conductive wire 40 is connected to the first conductive wire 20 of each display substrate 1000 to form the closed loop required for testing.

[0105] It should be noted that Figure 1 The arrangement of the display substrate 1000 and the number of test electrodes 31 are merely examples. A greater or lesser number of display substrates 1000 or a greater or lesser number of test electrodes 31 may be arranged according to actual needs, and the present disclosure does not impose any restrictions on this.

[0106] like Figure 1 As shown, motherboard 100 further includes a first alignment mark 50 located in the area to be cut 1, and a second conductive wire 40 located on the side of the first alignment mark 50 near the array area 2. The first alignment mark 50 allows for better alignment and identification of motherboard 100 by the cutting equipment, thereby improving cutting accuracy. The second conductive wire 40 located on the side of the first alignment mark 50 near the array area 2 reduces the impact of the second conductive wire 40 on the area of ​​motherboard 100, thereby improving the area utilization of motherboard 100.

[0107] In other embodiments, the motherboard 100 may further include a second alignment mark located in the array region 2 .

[0108] like Figure 5 As shown, the second isolation segment 41 includes a plurality of second sub-conductors 411 arranged side by side and spaced apart. The plurality of second sub-conductors 411 intersect with the cutting line 1 a , and one end of the plurality of second sub-conductors 411 is connected to one end of the second connection segment 42 .

[0109] Exemplarily, the second isolation segment 41 and the first isolation segment 21 are on the same layer, and the second connecting segment 42 and the first connecting segment 22 are on the same layer.

[0110] Exemplarily, the second isolation segment 41 and the second connection segment 42 may both be metal wires and be in the same layer.

[0111] Exemplarily, the line width of the second sub-conductor 411 is equal to the line width of the first sub-conductor 211 .

[0112] Exemplarily, the distance between two adjacent second sub-conductors 411 is equal to the distance between two adjacent first sub-conductors 211 .

[0113] Exemplarily, the maximum line width of the second conductive line 40 is equal to the maximum line width of the first conductive line 20 .

[0114] Exemplarily, the thickness of the second isolation segment 41 is equal to the thickness of the first isolation segment 21 .

[0115] Figure 6 This is a partially enlarged structural diagram of another motherboard provided in an embodiment of the present disclosure. Figure 6 In the embodiment, the second isolation segment 41 is a metal oxide wire, and the second connection segment 42 is a metal wire.

[0116] Exemplarily, the second isolation segment 41 is a metal oxide wire located in the transparent conductive layer, the second connection segment 42 is a metal wire located in the source / drain metal layer or the gate metal layer, the second isolation segment 41 and the second connection segment 42 are in different layers, and the second isolation segment 41 and the second connection segment 42 are connected through a via.

[0117] like Figure 6 As shown, the second isolation segment 41 further includes a second connecting portion 412, through which one end of each of the plurality of second sub-conductors 411 is connected to one end of the second connecting segment 42. For example, the second isolation segment 41 is located in the transparent conductive layer, and the second connecting segment 42 is located in the source / drain metal layer. One end of each of the second sub-conductors 411 in the second isolation segment 41 is connected to the second connecting portion 412, and the second connecting portion 412 is connected to one end of the second connecting segment 42 through a via in the passivation layer.

[0118] In a possible implementation, the second connecting portion 412 may not be provided, and one end of each second sub-conductor 411 in the second isolation segment 41 is connected to one end of the second connecting segment 42 through a via in the passivation layer.

[0119] In another possible implementation, the second isolation segment 41 is a metal oxide wire located in the transparent conductive layer, and the plurality of second sub-wires 411 are not provided. The second connection segment 42 is a metal wire located in the source / drain metal layer.

[0120] Figure 7 This is a schematic diagram of the structure of another motherboard provided by an embodiment of the present disclosure. This motherboard 100 includes a second conductive line 40 and multiple display substrates 1000, at least one of which is the aforementioned display substrate. The motherboard 100 has a to-be-cut area 1 and multiple array areas 2 arranged in an array. The to-be-cut area 1 is located between adjacent array areas 2 and around the periphery of the multiple array areas 2. Each display substrate 1000 is located in a corresponding array area 2. Figure 7 The motherboard 100 shown is Figure 1 The motherboard 100 shown differs mainly in that Figure 7 The arrangement of multiple array areas 2 is different. Figure 7 The array area 2 is arranged in four rows and eight columns, that is, the display substrate 1000 is arranged in four rows and eight columns.

[0121] It should be noted that Figure 7 The first wire, the connecting electrode, the second wire, the test electrode and the first alignment mark are not shown in FIG. For related setting methods, see Figures 1 to 6 Detailed description of the related embodiments is omitted here.

[0122] like Figure 7 As shown, the motherboard 100 may be a rectangular motherboard.

[0123] For example, the rectangular motherboard may have a length of 2500 mm and a width of 2200 mm.

[0124] Optionally, the minimum distance D4 between the display area 3 of the display substrate 1000 and the outer contour line of the motherboard 100 may be 20 mm to 27 mm.

[0125] For example, the minimum distance D4 between the display area 3 of the display substrate 1000 and the outer contour line of the motherboard 100 may be 20 mm, 25 mm, or 26 mm.

[0126] Optionally, the minimum distance D5 between the array area 2 and the outer contour line of the motherboard 100 may be 16 mm to 19 mm.

[0127] For example, the minimum distance D5 between the array area 2 and the outer contour line of the motherboard 100 may be 16 mm, 17 mm, 18 mm, or 19 mm.

[0128] Optionally, the distance D6 between two adjacent array areas 2 may be greater than 0 mm and less than or equal to 10 mm.

[0129] For example, the distance D6 between two adjacent array areas 2 may be 3 mm, 5 mm, or 10 mm.

[0130] Figure 8 Schematic diagram of the structure of a liquid crystal display panel provided by an embodiment of the present disclosure. Figure 8 As shown, the liquid crystal display panel includes an array substrate, a color filter substrate 2000 disposed opposite to the array substrate, and a liquid crystal layer 3000 located between the array substrate and the color filter substrate 2000. The array substrate is the aforementioned display substrate 1000. For the structure and materials of the display substrate 1000, see Figures 1 to 6 Detailed description of the related embodiments is omitted here.

[0131] For example, the color filter substrate 2000 may include a first base substrate, a color filter layer disposed on the first base substrate, and an alignment layer disposed on a side of the color filter layer away from the first base substrate. The color filter layer may include a plurality of color filter units of different colors and a black matrix located between the color filter units.

[0132] For example, the liquid crystal display panel may be a Fringe Field Switching (FFS) type liquid crystal display panel or an Advanced Super Dimension Switch (ADS) type liquid crystal display panel.

[0133] It should be noted that the structure of the color filter substrate 2000 can be found in related art and will not be elaborated herein.

[0134] The embodiment of the present disclosure further provides a display device, which includes a backlight module and the aforementioned liquid crystal display panel, wherein the backlight module provides a light source for the liquid crystal display panel.

[0135] Optionally, the display device further includes a power supply circuit, which supplies power to the liquid crystal display panel.

[0136] Optionally, the display device can be any product or component with a display function, such as an outdoor electronic billboard, an outdoor charging station, a laptop computer, a mobile phone, a tablet computer, a television, a monitor, a wearable device, a digital photo frame, a navigator, or the like.

[0137] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A display substrate, characterized in that: The invention comprises a base substrate (10) and a first conductive line (20) located on the base substrate (10), wherein the first conductive line (20) comprises a first isolation segment (21) and a first connecting segment (22) connected in sequence, wherein the first isolation segment (21) intersects with a contour line (11) of the base substrate (10), and the first isolation segment (21) is used to prevent water and oxygen from entering the first connecting segment (22).

2. The display substrate according to claim 1, wherein: The first isolation segment (21) comprises a plurality of first sub-conductors (211) arranged side by side and spaced apart, the plurality of first sub-conductors (211) all intersect with the outline (11) of the substrate (10), and one end of the plurality of first sub-conductors (211) is connected to one end of the first connection segment (22).

3. The display substrate according to claim 2, wherein: The minimum distance between the end of the first sub-conductor (211) away from the outline (11) of the base substrate (10) and the outline (11) of the base substrate (10) is greater than 200 μm and less than or equal to 400 μm.

4. The display substrate according to claim 2, wherein: The line width of the first sub-conductor (211) is smaller than the line width of the first connecting section (22).

5. The display substrate according to claim 2, wherein: The line width of the first sub-conductor (211) is 5 μm to 15 μm; and / or, The distance between two adjacent first sub-conductors (211) is 5 μm to 15 μm.

6. The display substrate according to any one of claims 2 to 5, characterized in that: The first isolation section (21) and the first connection section (22) are both metal wires.

7. The display substrate according to claim 6, wherein: The thickness of the first isolation segment (21) is 0.3 μm to 0.4 μm.

8. The display substrate according to any one of claims 1 to 5, characterized in that: The first isolation section (21) is a metal oxide wire, and the first connection section (22) is a metal wire.

9. The display substrate according to claim 8, wherein: The thickness of the first isolation segment (21) is 0.6 μm to 0.8 μm.

10. The display substrate according to any one of claims 1 to 5, claim 7 and claim 9, characterized in that: The first isolation segment (21) and the first connection segment (22) are in different layers, and the first isolation segment (21) and the first connection segment (22) are connected through a via.

11. The display substrate according to any one of claims 1 to 5, claim 7 and claim 9, wherein: The first connecting section (22) is located in the source / drain metal layer or the gate metal layer.

12. A motherboard, characterized in that: The device comprises a second conductive line (40) and a plurality of display substrates (1000), wherein at least one display substrate (1000) among the plurality of display substrates (1000) is the display substrate (1000) according to any one of claims 1 to 11; The motherboard (100) comprises a to-be-cut area (1) and a plurality of array areas (2) arranged in an array, the to-be-cut area (1) being located between adjacent array areas (2) and at the periphery of the plurality of array areas (2), and each display substrate (1000) being located at a corresponding array area (2); The second conductive line (40) is located in the area to be cut (1), is connected to the first isolation segment (21), and intersects with a cutting line (1a), and the cutting line (1a) is the boundary line between the area to be cut (1) and the array area (2).

13. The motherboard according to claim 12, wherein: The second conductive line (40) comprises a second isolation segment (41) and a second connecting segment (42) connected in sequence, and an end of the second isolation segment (41) away from the second connecting segment (42) is connected to the first isolation segment (21); The minimum distance between the end of the second isolation segment (41) away from the cutting line (1a) and the cutting line (1a) is greater than 200 μm and less than or equal to 400 μm.

14. The motherboard (100) according to claim 12 or 13, characterized in that: The motherboard (100) further comprises a first alignment mark (50) located in the area to be cut (1), and the second conductive line (40) is located on a side of the first alignment mark (50) close to the array area (2).

15. A liquid crystal display panel, characterized in that: The invention comprises an array substrate, a color filter substrate (2000) arranged opposite to the array substrate, and a liquid crystal layer (3000) located between the array substrate and the color filter substrate (2000), wherein the array substrate is the display substrate (1000) according to any one of claims 1 to 11.

16. A display device, characterized in that: The device comprises a backlight module and the liquid crystal display panel as claimed in claim 15 , wherein the backlight module provides a light source for the liquid crystal display panel.

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