Display device

Abstract

A display device is provided. The display device includes: a bottom electrode on a substrate and including a first electrode portion and a second electrode portion on a side surface of the first electrode portion; a first insulating layer on the substrate and the bottom electrode; an active layer on the first insulating layer and including a channel region on the first electrode portion and source and drain regions on the second electrode portion; a gate insulating layer on the channel region and exposing the source region and the drain region; and a gate electrode on the gate insulating layer and overlapping the channel region. The first insulating layer and the active layer include valleys in respective regions between the first electrode portion and the second electrode portion. The gate insulating layer includes an end portion positioned on the valley of the active layer, and has a length greater than a length of the gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0137774, filed on October 16, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] With the development of multimedia technology, the importance of display devices has steadily increased. In response to this, various display devices including light-emitting display devices are being developed. Utility Model Content

[0005] Aspects of the present disclosure provide a display device capable of appropriately securing an effective channel length of a transistor and a method for manufacturing the display device.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment of the present disclosure, a display device may include: a bottom electrode disposed on a substrate and including a first electrode portion and a second electrode portion positioned on a side of the first electrode portion; a first insulating layer disposed on the substrate and covering the bottom electrode; an active layer disposed on the first insulating layer and including a channel region and source and drain regions, the channel region being disposed on the first electrode portion of the bottom electrode, and the source and drain regions being disposed on the second electrode portion of the bottom electrode; a gate insulating layer disposed on a portion of the active layer including the channel region and exposing the source and drain regions; and a gate electrode disposed on the gate insulating layer and overlapping the channel region of the active layer in a thickness direction of the substrate. The first insulating layer and the active layer may include valleys in respective regions between the first and second electrode portions of the bottom electrode. The gate insulating layer may include an end portion positioned on the valley of the active layer and may have a length in a longitudinal direction of the channel region that is greater than a length of the gate electrode.

[0008] In an embodiment, the gate insulating layer may protrude beyond a side of the gate electrode in a longitudinal direction of the channel region and may cover a portion of each of the source region and the drain region adjacent to the channel region.

[0009] In an embodiment, the substrate may include a groove overlapping the channel region and the gate electrode in a thickness direction.

[0010] In an embodiment, the first electrode portion of the bottom electrode may be disposed on the groove of the substrate.

[0011] In an embodiment, the second electrode portion of the bottom electrode may extend from the first electrode portion and be disposed on a peripheral portion of the groove of the substrate, and may have a height greater than that of the first electrode portion.

[0012] In an embodiment, the bottom electrode may include a valley positioned at a boundary between the first electrode portion and the second electrode portion and corresponding to the groove of the substrate.

[0013] In an embodiment, the first electrode portion and the second electrode portion of the bottom electrode may be spaced apart from each other in a region where the channel region is connected to the source region and the drain region.

[0014] In an embodiment, the bottom electrode may include an opening positioned between the first electrode portion and the second electrode portion.

[0015] In an embodiment, the display device may further include a second insulating layer disposed on the first insulating layer and covering the active layer, the gate insulating layer, and the gate electrode.

[0016] In an embodiment, the display device may further include a first transistor, which may include at least one of: a source electrode arranged on the second insulating layer and connected to the source region of the active layer; and a drain electrode arranged on the second insulating layer and connected to the drain region of the active layer.

[0017] In an embodiment, the display device may further include: a third insulating layer, which is arranged on the second insulating layer and covers at least one of the source electrode and the drain electrode; a light-emitting element layer, which includes a light-emitting element arranged on the third insulating layer; and an encapsulation layer, which covers the light-emitting element layer.

[0018] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a bottom electrode on a substrate including a first electrode portion and a second electrode portion positioned on a side of the first electrode portion; forming a first insulating layer on the substrate covering the bottom electrode and including a valley in a corresponding area between the first electrode portion and the second electrode portion of the bottom electrode; forming an active layer on the first insulating layer and the second electrode portion of the bottom electrode; sequentially forming a gate insulating layer covering the active layer and a conductive layer covering the gate insulating layer on the first insulating layer; arranging a mask on the conductive layer that overlaps with the first electrode portion of the bottom electrode in a thickness direction of the substrate; forming a gate electrode under the mask by etching the conductive layer; extending the width of the mask so that the mask covers the side surface of the gate electrode; and etching the gate insulating layer to cover a portion of the active layer overlapping with the mask and expose another portion of the active layer.

[0019] In an embodiment, extending the width of the mask may include reflowing the mask through a thermal treatment process.

[0020] In an embodiment, after reflow of the mask, ends of the mask may be positioned on valleys of the first insulating layer.

[0021] In an embodiment, after etching of the gate insulating layer, the gate insulating layer may cover the channel region and a portion adjacent to the channel region of the active layer, and may expose a remaining portion of the active layer.

[0022] In an embodiment, the method may further include, before the forming of the bottom electrode, forming a groove in the substrate by etching the substrate to correspond to a region in which the first electrode portion of the bottom electrode is located.

[0023] In an embodiment, the bottom electrode may be formed on the groove of the substrate and a peripheral portion of the groove.

[0024] In an embodiment, the bottom electrode may be formed to include an opening between the first electrode portion and the second electrode portion.

[0025] In an embodiment, the method may further include forming a second insulating layer covering the active layer, the gate insulating layer, and the gate electrode on the first insulating layer after etching the gate insulating layer.

[0026] In an embodiment, the method may further include forming at least one of a source electrode connected to the source region of the active layer and a drain electrode connected to the drain region of the active layer on the second insulating layer.

[0027] According to a display device and a method for manufacturing a display device according to an embodiment, a stepped portion or valley can be formed below the gate insulating layer corresponding to the region to be formed by extending the gate insulating layer, and the gate insulating layer can be etched after extending the width of the mask used to etch the gate electrode. In some embodiments, a stepped portion or valley can be formed in the gate insulating layer by forming a groove in the substrate or patterning the bottom electrode, corresponding to the region to be formed by extending the gate insulating layer. Therefore, the reflow range of the mask can be appropriately limited in a reflow process, etc., to extend the width of the mask.

[0028] According to embodiments, by using a mask for forming a gate electrode, a gate insulating layer having an extended width or length compared to the gate electrode can be formed below the gate electrode. Therefore, the operating characteristics of the transistor can be improved by appropriately ensuring the effective channel length of the transistor, and the manufacturing process of the display device can be simplified.

[0029] However, the effects according to the embodiments of the present disclosure are not limited to the above-described effects, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a plan view illustrating a display device according to an embodiment;

[0032] Figure 2 It is an icon Figure 1 a plan view of a display panel;

[0033] Figure 3 is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0034] Figure 4 is a schematic cross-sectional view illustrating a display panel according to an embodiment;

[0035] Figure 5 is a schematic plan view showing a bottom electrode according to an embodiment;

[0036] Figures 6 to 18 is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment; and

[0037] Figure 19 and Figure 20 is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0038] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0039] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to physical, electrical, and / or fluid connections, with or without intervening elements. Furthermore, when an element is referred to as being "in contact with," "in contact with," etc., another element, the element may be in "electrical contact" or "physical contact" with the other element; or in "indirect contact" or "direct contact" with the other element.

[0040] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be referred to as the first element.

[0041] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may technically interact differently with each other, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0042] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings were turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the example term "below" can encompass both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0043] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the," as used herein, are intended to include the plural forms as well. In addition, the terms "comprises," "comprising," "includes," and / or "including," when used in this specification, specify the presence of stated features, wholes, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and are thereby used to take into account the inherent deviations in measured, calculated, and / or provided values ​​that will be recognized by one of ordinary skill in the art.

[0044] For the purposes of its meaning and interpretation, in the specification and claims, the phrase "at least one" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B." For the purposes of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in either a conjunction or an antonymous conjunction sense and may be understood to be equivalent to "and / or."

[0045] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined in the specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 is a plan view illustrating a display device 100 according to an embodiment. Figure 2 It is an icon Figure 1 1 is a plan view of the display panel 110.

[0047] Reference Figure 1 and Figure 2 The display device 100 may be a device for displaying moving images or still images. The display device 100 may be used as a display screen for various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, wristwatches, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). However, the present disclosure is not limited thereto, and the display device 100 may be applied to various other types of electronic devices.

[0048] In one embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or an ultra-small light-emitting display using ultra-small light-emitting diodes such as micro- or nano-light-emitting diodes (micro-LEDs or nano-LEDs), but the present disclosure is not limited thereto. For example, the display device 100 may be another type of display device other than a light-emitting display device. Hereinafter, an embodiment in which the display device 100 is an organic light-emitting display device will be disclosed.

[0049] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 configured to supply drive signals to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may include a power supply unit for supplying a power supply voltage to the pixels PX, the first driver 120, and the second driver 130, and a timing controller for controlling the operation of the first driver 120 and the second driver 130.

[0050] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be a region including pixels PX for displaying an image. For example, the display area DA may include a pixel region in which each of the plurality of pixels PX is arranged. The non-display area NDA is a region other than the display area DA, and images may not be displayed in the non-display area NDA. In one embodiment, the non-display area NDA may be located adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA in a plan view.

[0051] exist Figure 1 and Figure 2 In the embodiment, a first direction D1, a second direction D2, and a third direction D3 are defined. In one embodiment, the first direction D1 may be a horizontal direction of the display panel 110, and the second direction D2 may be a vertical direction of the display panel 110. The third direction D3 may be a thickness direction of the display panel 110.

[0052] In one embodiment, the display panel 110 may have a rectangular shape in a plan view. Figure 1 and Figure 2 The display panel 110 is shown as having a horizontal length longer than a vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the vertical length is longer than the horizontal length, or may have a square shape, etc. The display panel 110 may include angled corners or rounded corners.

[0053] The planar shape of the display panel 110 is not limited to the illustrated quadrilateral shape, and the display panel 110 may have other shapes. For example, the display panel 110 may have a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes in a plan view.

[0054] In one embodiment, the display panel 110 may be substantially flat on a plane defined by the first and second directions D1 and D2 and may have a uniform thickness in the third direction D3. In another embodiment, the display panel 110 may be provided in a three-dimensional shape having a curved surface or the like.

[0055] The display panel 110 may be provided as a rigid panel so as not to be substantially deformed, or as a flexible panel that can be deformed to be at least partially folded, bent, or rolled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 with being partially bent.

[0056] The display panel 110 may include a substrate SUB and pixels PX arranged on the substrate SUB. The pixels PX may be arranged in a display area DA on the substrate SUB.

[0057] The substrate SUB, which is a base member for manufacturing or providing the display panel 110, may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA adjacent to the display area DA.

[0058] Depending on the embodiment, the display area DA may have various shapes. For example, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In one embodiment, the display area DA may have a shape corresponding to the shape of the display panel 110, but the present disclosure is not limited thereto.

[0059] The pixels PX may be provided and / or arranged in the display area DA. For example, the display area DA may include a plurality of pixel areas in which each of the plurality of pixels PX is arranged.

[0060] In one embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element positioned in each emission region and a pixel circuit connected to the light-emitting element. In describing the embodiment, the term "connection" may include electrical connection and / or physical connection. Each pixel circuit may include a transistor (e.g., a pixel transistor including a drive transistor that generates a drive current corresponding to a data signal, and at least one switching transistor) and at least one capacitor (e.g., a pixel capacitor including a storage capacitor).

[0061] The non-display area NDA may include a pad area PA in which pads PD are arranged, and may also optionally include a driver circuit area. The driver circuit area may be positioned on at least one side of the display area DA. At least one driver, pads PD, and / or wiring may be arranged in the non-display area NDA.

[0062] In the driver circuit region, at least one driver or a portion of a driver for driving the pixel PX may be disposed. For example, in the driver circuit region on the substrate SUB, circuit elements constituting the first driver 120 (e.g., driver transistors and driver capacitors constituting the stage circuit of the first driver 120) may be disposed. In one embodiment, the circuit elements of the first driver 120 may be formed together with the pixel PX in the display panel 110.

[0063] The pads PD may be arranged in the pad area PA. At least one circuit board 140 may be arranged and / or bonded to the pad area PA. In one embodiment, multiple circuit boards 140 connected to different pads PD may be arranged in the pad area PA. The pads PD may include signal pads and power pads for transmitting drive signals and power supply voltages required to drive the pixels PX and / or the first driver 120 to the display panel 110.

[0064] The first driver 120 and the second driver 130 can generate drive signals for controlling the operation timing, brightness, etc. of the pixel PX, and can supply the generated drive signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver and can be connected to the pixel PX via a corresponding gate line. The first driver 120 can supply corresponding gate signals (for example, control signals that control the drive timing of the pixel PX, including scan signals and / or emission control signals) to the pixel PX. The second driver 130 can be a data driver including a source driver circuit and can be connected to the pixel PX via a corresponding data line. The second driver 130 can supply corresponding data signals to the pixel PX.

[0065] In one embodiment, at least one of the first driver 120 and the second driver 130 or a portion of at least one of the first driver 120 and the second driver 130 may be embedded in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be arranged and / or formed in the non-display area NDA and arranged on the substrate SUB of the display panel 110.

[0066] although Figure 1 The first driver 120 is shown as being formed on one side of the display area DA (e.g., the non-display area NDA on the right side of the display area DA), but the present disclosure is not limited thereto. For example, the first driver 120 may be positioned only on the other side of the display area DA (e.g., the non-display area NDA on the left side of the display area DA), or may be positioned on both sides of the display area DA (e.g., the non-display areas NDA on the left and right sides of the display area DA). In another embodiment, a portion of the first driver 120 may be positioned in the non-display area NDA, and another portion of the first driver 120 may be positioned in a non-emission area within the display area DA (e.g., an area between multiple emission areas of the pixel PX).

[0067] In one embodiment, the other or a portion of the other of the first driver 120 and the second driver 130 may be arranged or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 may be implemented with a plurality of integrated circuit chips and may be arranged on a circuit board 140 electrically connected to the pixels PX of the display panel 110. The second driver 130 may be implemented as at least one integrated circuit chip and mounted on the non-display area NDA of the display panel 110.

[0068] The circuit board 140 may be connected to the display panel 110 via the pads PD. In one embodiment, the circuit board 140 may be a flexible film (such as a flexible printed circuit board (FPCB), a printed circuit board, or a chip on film (COF)), but the present disclosure is not limited thereto. In one embodiment, the circuit board 140 may be connected to the timing controller and / or the power supply unit via another circuit board, a connector, etc.

[0069] Figure 3 1 is a schematic cross-sectional view illustrating a display panel 110 according to an embodiment. For example, Figure 3 A portion of the display area DA of the display panel 110 is schematically illustrated. Figure 3 A light emitting display panel including light emitting elements ED (eg, organic light emitting diodes) is schematically illustrated as an embodiment of the display panel 110. However, the type and / or structure of the display panel 110 is not limited thereto.

[0070] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the display panel 110 may include a substrate SUB (also referred to as a "base layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be arranged on the substrate SUB and overlap each other in a third direction D3. For example, with respect to the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially arranged or formed on the substrate SUB along the third direction D3. However, the present disclosure is not limited thereto, and the positions of the panel circuit layer PCL, the light emitting element layer LEL, and / or the encapsulation layer ENL may be changed.

[0071] In one embodiment, the display panel 110 may further include additional elements provided above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the passivation layer may be provided above the encapsulation layer ENL, or may be provided between the light-emitting element layer LEL and the encapsulation layer ENL.

[0072] The substrate SUB may be a base member for forming the display panel 110 and may be a rigid or flexible substrate (or film). In one embodiment, the substrate SUB may be a substrate including an insulating material such as glass and having rigid characteristics, and may not bend. In another embodiment, the substrate SUB may be a flexible substrate including polyimide or another insulating material and deformable to bend, fold, or curl, and may or may not bend. The type and / or material of the substrate SUB may vary depending on the embodiment.

[0073] In one embodiment, the substrate SUB may include a groove GRV positioned in a region in which the at least one transistor T is arranged. The groove GRV may overlap with a portion of the active layer ACT including the channel region CH and the gate electrode GE included in the at least one transistor T in the third direction D3. The groove GRV may also overlap with a first electrode portion BE1 of the bottom electrode BE positioned below the channel region CH of the active layer ACT in the third direction D3.

[0074] In one embodiment, the display panel 110 may further include a barrier layer (e.g., an inorganic insulating layer capable of blocking moisture penetration) disposed between the substrate SUB and the panel circuit layer PCL. For example, the barrier layer and the panel circuit layer PCL may be sequentially disposed on the substrate SUB, or the panel circuit layer PCL may be disposed (e.g., directly) on the substrate SUB.

[0075] The panel circuit layer PCL may include circuit elements of the pixels PX and / or the first driver 120 (e.g., pixel transistors and pixel capacitors provided to the pixels PX, and / or driver transistors and / or driver capacitors provided to the first driver 120) and wiring (e.g., signal lines and power lines). In one embodiment, the panel circuit layer PCL may include additional conductive patterns (e.g., bridge patterns).

[0076] Figure 3 One transistor T arranged in one pixel area PXA (eg, transistor T connected to the light emitting element ED of the corresponding pixel PX) is schematically illustrated as an embodiment of a circuit element that may be provided or arranged on the panel circuit layer PCL. Figure 3 The transistor T in φX may be a driving transistor or a switching transistor provided in a pixel circuit of a corresponding pixel PX.

[0077] The panel circuit layer PCL may further include a plurality of insulating layers and / or insulating patterns arranged on the substrate SUB. For example, the panel circuit layer PCL may include a first insulating layer INS1, a gate insulating layer GI, a second insulating layer INS2, and a third insulating layer INS3 sequentially arranged on the substrate SUB along the third direction D3.

[0078] In one embodiment, at least one insulating layer provided on the panel circuit layer PCL may be disposed throughout the display area DA. For example, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may be disposed throughout the display area DA.

[0079] In one embodiment, the gate insulating layer GI may be disposed only on a portion of the active layer ACT provided in the transistor T, and may not be disposed on another portion of the active layer ACT. For example, the gate insulating layer GI may be individually disposed corresponding to a region in which each of the plurality of transistors T is formed, and may be an insulating pattern that covers a portion of the active layer ACT provided to the corresponding transistor T and exposes another portion of the active layer ACT.

[0080] The transistor T may include an active layer ACT (also referred to as an "active pattern" or "semiconductor pattern") and a gate electrode GE overlapping a portion of the active layer ACT in a third direction D3. In an embodiment, the transistor T may be a top-gate transistor. For example, the gate electrode GE of the transistor T may be disposed on a gate insulating layer GI covering the active layer ACT.

[0081] In one embodiment, the transistor T may further include at least one of a source electrode SE and a drain electrode DE. For example, the transistor T may further include a source electrode SE connected to the source region SR of the active layer ACT and a drain electrode DE connected to the drain region DR of the active layer ACT. In another embodiment, the transistor T may not include a separate source electrode and / or drain electrode, and the source region SR and / or drain region DR of the active layer ACT may be connected to other circuit elements, wiring, and / or conductive patterns to function as the source electrode SE and / or source electrode DE of the transistor T.

[0082] In an embodiment, a bottom electrode BE (also referred to as a "bottom gate electrode" or "lower electrode") may be disposed below the active layer ACT of the transistor T. In one embodiment, the bottom electrode BE may be connected to an electrode of the transistor T and may function as a back gate electrode to adjust the characteristics of the transistor T. The bottom electrode BE may also be an element included in the transistor T. By disposing the bottom electrode BE below the active layer ACT, it is possible to block external light from entering the active layer ACT (e.g., the channel region CH) and stabilize the operating characteristics of the transistor T.

[0083] In one embodiment, the bottom electrode BE may be connected to the source electrode SE or the gate electrode GE of the transistor T. For example, the transistor T may be a driving transistor of the pixel PX, and the bottom electrode BE may be connected to the source electrode SE of the transistor T. In another embodiment, the transistor T may be a switching transistor of the pixel PX, and the bottom electrode BE may be connected to the gate electrode GE of the transistor T.

[0084] In one embodiment, the transistor T may be an N-type transistor. For example, the transistor T may be an N-type oxide transistor.

[0085] The bottom electrode BE may be provided in a first conductive layer CDL1 on a substrate SUB. In one embodiment, the first conductive layer CDL1 may be disposed between the substrate SUB and the first insulating layer INS1. For example, the first conductive layer CDL1 may be disposed on the substrate SUB and may be covered by the first insulating layer INS1.

[0086] The bottom electrode BE may include a first electrode portion BE1 and second electrode portions BE2 positioned on either side of the first electrode portion BE1. The bottom electrode BE may overlap the active layer ACT in a third direction D3. For example, in the third direction D3, the first electrode portion BE1 of the bottom electrode BE may overlap the channel region CH of the active layer ACT, and the second electrode portion BE2 of the bottom electrode BE may overlap the source region SR and the drain region DR of the active layer ACT.

[0087] In one embodiment, the first electrode portion BE1 of the bottom electrode BE may be disposed on the groove GRV of the substrate SUB. The second electrode portion BE2 of the bottom electrode BE may extend from the first electrode portion BE1 and be disposed on a peripheral portion of the groove GRV of the substrate SUB.

[0088] The bottom electrode BE may have a stepped portion corresponding to the groove GRV of the substrate SUB. For example, the second electrode portion BE2 of the bottom electrode BE may be positioned at a height higher than that of the first electrode portion BE1. In one embodiment, the bottom electrode BE may have a uniform thickness throughout, excluding inclined surfaces, and the height difference between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may correspond to the depth of the groove GRV.

[0089] In one embodiment, the bottom electrode BE may include a valley VAL positioned at a boundary between the first electrode portion BE1 and the second electrode portion BE2 and corresponding to the groove GRV of the substrate SUB. For example, the bottom electrode BE may have a thickness greater than or equal to the depth of the groove GRV formed in the substrate SUB and may have the valley VAL formed around the periphery of the groove GRV.

[0090] The first insulating layer INS1 may be disposed on the bottom electrode BE. In one embodiment, the first insulating layer INS1 may have a valley VAL corresponding to the valley VAL of the bottom electrode BE. For example, the first insulating layer INS1 may include the valley VAL in a corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE and / or in a boundary thereof.

[0091] The active layer ACT may be disposed on the first insulating layer INS1. The active layer ACT may be provided in the semiconductor layer SCL on the substrate SUB. In one embodiment, the semiconductor layer SCL may be disposed on the first insulating layer INS1 covering the first conductive layer CDL1 and may be covered by the gate insulating layer GI and the second insulating layer INS2.

[0092] The active layer ACT may include a channel region CH and a source region SR and a drain region DR spaced apart from each other, with the channel region CH interposed therebetween. For example, the source region SR and the drain region DR may be positioned on the sides of the channel region CH. The channel region CH may be a non-conductive region that maintains semiconductor characteristics. The source region SR and the drain region DR, which have become conductive, may have a higher carrier concentration (e.g., electron concentration) than that of the channel region CH.

[0093] The active layer ACT may overlap the bottom electrode BE and the gate electrode GE in the third direction D3. For example, a portion of the active layer ACT including the channel region CH may overlap the bottom electrode BE and the gate electrode GE in the third direction D3.

[0094] In one embodiment, the channel region CH of the active layer ACT may be arranged on the first electrode portion BE1 of the bottom electrode BE, and the source region SR and the drain region DR of the active layer ACT may be arranged on the second electrode portion BE2 of the bottom electrode BE. In one embodiment, the active layer ACT may have a valley VAL corresponding to the valley VAL of the bottom electrode BE and the first insulating layer INS1. For example, the active layer ACT may include a valley VAL in the corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE and / or in the boundary thereof.

[0095] In one embodiment, the active layer ACT may include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), and another oxide semiconductor. For example, the active layer ACT may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), indium tin gallium zinc oxide (ITGZO), etc.

[0096] In one embodiment, the active layer ACT may be made of a high-mobility oxide semiconductor (eg, having a conductivity greater than or equal to about 20 cm 2 / Vs or about 30cm 2 / Vs mobility oxide semiconductor material). For example, the active layer ACT may include indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO), and may have a conductivity greater than or equal to about 30cm 2 / Vs mobility. In the case where the active layer ACT is formed of a high-mobility oxide semiconductor, the conductivity of the source region SR and the drain region DR can be appropriately and / or easily ensured without performing an additional doping process. In the case where the active layer ACT is formed of a high-mobility oxide semiconductor, the mobility of the transistor T can be appropriately ensured while forming the transistor T having fine dimensions (for example, including the dimensions of the active layer ACT having a width and / or length in the range of approximately several micrometers to several tens of micrometers).

[0097] A gate insulating layer GI (also referred to as a “gate insulating pattern”) may be disposed on the active layer ACT. The gate insulating layer GI may be disposed between the active layer ACT and the gate electrode GE.

[0098] In one embodiment, the gate insulating layer GI may be disposed only on a portion of the active layer ACT and may not be disposed on another portion of the active layer ACT. For example, the gate insulating layer GI may be disposed on a portion of the active layer ACT including the channel region CH and may expose the source region SR and the drain region DR of the active layer ACT.

[0099] Since the gate insulating layer GI exposes the source region SR and the drain region DR, the source region SR and the drain region DR can be properly and / or easily conductive during the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI so that at least a portion of each of the source region SR and the drain region DR is exposed, oxygen vacancies can be formed in the source region SR and the drain region DR by etching gas, etc. Therefore, the source region SR and the drain region DR can be properly conductive in a subsequent process (for example, a process of forming the second insulating layer INS2) without performing a separate doping process.

[0100] In one embodiment, in order to limit the carrier concentration of the source region SR and the drain region DR and / or the mobility of the active layer ACT to an appropriate range, an oxygen supply layer may be formed between the gate insulating layer GI and the gate electrode GE. For example, the transistor T may be arranged between the gate insulating layer GI and the gate electrode GE and may further include an oxygen supply layer including an oxide semiconductor. The active layer ACT and the oxygen supply layer of the transistor T may include the same oxide semiconductor or different oxide semiconductors.

[0101] In an embodiment, the gate insulating layer GI may have a length in the longitudinal direction of the channel region CH of the active layer ACT (e.g., in a direction from an end of the channel region CH adjacent to the source region SR to the other end of the channel region CH adjacent to the drain region DR) that is greater than the length of the gate electrode GE above the gate insulating layer GI. For example, the gate insulating layer GI may protrude beyond both sides of the gate electrode GE in the longitudinal direction of the channel region CH. Therefore, the gate insulating layer GI may cover a portion of the active layer ACT that overlaps with the gate electrode GE in the third direction D3, and may also cover another portion of the active layer ACT that is adjacent to the portion of the active layer ACT and does not overlap with the gate electrode GE in the third direction D3. For example, the gate insulating layer GI may cover at least a portion of the active layer ACT including the channel region CH, and may also cover another portion of the active layer ACT including a portion of each of the source region SR and the drain region DR that is adjacent to the channel region CH. The gate insulating layer GI may not be disposed on the remaining portion of the active layer ACT (eg, on the remaining portion of each of the source and drain regions SR and DR), and thus may expose the remaining portion of each of the source and drain regions SR and DR.

[0102] The gate insulating layer GI may extend over both sides of the gate electrode GE to further cover a portion of each of the source region SR and the drain region DR, thereby appropriately extending and / or ensuring the effective channel length of the transistor T. Therefore, the operating characteristics of the transistor T may be improved and / or ensured.

[0103] In one embodiment, an end portion of the gate insulating layer GI may be positioned over the valley VAL of the active layer ACT. For example, the gate insulating layer GI may have a width and / or length extending from an upper portion of the channel region CH of the active layer ACT to an upper portion of the valley VAL region of the active layer ACT. In one embodiment, the gate insulating layer GI may cover the valley VAL of the active layer ACT and may have a valley VAL corresponding to the valley VAL of the bottom electrode BE, the first insulating layer INS1, and the active layer ACT. For example, the gate insulating layer GI may include the valley VAL in the corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE and / or in the boundary thereof.

[0104] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be provided in the second conductive layer CDL2 on the substrate SUB. In one embodiment, the second conductive layer CDL2 may be disposed on the gate insulating layer GI and may be covered by the second insulating layer INS2.

[0105] The gate electrode GE may be disposed on the active layer ACT and overlap the channel region CH in the third direction D3. The gate electrode GE and the active layer ACT may be separated and / or spaced apart from each other with a gate insulating layer GI interposed therebetween.

[0106] The second insulating layer INS2 may be disposed on the gate electrode GE. The second insulating layer INS2 may cover the active layer ACT, the gate insulating layer GI, and the gate electrode GE.

[0107] The source electrode SE and the drain electrode DE may be disposed on the second insulating layer INS2. The source electrode SE and the drain electrode DE may be provided in a third conductive layer CDL3 on the substrate SUB. In one embodiment, the third conductive layer CDL3 may be disposed on the second insulating layer INS2 and may be covered by the third insulating layer INS3.

[0108] The source electrode SE may be connected to a portion of the active layer ACT. For example, the source electrode SE may be connected to the source region SR via at least one contact hole penetrating the second insulating layer INS2. In one embodiment, the source electrode SE may also be connected to the bottom electrode BE via at least one contact hole penetrating the first insulating layer INS1 and the second insulating layer INS2.

[0109] The drain electrode DE may be connected to another portion of the active layer ACT. For example, the drain electrode DE may be connected to the drain region DR through at least one contact hole penetrating the second insulating layer INS2.

[0110] In one embodiment, the display panel 110 may further include a Figure 1 and Figure 2 The driver transistor in the driver circuit area of ​​the first driver 120, etc. At least one driver transistor among the plurality of driver transistors may have a similar Figure 3 For example, the display panel 110 may include a groove formed in the substrate SUB in a transistor region corresponding to at least one driver transistor, and may include a bottom electrode arranged on the groove and having a stepped portion and / or valley corresponding to the groove, and a driver transistor arranged on the bottom electrode. A gate insulating layer may be arranged between the active layer and the gate electrode of the driver transistor, the gate insulating layer covering a portion of the channel region including the active layer, the portion having a length and / or width greater than that of the gate electrode and protruding beyond the side of the gate electrode.

[0111] The third insulating layer INS3 may be disposed on the circuit elements of the panel circuit layer PCL. The circuit elements include Figure 3 The third insulating layer INS3 may be disposed on the second insulating layer INS2 and may cover the circuit elements provided in the panel circuit layer PCL. For example, the third insulating layer INS3 may cover the source electrode SE and the drain electrode DE provided in the third conductive layer CDL3.

[0112] In one embodiment, the third insulating layer INS3 may have a multi-layer structure including an inorganic insulating layer and an organic insulating layer. For example, the third insulating layer INS3 may include an inorganic layer IOL and an organic layer ORL sequentially disposed on the second insulating layer INS2.

[0113] The corresponding electrodes, conductive patterns, and / or wiring provided in the conductive layers of the panel circuit layer PCL may include at least one conductive material. For example, the electrodes, conductive patterns, and / or wiring provided in each of the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), another metal, an alloy thereof, and another conductive material. In one embodiment, the electrodes, conductive patterns, and / or wiring arranged in the same conductive layer may be formed simultaneously using the same conductive material.

[0114] In one embodiment, each of the electrodes, conductive patterns, and / or wirings provided in the conductive layers of the panel circuit layer PCL may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wirings provided in the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may have a single-layer or multi-layer structure.

[0115] In one embodiment, each of the inorganic layers IOL of the first insulating layer INS1, the gate insulating layer GI, the second insulating layer INS2, and the third insulating layer INS3 may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide) or another inorganic insulating material. For example, each of the inorganic layers IOL of the first insulating layer INS1, the gate insulating layer GI, the second insulating layer INS2, and the third insulating layer INS3 may be a single layer or a plurality of layers of inorganic insulating layers.

[0116] In one embodiment, the organic layer ORL of the third insulating layer INS3 may include at least one organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin) or another organic insulating material. The surface (e.g., top surface) of the organic layer ORL may be substantially flat.

[0117] The light emitting element layer LEL may be disposed on the panel circuit layer PCL. For example, the light emitting element layer LEL may be positioned at least in the display area DA and may be disposed on the third insulating layer INS3.

[0118] The light emitting element layer LEL may include a light emitting element ED for each of the plurality of pixels PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that divides the emission area of ​​the pixel PX and the light emitting element ED positioned in each emission area. In one embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0119] Each of the plurality of light emitting elements ED may include a first electrode ET1 positioned in each emission region and a light emitting layer EML and a second electrode ET2 sequentially arranged on the first electrode ET1. The first electrode ET1 of the light emitting element ED may be connected to at least one pixel transistor (e.g., Figure 3 The transistor T in FIG.

[0120] The first electrode ET1 of the light emitting element ED may be a single-layer or multi-layer electrode including at least one conductive material. In one embodiment, the display panel 110 may be a top emission type display panel, and the first electrode ET1 may include a metal material having high reflectivity.

[0121] The light emitting layer EML of the light emitting element ED may include a polymer material or a low molecular material. Light emitted from the light emitting layer EML may contribute to image display.

[0122] The second electrode ET2 of the light-emitting element ED may include a conductive material. In one embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA and cover the light-emitting layer EML and the pixel-defining layer PDL. In one embodiment, the display panel 110 may be a top-emission display panel, and the second electrode ET2 may include a transparent or semi-transparent conductive material.

[0123] The pixel-defining layer (PDL) may have an opening corresponding to each emission region and may surround the emission region in a plan view. For example, in a plan view, the pixel-defining layer (PDL) may cover the edge of the first electrode ET1 of the light-emitting element ED and may include an opening that exposes the remaining portion of the first electrode ET1. The area where the exposed first electrode ET1 and the light-emitting layer (EML) overlap in the third direction (D3) may be the emission region of each pixel PX. In one embodiment, the pixel-defining layer (PDL) may include at least one organic insulating layer comprising an organic insulating material.

[0124] The spacer SPC may be disposed on a portion of the pixel defining layer (PDL). The spacer SPC may include at least one organic insulating layer containing an organic insulating material. The spacer SPC and the pixel defining layer (PDL) may include the same material or different materials. The pixel defining layer (PDL) and the spacer SPC may be formed sequentially using a mask process, or may be formed simultaneously and / or integrally using a halftone mask.

[0125] The encapsulation layer ENL may be disposed on the light-emitting element layer LEL. The encapsulation layer ENL may cover the light-emitting element layer LEL in the display area DA and may extend into the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light-emitting element layer LEL and may reduce electrical and / or physical effects on the panel circuit layer PCL and the light-emitting element layer LEL.

[0126] In one embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially arranged on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer including an organic material.

[0127] Figure 4 1 is a schematic cross-sectional view illustrating a display panel 110 according to an embodiment. For example, Figure 4 A portion of the display area DA of the display panel 110 is schematically illustrated, and Figure 4 Implementation of the display panel 110 and Figure 3 The embodiments of the display panel 110 may differ with respect to the bottom electrode BE and the like.

[0128] Figure 5 : is a schematic plan view showing a bottom electrode BE according to an embodiment. For example, Figure 5 Schematically shows Figure 4 In the description of the embodiment of the bottom electrode BE Figure 4 and Figure 5 In the embodiment of Figure 3 Redundant description of components of the embodiments that are substantially the same or similar.

[0129] Apart from Figures 1 to 3 In addition, refer to Figure 4 and Figure 5 , Figure 4 The substrate SUB may not include Figure 3The groove GRV is shown in FIG. The first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be spaced apart from each other in the region where the bottom electrode BE and the active layer ACT overlap. In one embodiment, the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may have the same thickness and / or height.

[0130] In one embodiment, the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be connected to each other, such as Figure 5 For example, the bottom electrode BE may include an opening OP positioned between the first electrode portion BE1 and the second electrode portion BE2, and the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be connected to each other in a region in which the active layer ACT does not overlap with the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE in the third direction D3.

[0131] However, Figure 5 Only the diagram shows the Figure 4 The shape and / or structure of the bottom electrode BE of the embodiment of the present disclosure are not limited thereto. For example, in another embodiment, the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be separated from each other. In one embodiment, the first electrode portion BE1 of the bottom electrode BE may be connected to one electrode of the transistor T (e.g., the source electrode SE or the gate electrode GE) and may have a shape and / or size corresponding to the electrode. In another embodiment, the first electrode portion BE1 of the bottom electrode BE may not be connected to the transistor T. In one embodiment, the second electrode portion BE2 of the bottom electrode BE may be spaced apart from the first electrode portion BE1 and may be connected to a wiring located at the periphery (e.g., a power line supplying a constant voltage), or may be floating.

[0132] In an embodiment, the first insulating layer INS1 and the active layer ACT disposed on the bottom electrode BE may have a valley VAL depending on the shape and / or structure of the bottom electrode BE. For example, the first insulating layer INS1 and the active layer ACT may include a stepped portion and / or a valley VAL in a corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE1.

[0133] In embodiments, the gate insulating layer GI may have a length greater than that of the gate electrode GE in the longitudinal direction of the channel region CH of the active layer ACT and may protrude beyond the sides of the gate electrode GE. For example, the gate insulating layer GI may cover portions of each of the source region SR and the drain region DR that do not overlap with the gate electrode GE around the channel region CH. Thus, the effective channel length of the transistor T may be appropriately extended and / or ensured, and the operating characteristics of the transistor T may be improved and / or ensured.

[0134] In one embodiment, the gate insulating layer GI may terminate on the stepped portion and / or valley VAL of the first insulating layer INS1 and the active layer ACT. Thus, an end of the gate insulating layer GI may be positioned on the valley VAL of the first insulating layer INS1 and the active layer ACT.

[0135] Figures 6 to 18 is a schematic cross-sectional view illustrating a method for manufacturing the display device 100 according to an embodiment. For example, Figures 6 to 18 The sequence diagram shows the Figure 3 The step of forming a bottom electrode BE and a transistor T on a substrate SUB is included in the step of manufacturing a display panel 110.

[0136] Apart from Figures 1 to 3 In addition, refer to Figure 6 , a substrate SUB including at least a display area DA may be prepared. In one embodiment, the substrate SUB may be a glass substrate, but the present disclosure is not limited thereto. The display area DA may include a pixel area PXA.

[0137] Thereafter, a first mask M1 (eg, a photoresist pattern) may be disposed on the substrate SUB. The first mask M1 may expose the groove GRV of the substrate SUB in which the groove GRV is to be formed. Figure 3 The first mask M1 may be arranged on the substrate SUB to expose a portion of the substrate SUB for forming the groove GRV and cover the remaining area of ​​the substrate SUB. Figure 3 In the transistor region corresponding to the transistor T in FIG.

[0138] Apart from Figures 1 to 6 In addition, refer to Figure 7 , a groove GRV can be formed in the substrate SUB by selectively etching the exposed area of ​​the substrate SUB using the first mask M1. For example, the groove GRV can be formed in the substrate SUB by etching the portion of the substrate SUB not covered by the first mask M1 to a thickness using a dry etching process or the like. Therefore, the groove GRV can be formed in the substrate SUB corresponding to the area in which the first electrode portion BE1 of the bottom electrode BE is to be positioned. In one embodiment, the groove GRV can be formed to be longer than or equal to the width and / or length in which the first electrode portion BE1 of the bottom electrode BE is to be formed. After the groove GRV is formed in the substrate SUB, the first mask M1 can be removed.

[0139] Apart from Figures 1 to 7 In addition, refer to Figure 8A first conductive layer CDL1 including a bottom electrode BE may be formed on the substrate SUB. For example, the first conductive layer CDL1 may be formed by applying at least one conductive material as described above to the substrate SUB including the groove GRV, and the bottom electrode BE may be formed by performing a patterning process (e.g., an etching process using a mask) on the first conductive layer CDL1.

[0140] In one embodiment, the bottom electrode BE may be formed of a multilayer metal electrode. For example, a first metal layer including titanium (Ti), a second metal layer including aluminum (Al), and a third metal layer including titanium (Ti) may be sequentially formed on the substrate SUB including the groove GRV. The first, second, and third metal layers may be etched to form a bottom electrode BE having a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The material and / or structure of the bottom electrode BE may vary depending on the embodiment.

[0141] The bottom electrode BE may be formed on the groove GRV of the substrate SUB and the peripheral portion of the groove GRV. For example, the bottom electrode BE may include a first electrode portion BE1 disposed on the groove GRV of the substrate SUB and a second electrode portion BE2 positioned on a side of the first electrode portion BE1 and disposed on the peripheral portion of the groove GRV of the substrate SUB.

[0142] In one embodiment, the bottom electrode BE may have a shape corresponding to the groove GRV of the substrate SUB. For example, the bottom electrode BE may have a stepped portion and / or a valley VAL corresponding to the groove GRV.

[0143] Apart from Figures 1 to 8 In addition, refer to Figure 9 A first insulating layer INS1 may be formed on the substrate SUB, covering the bottom electrode BE. In one embodiment, the first insulating layer INS1 may have a stepped portion and / or a cross-sectional shape corresponding to the stepped portion and / or cross-sectional shape of the bottom electrode BE. For example, the first insulating layer INS1 may include a valley VAL in a corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE.

[0144] The first insulating layer INS1 can be formed by a film formation process using at least one insulating material (e.g., an inorganic insulating material) as described above. In one embodiment, the first insulating layer INS1 can be formed of two or more inorganic insulating layers. For example, by sequentially forming a first inorganic insulating layer made of silicon nitride and a second inorganic insulating layer made of silicon oxide on a substrate SUB having a bottom electrode BE formed thereon, a double-layered first insulating layer INS1 including a first inorganic insulating layer and a second inorganic insulating layer on the first inorganic insulating layer can be formed. The material and / or structure of the first insulating layer INS1 may vary depending on the embodiment.

[0145] Apart from Figures 1 to 9 In addition, refer to Figure 10 , a semiconductor layer SCL including an active layer ACT and the like may be formed on the first insulating layer INS1. For example, the active layer ACT may be formed in each transistor region on the substrate SUB.

[0146] The active layer ACT may be formed to overlap the bottom electrode BE in the third direction D3. For example, the active layer ACT may overlap the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE in the third direction D3. In one embodiment, the active layer ACT may have a stepped portion and / or cross-sectional shape corresponding to that of the first insulating layer INS1. For example, the active layer ACT may include a valley VAL in the corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE.

[0147] In one embodiment, the active layer ACT may be formed by a film formation process using a semiconductor layer of at least one oxide semiconductor as described above and a patterning process (e.g., an etching process using a mask). For example, after forming a semiconductor layer made of indium gallium zinc oxide (IGZO) on the first insulating layer INS1, the active layer ACT may be formed by etching (e.g., wet etching) the semiconductor layer. Depending on the embodiment, the material of the active layer ACT may vary.

[0148] Apart from Figures 1 to 10 In addition, refer to Figure 11 A gate insulating layer GI covering the active layer ACT may be formed on the first insulating layer INS1. In one embodiment, the gate insulating layer GI may be first completely formed on the substrate SUB including the display area DA and the like.

[0149] The gate insulating layer GI may be formed by a film forming process using at least one insulating material (e.g., an inorganic insulating material) as described above. For example, the gate insulating layer GI including silicon oxide may be formed by depositing silicon oxide on the first insulating layer INS1 on which the active layer ACT and the like are formed. The material of the gate insulating layer GI may vary depending on the embodiment.

[0150] In one embodiment, the gate insulating layer GI may have a stepped portion and / or cross-sectional shape corresponding to those of the first insulating layer INS1 and the active layer ACT. For example, the gate insulating layer GI may include a valley VAL in a corresponding region between the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE.

[0151] Apart from Figures 1 to 11 In addition, refer to Figure 12 , a conductive layer GCDL covering the gate insulating layer GI may be formed on the substrate SUB. The conductive layer GCDL may be used to form a Figure 3 The second conductive layer CDL2 of the gate electrode GE in the display area DA may be formed completely first, such as to extend over the display area DA. For example, the conductive layer GCDL may be formed completely on the gate insulating layer GI. The conductive layer GCDL may be formed by a film formation process using at least one conductive material as described above. In one embodiment, the conductive layer GCDL may have a stepped portion and / or cross-sectional shape corresponding to the stepped portion and / or cross-sectional shape of the gate insulating layer GI.

[0152] In one embodiment, the conductive layer GCDL may be formed of multiple metal layers. For example, a first metal layer including titanium (Ti), a second metal layer including aluminum (Al), and a third metal layer including titanium (Ti) may be sequentially formed on the gate insulating layer GI. Therefore, in subsequent processes, the gate electrode GE formed by the conductive layer GCDL may be formed into a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The materials and / or structures of the conductive layer GCDL and the gate electrode GE formed by the conductive layer GCDL may vary depending on the embodiment.

[0153] Apart from Figures 1 to 12 In addition, refer to Figure 13 A second mask M2 (e.g., a photoresist pattern) for patterning electrodes, wirings, and / or patterns provided in the second conductive layer CDL2 may be disposed on the conductive layer GCDL. For example, to form the gate electrode GE on the first electrode portion BE1 of the bottom electrode BE, the second mask M2 may be disposed on the conductive layer GCDL to overlap with the first electrode portion BE1 of the bottom electrode BE.

[0154] In one embodiment, after arranging the second mask M2, a heat treatment process may be performed at a temperature sufficient to slightly reflow the second mask M2, so that the second mask M2 can be made to have a flatter curve. For example, by performing a first hard baking process on the second mask M2 at a temperature of approximately 130°C, the side surface shape of the second mask M2 can be slightly modified. Therefore, in a subsequent process (for example, an etching process of the conductive layer GCDL using the second mask M2), the shape (for example, the side surface inclination) of the electrode, wiring and / or pattern of the second conductive layer CDL2 patterned by the conductive layer GCDL can be appropriately controlled. For example, by heat treating the second mask M2 so that the second mask M2 has a flatter curve, the side surface inclination of the gate electrode GE can be controlled to be flatter. Therefore, disconnection of the upper layer and / or pattern formed on the gate electrode GE can be prevented.

[0155] Apart from Figures 1 to 13 In addition, refer to Figure 14 By etching (e.g., dry etching) the conductive layer GCDL using the second mask M2, a second conductive layer CDL2 including the gate electrode GE may be formed and / or patterned. For example, the gate electrode GE may be formed under the second mask M2 disposed on the first electrode portion BE1 of the bottom electrode BE.

[0156] Apart from Figures 1 to 14 In addition, refer to Figure 15 The width of the second mask M2 can be extended by performing an additional heat treatment process on the second mask M2 to reflow the second mask M2. For example, a second hard bake process can be performed on the second mask M2 at a sufficient temperature so that the second mask M2 can reflow and the width of the second mask M2 can be extended to be greater than or equal to the width of the gate electrode GE. For example, the width of the second mask M2 can be extended by performing a second hard bake process on the second mask M2 at a temperature in the range of approximately 135°C to approximately 150°C. Thus, a second mask M2' covering the side surface of the gate electrode GE and having a more extended width can be formed on the gate electrode GE. The heat treatment temperature for the second mask M2 can be varied differently taking into account the material properties of the second mask M2, the substrate SUB, and / or the elements arranged on the substrate SUB, process conditions, etc.

[0157] In one embodiment, the backflow of the second mask M2 can be controlled by a step portion and / or valley VAL formed in the gate insulating layer GI, etc. For example, the step portion and / or valley VAL formed in the gate insulating layer GI can serve as a dam to control or limit the backflow range of the second mask M2. Therefore, the end of the second mask M2' having a width extended by the backflow can be positioned on the valley VAL of the first insulating layer INS1, the active layer ACT, and / or the gate insulating layer GI formed on the step portion of the bottom electrode BE (e.g., the boundary region between the first electrode portion BE1 and the second electrode portion BE2).

[0158] Apart from Figures 1 to 15 In addition, refer to Figure 16 By etching (e.g., dry etching) the gate insulating layer GI using a second mask M2' having a more extended width, a gate insulating layer GI can be formed that covers a portion of the active layer ACT and exposes another portion of the active layer ACT while having a width and / or length greater than the width and / or length of the gate electrode GE. For example, the gate insulating layer GI can be etched to cover the portion of the active layer ACT that overlaps with the second mask M2', while exposing another portion of the active layer ACT in the third direction D3. Thus, a gate insulating layer GI can be formed under the second mask M2', overlapping the gate electrode GE in the third direction D3 and having a width and / or length greater than the width and / or length of the gate electrode GE. For example, the etched gate insulating layer GI can cover the channel region CH of the active layer ACT that overlaps with the gate electrode GE and portions adjacent to the channel region CH (e.g., portions of the source region SR and the drain region DR), while exposing the remaining portion of the active layer ACT (e.g., the remaining portion of the source region SR and the drain region DR).

[0159] By etching the gate insulating layer GI using the second mask M2′ having a wider width using a reflow method or the like, the gate insulating layer GI can be formed to have a size that is wider than the gate electrode GE without adding a process of forming a separate mask. Therefore, the manufacturing process of the display device 100 can be simplified, and manufacturing efficiency can be improved.

[0160] In one embodiment, by adjusting the position and / or size (e.g., width, length, and / or depth) of the groove GRV formed in the substrate SUB, the shape of the gate insulating layer GI and / or the formation area and length of the gate insulating layer GI can be adjusted. The effective channel length of the transistor T can be appropriately adjusted by adjusting the formation area and length of the gate insulating layer GI.

[0161] After etching the gate insulating layer GI, the second mask M2' may be removed. For example, the second mask M2' may be removed by a stripping or ashing process.

[0162] In the process of etching the gate insulating layer GI, the properties of the active layer ACT may be changed so that multiple portions of the active layer ACT have different characteristics. Therefore, the active layer ACT may be divided into multiple regions with different characteristics.

[0163] For example, mainly at the portion not covered by the etched gate insulating layer GI, oxide bonds may be broken to release oxygen, and oxygen vacancies may occur in the oxide semiconductor constituting the active layer ACT due to etching gas, etc. Therefore, the active layer ACT may be divided into a plurality of regions with different characteristics (e.g., a channel region CH, a source region SR, and a drain region DR). In one embodiment, oxygen vacancies may mainly occur at a portion of the active layer ACT that does not overlap with the gate insulating layer GI in the third direction D3 (e.g., the source region SR and the drain region DR), and may diffuse to a portion of the region overlapping with the gate insulating layer GI and / or the gate electrode GE in the third direction D3.

[0164] In one embodiment, because the gate insulating layer GI has a width and / or length greater than that of the gate electrode GE and is formed to extend to the sides of the gate electrode GE, the length and / or area of ​​the region in the active layer ACT where the source region SR and the drain region DR extend can be reduced, thereby appropriately extending and / or ensuring the effective channel length of the channel region CH. For example, by forming the gate insulating layer GI having a more extended width and / or length below the gate electrode GE using the second mask M2′ having an extended width, the range of the source region SR and the drain region DR where oxygen vacancies diffuse during the etching process of the gate insulating layer GI and / or the amount of hydrogen introduced into the source region SR and the drain region DR during subsequent processes (e.g., the formation process of the second insulating layer INS2) can be reduced. Consequently, the threshold voltage roll-off of the transistor T can be prevented, and the operating characteristics of the transistor T can be improved and / or stabilized.

[0165] By covering a portion of the active layer ACT to a degree greater than or equal to the width and / or length of the gate electrode GE, the length of the effective channel formed in the channel region CH can be extended and / or ensured even though the size of the transistor T (e.g., the length of the channel region CH) is reduced in the high-resolution display device 100. Therefore, even in the high-resolution display device 100 including the transistor T of a smaller size, the operating characteristics of the transistor T can be appropriately and / or easily improved.

[0166] By covering a portion of the active layer ACT positioned adjacent to the gate electrode GE with the gate insulating layer GI having an extended width and / or length as compared to the gate electrode GE, a short circuit defect that may occur between the gate electrode GE and the active layer ACT of the transistor T can be prevented. Therefore, the reliability of the transistor T and the display device 100 including the transistor T can be ensured.

[0167] Apart from Figures 1 to 16 In addition, refer to Figure 17 , a second insulating layer INS2 may be formed on the first insulating layer INS1. The second insulating layer INS2 may be formed entirely on the display area DA to cover the active layer ACT, the gate insulating layer GI, and the gate electrode GE. The second insulating layer INS2 may be formed by a film formation process using an insulating layer of at least one insulating material (e.g., an inorganic insulating material) as described above.

[0168] In one embodiment, the second insulating layer INS2 may be formed of two or more inorganic insulating layers. For example, a double-layered second insulating layer INS2 may be formed by sequentially forming a first inorganic insulating layer made of silicon oxide and a second inorganic insulating layer made of silicon nitride on the first insulating layer INS1 having the active layer ACT, the gate insulating layer GI, and the gate electrode GE formed thereon. The material and / or structure of the second insulating layer INS2 may vary depending on the embodiment.

[0169] During the process of forming the second insulating layer INS2, hydrogen may be introduced into the active layer ACT. When hydrogen is introduced into the active layer ACT primarily at a portion containing a large number of oxygen vacancies, a portion of the active layer ACT may become conductive (e.g., N-type conductive). For example, the source region SR and the drain region DR may be formed to be conductive.

[0170] In one embodiment, a portion of each of the source region SR and the drain region DR adjacent to the channel region CH may be covered by the gate insulating layer GI, and thus the amount of hydrogen introduced into the source region SR and the drain region DR and / or the formation range of the source region SR and the drain region DR may be controlled or reduced. Thus, the length of the channel region CH and / or the effective channel formed in the channel region CH may be extended and / or ensured.

[0171] In one embodiment, after forming the second insulating layer INS2, a contact hole CNT exposing a portion of each of the plurality of active layers ACT may be formed in the second insulating layer INS2. For example, the contact hole CNT exposing a portion of each of the source region SR and the drain region DR may be formed by etching the second insulating layer INS2 using a mask (e.g., dry etching). In one embodiment, in the case where the bottom electrode BE is connected to the source electrode SE, the contact hole CNT exposing a portion of the bottom electrode BE may be formed in the second insulating layer INS2 and the first insulating layer INS1. Figure 17 , only one contact hole CNT among the plurality of contact holes CNT formed in the second insulating layer INS2 and / or the first insulating layer INS1 is denoted by a reference numeral.

[0172] Apart from Figures 1 to 17In addition, refer to Figure 18 , a third conductive layer CDL3 including a source electrode SE and a drain electrode DE may be formed on the second insulating layer INS2. For example, the third conductive layer CDL3 may be formed by applying at least one conductive material as described above on the second insulating layer INS2 having the contact hole CNT formed therein, and a patterning process (e.g., an etching process using a mask) of the third conductive layer CDL3 may be performed to form the source electrode SE and the drain electrode DE.

[0173] The source electrode SE may be formed to be connected to the source region SR of the active layer ACT, and the drain electrode DE may be formed to be connected to the drain region DR of the active layer ACT. In one embodiment, the source electrode SE may be formed to be connected to the bottom electrode BE. In one embodiment, at least one of the source electrode SE and the drain electrode DE may not be formed, with at least one of the source region SR and the drain region DR replacing at least one of the source electrode SE and the drain electrode DE.

[0174] Through the above process, a plurality of pixel transistors including the transistor T can be formed in the display area DA. In one embodiment, the driver transistor can be formed in the drive circuit region in a manner substantially the same as or similar to the above embodiment. For example, the pixel transistors and the driver transistor can be formed simultaneously on the display panel 110. In one embodiment, elements provided on the same conductive layer or the same semiconductor layer in the display panel 110 can be formed simultaneously.

[0175] After forming the transistor T, the formation of Figure 3 The third insulating layer INS3 may cover the circuit elements, wirings and / or conductive patterns of the panel circuit layer PCL including the transistor T. Thus, the panel circuit layer PCL of the display panel 110 may be formed.

[0176] In one embodiment, when the display panel 110 includes a light emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL. Figure 3 A display panel 110 according to an embodiment and a display device 100 including the display panel 110 are provided.

[0177] Figure 19 and Figure 20 1 is a schematic cross-sectional view illustrating a method for manufacturing the display device 100 according to an embodiment. For example, Figure 19 and Figure 20 The manufacturing sequence is shown in FIG Figure 4Among the steps of forming the display panel 110, the bottom electrode BE and the first insulating layer INS1 are formed on the substrate SUB. The steps of forming the active layer ACT, the gate insulating layer GI, the gate electrode GE, the second insulating layer INS2, the source electrode SE, the drain electrode DE, etc., which are performed after the first insulating layer INS1 is formed, can be performed in a manner substantially the same as or similar to that of the aforementioned embodiment.

[0178] Apart from Figures 1 to 18 In addition, refer to Figure 19 and Figure 20 , a bottom electrode BE and a first insulating layer INS1 may be sequentially formed on the substrate SUB. The bottom electrode BE may be formed to include an opening OP between the first electrode portion BE1 and the second electrode portion BE2. For example, the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be formed to be first connected to each other and disconnected from each other in a region where the bottom electrode BE and the active layer ACT overlap in the third direction D3. In another embodiment, the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE may be formed independently of each other. Therefore, the first insulating layer INS1 formed on the substrate SUB to cover the bottom electrode BE after the bottom electrode BE is formed may have a step portion and / or a valley VAL according to the shape and / or structure of the bottom electrode BE. As Figure 4 As shown in FIG, the active layer ACT and the gate insulating layer GI formed on the first insulating layer INS1 may have a stepped portion and / or a valley VAL according to the shape and / or structure of the bottom electrode BE and the first insulating layer INS1.

[0179] Therefore, a mask for controlling (eg, a mask for controlling the active layer ACT) may be formed in the first insulating layer INS1, the active layer ACT, and / or the gate insulating layer GI. Figures 13 to 16 The second mask M2 and the second mask M2') in the backflow step portion and / or valley VAL, which is used to pattern the gate electrode GE and the gate insulating layer GI in a subsequent process without forming a groove GRV in the substrate SUB. Figure 3 Compared with the display panel 110 of the embodiment of the present invention, fewer masks can be used to manufacture the display panel according to the embodiment of the present invention. Figure 4 For example, in manufacturing the display panel 110 according to the embodiment of Figure 4 When the display panel 110 of the embodiment is used, the Figure 6 and Figure 7 1 and 2. In one embodiment, the region where the gate insulating layer GI is formed may be adjusted by adjusting the position and size of the first electrode portion BE1 and the second electrode portion BE2 of the bottom electrode BE and / or the distance therebetween (or the size of the opening OP).

[0180] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and variations. Therefore, the above-mentioned embodiments of the present disclosure may be implemented individually or in combination with each other.

[0181] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are used to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the accompanying claims, and should be interpreted as all technical spirits within the scope of equivalents are included in the scope of this disclosure.

Claims

1. A display device, characterized in that: include: a bottom electrode disposed on the substrate and including a first electrode portion and a second electrode portion positioned on a side of the first electrode portion; a first insulating layer, disposed on the substrate and covering the bottom electrode; an active layer, the active layer being arranged on the first insulating layer and comprising a channel region and a source region and a drain region, the channel region being arranged on the first electrode portion of the bottom electrode, the source region and the drain region being arranged on the second electrode portion of the bottom electrode; a gate insulating layer disposed on a portion of the active layer including the channel region and exposing the source region and the drain region; as well as a gate electrode disposed on the gate insulating layer and overlapping the channel region of the active layer in a thickness direction of the substrate, wherein the first insulating layer and the active layer include valleys in corresponding regions between the first electrode portion and the second electrode portion of the bottom electrode, and The gate insulating layer includes an end portion positioned on the valley of the active layer, and has a length greater than a length of the gate electrode in a longitudinal direction of the channel region.

2. The display device according to claim 1, wherein The gate insulating layer protrudes beyond a side surface of the gate electrode in the longitudinal direction of the channel region and covers a portion of each of the source region and the drain region adjacent to the channel region.

3. The display device according to claim 1, wherein The substrate includes a groove overlapping the channel region and the gate electrode in the thickness direction.

4. The display device according to claim 3, wherein: The first electrode portion of the bottom electrode is disposed on the groove of the substrate.

5. The display device according to claim 4, wherein: The second electrode portion of the bottom electrode extends from the first electrode portion, is disposed on a peripheral portion of the groove of the substrate, and has a height greater than that of the first electrode portion, and The bottom electrode includes a valley positioned at a boundary between the first electrode portion and the second electrode portion and corresponding to the groove of the substrate.

6. The display device according to claim 1, wherein The first electrode portion and the second electrode portion of the bottom electrode are spaced apart from each other in a region where the channel region is connected to the source region and the drain region.

7. The display device according to claim 1, wherein The bottom electrode includes an opening positioned between the first electrode portion and the second electrode portion.

8. The display device according to claim 1, wherein Also includes: a second insulating layer disposed on the first insulating layer and covering the active layer, the gate insulating layer, and the gate electrode.

9. The display device according to claim 8, wherein Also included is a first transistor, the first transistor comprising at least one of the following: a source electrode disposed on the second insulating layer and connected to the source region of the active layer; as well as A drain electrode is disposed on the second insulating layer and connected to the drain region of the active layer.

10. The display device according to claim 9, wherein Also includes: a third insulating layer disposed on the second insulating layer and covering at least one of the source electrode and the drain electrode; a light emitting element layer, the light emitting element layer including a light emitting element arranged on the third insulating layer; as well as An encapsulation layer covers the light-emitting element layer.

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