Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a plurality of repeating units, at least one repeating unit comprises a display unit and a light-transmitting unit, the display unit is configured to display images on the two sides, and the light-transmitting unit is configured to transmit light; the display unit comprises 2n circuit units and 2n light-emitting units, the 2n light-emitting units comprise n first-type light-emitting units and n second-type light-emitting units, the emergent light of the first-type light-emitting units is in a bottom emission mode, the emergent light of the second-type light-emitting units is in a top emission mode, and n is a positive integer; the 2n circuit units comprise n first-class circuit units and n second-class circuit units, pixel driving circuits of the first-class circuit units are connected with the first-class light-emitting units, and pixel driving circuits of the second-class circuit units are connected with the second-class light-emitting units. According to the invention, through organic combination of the top emission structure and the bottom emission structure in one repeating unit, double-side transparent display is realized.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices. They offer advantages such as active illumination, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, extremely fast response times, lightweight design, customizable form factors, and flexible displays. They are becoming a highly promising next-generation display technology. Active Matrix (AM) OLEDs are current-driven devices that use independent thin film transistors (TFTs) to control each circuit unit, allowing each unit to emit light continuously and independently.

[0003] With the continuous development of display technology, OLED technology is increasingly being used in transparent displays. Transparent display is an important personalized display field in display technology. It refers to the display of images in a transparent state. The viewer can see not only the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR), augmented reality (AR) and 3D display functions. Currently, OLED transparent display devices are mainly single-sided display. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to achieve double-sided transparent display.

[0006] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to display images on both sides, and the light-transmitting unit being configured to transmit light; in a direction perpendicular to the display substrate, the display substrate comprises at least a driving circuit layer arranged on a base and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base, the driving circuit layer of the display unit comprising 2n circuit units, the light-emitting structure layer of the display unit comprising 2n light-emitting units, the circuit unit comprising at least a pixel driving circuit, the light-emitting unit comprising at least a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, where n is 3 or 4; the 2n light-emitting units comprising n first-type light-emitting units and n second-type light-emitting units, the light-emitting light of the first-type light-emitting units being bottom-emitting, the light-emitting light of the second-type light-emitting units being top-emitting, or the light-emitting light of the first-type light-emitting units being top-emitting. The outgoing light is top-emitting, and the outgoing light of the second type of light-emitting unit is bottom-emitting; the 2n circuit units include n first-type circuit units and n second-type circuit units, the pixel driving circuit in the first-type circuit unit is connected to the light-emitting device in the first type of light-emitting unit, and the pixel driving circuit in the second-type circuit unit is connected to the light-emitting device in the second type of light-emitting unit; the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a first node electrode with a first node potential and a second node electrode with a second node potential, the second pole of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second pole of the second transistor and the second pole of the third transistor are connected to the second node electrode; in at least one circuit unit, the first transistor, the second transistor and the third transistor are arranged in sequence along the first direction, and in at least one repeating unit, the 2n circuit units are arranged in sequence along the second direction, and the first direction and the second direction intersect.

[0007] In an exemplary embodiment, the n first-category light-emitting units include at least a first-category first light-emitting unit that emits a first color light, a first-category second light-emitting unit that emits a second color light, and a first-category third light-emitting unit that emits a third color light; the n second-category light-emitting units include at least a second-category first light-emitting unit that emits a first color light, a second-category second light-emitting unit that emits a second color light, and a second-category third light-emitting unit that emits a third color light; the n first-category circuit units include at least a first-category first circuit unit connected to the first-category first light-emitting unit, a first-category second circuit unit connected to the first-category second light-emitting unit, and a first-category third circuit unit connected to the first-category third light-emitting unit; the n second-category circuit units include at least a second-category first circuit unit connected to the second-category first light-emitting unit, a second-category second circuit unit connected to the second-category second light-emitting unit, and a second-category third circuit unit connected to the second-category third light-emitting unit; in at least one repeating unit, the first-category first circuit unit, the second-category first circuit unit, the first-category second circuit unit, the second-category second circuit unit, the first-category third circuit unit, and the second-category third circuit unit are arranged sequentially along the second direction.

[0008] In an exemplary embodiment, the first light-emitting unit of the first category, the second light-emitting unit of the first category, and the third light-emitting unit of the first category are sequentially arranged along the second direction to form a first light-emitting unit group; the first light-emitting unit of the second category, the second light-emitting unit of the second category, and the third light-emitting unit of the second category are sequentially arranged along the second direction to form a second light-emitting unit group; and the first light-emitting unit group is arranged on one side of the second light-emitting unit group in the first direction.

[0009] In an exemplary embodiment, the n first-category light-emitting units include at least a first-category first light-emitting unit that emits a first color light, a first-category second light-emitting unit that emits a second color light, and a first-category third light-emitting unit that emits a third color light; the n second-category light-emitting units include at least a second-category first light-emitting unit that emits a first color light, a second-category second light-emitting unit that emits a second color light, and a second-category third light-emitting unit that emits a third color light; the n first-category circuit units include at least a first-category first circuit unit connected to the first-category first light-emitting unit, a first-category second circuit unit connected to the first-category second light-emitting unit, and a first-category third circuit unit connected to the first-category third light-emitting unit; the n second-category circuit units include at least a second-category first circuit unit connected to the second-category first light-emitting unit, a second-category second circuit unit connected to the second-category second light-emitting unit, and a second-category third circuit unit connected to the second-category third light-emitting unit; in at least one repeating unit, the first-category first circuit unit, the first-category second circuit unit, the first-category third circuit unit, the second-category first circuit unit, the second-category second circuit unit, and the second-category third circuit unit are arranged sequentially along the second direction.

[0010] In an exemplary embodiment, the first light-emitting unit of the first category, the second light-emitting unit of the first category, and the third light-emitting unit of the first category are sequentially arranged along the second direction to form a third light-emitting unit group; the first light-emitting unit of the second category and the second light-emitting unit of the second category are sequentially arranged along the second direction to form a fourth light-emitting unit group; the third light-emitting unit group is arranged on one side of the fourth light-emitting unit group in the first direction, and the third light-emitting unit of the second category is arranged on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction.

[0011] In an exemplary embodiment, at least one repeating unit further includes a scan signal line, which is in the shape of a straight line or a broken line extending along the first direction, and the first transistor and the third transistor in the 2n circuit units in the repeating unit are connected to the same scan signal line.

[0012] In an exemplary embodiment, at least one repeating unit further includes a first gate line and a third gate line connected to the scanning signal line, the first gate line and the third gate line are in the shape of a straight line or a broken line extending along the second direction, and the third gate line is arranged on one side of the first gate line in the first direction; the first gate line is respectively connected to the gate electrodes of the first transistors of 2n circuit units in the repeating unit, and the third gate line is respectively connected to the gate electrodes of the third transistors of the 2n circuit units in the repeating unit.

[0013] In an exemplary embodiment, at least one repeating unit further includes a first power line, a second power line, a compensation signal line and 2n data signal lines, the first electrodes of the second transistors of the 2n circuit units in the repeating unit are connected to the same first power line, the first electrodes of the third transistors of the 2n circuit units in the repeating unit are connected to the same compensation signal line, and the first electrodes of the first transistors of the 2n circuit units in the repeating unit are respectively connected to the 2n data signal lines.

[0014] In an exemplary embodiment, the first power line, the second power line, the compensation signal line and the data signal line are in the shape of straight lines or broken lines extending along the second direction; in at least one repeating unit, in the first direction, the second power line is arranged on a side of the first gate line away from the third gate line, the 2n data signal lines are arranged between the first gate line and the second power line, the compensation signal line is arranged on a side of the third gate line away from the first gate line, and the first power line is arranged between the first gate line and the third gate line.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, and a structure of the storage capacitor in the first type of circuit unit is different from a structure of the storage capacitor in the second type of circuit unit.

[0016] In an exemplary embodiment, the light emitted by the first type of light-emitting unit is bottom-emitting, the light emitted by the second type of light-emitting unit is top-emitting, the first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit; in the bottom-emitting circuit unit, the storage capacitor includes at least a transparent first plate and a transparent second plate, the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first plate on the substrate, the first plate is connected to the second node electrode, the second plate is connected to the first node electrode, and the first plate and the second plate form a transparent storage capacitor in the bottom-emitting circuit unit.

[0017] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer arranged on a base, a first conductive layer arranged on a side of the first transparent conductive layer away from the base, and a semiconductor layer arranged on a side of the first conductive layer away from the base, the first electrode plate is arranged in the first transparent conductive layer, and the second electrode plate is arranged in the semiconductor layer.

[0018] In an exemplary embodiment, the light emitted by the first type of light-emitting unit is bottom-emitting, the light emitted by the second type of light-emitting unit is top-emitting, the first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit; in at least one of the top-emitting circuit units, the storage capacitor includes at least a third plate, a fourth plate, and a fifth plate, the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate, the third plate and the fifth plate are connected to the second node electrode, the fourth plate is connected to the first node electrode, the third plate and the fourth plate form a first sub-capacitor, the fourth plate and the fifth plate form a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor connected in parallel form the storage capacitor in the top-emitting circuit unit.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer arranged on the substrate, a first conductive layer arranged on a side of the first transparent conductive layer away from the substrate, a semiconductor layer arranged on a side of the first conductive layer away from the substrate, a second conductive layer arranged on a side of the semiconductor layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate, the third electrode plate is arranged in the first conductive layer, the fourth electrode plate is arranged in the semiconductor layer, and the fifth electrode plate is arranged in the third conductive layer.

[0020] In an exemplary embodiment, the light emitted by the first type of light-emitting unit is bottom-emitting, and the light emitted by the second type of light-emitting unit is top-emitting. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from the structure of the second anode.

[0021] In an exemplary embodiment, the first anode includes at least a main body and a connecting part, the main body is provided in the display unit, a first end of the connecting part is connected to the main body, and a second end of the connecting part extends to the light-transmitting unit and is connected to the pixel driving circuit of the first type circuit unit.

[0022] In an exemplary embodiment, the second anode includes at least a first sub-anode, a second sub-anode and a sub-connecting electrode, the first sub-anode and the second sub-anode are arranged in the display unit and isolated from each other, one end of the sub-connecting electrode is respectively connected to the first sub-anode and the second sub-anode, and the other end of the sub-connecting electrode extends to the back of the light-transmitting unit and is connected to the pixel driving circuit of the second-type circuit unit.

[0023] In an exemplary embodiment, the second type of light-emitting unit further includes a third anode, the third anode including at least a first reflective electrode and a second reflective electrode, the first reflective electrode and the second reflective electrode being arranged in the display unit and isolated from each other, the orthographic projection of the first reflective electrode on the substrate at least partially overlapping with the orthographic projection of the first sub-anode on the substrate and overlapping with the first sub-anode, the orthographic projection of the second reflective electrode on the substrate at least partially overlapping with the orthographic projection of the second sub-anode on the substrate and overlapping with the second sub-anode.

[0024] In an exemplary embodiment, the first type of light emitting unit further includes a first cathode, and the second type of light emitting unit further includes a second cathode. The first cathode and the second cathode are isolated from each other. The first cathode is made of a reflective material, and the second cathode is made of a transparent material.

[0025] In an exemplary embodiment, the first type of light emitting unit further includes a third cathode, the third cathode is overlapped with the first cathode, and the second cathode and the third cathode are provided in the same layer and are interconnected as an integral structure.

[0026] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0027] The exemplary embodiments of the present disclosure provide an OLED transparent display device. Through the organic combination of a top-emitting structure and a bottom-emitting structure in a repeating unit, it can not only achieve double-sided transparent display, but also ensure unobstructed interaction between the two light-emitting surfaces, providing technical support for OLED double-sided transparent display.

[0028] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0030] Figure 1 is a structural schematic diagram of a display device;

[0031] Figure 2 This is a schematic diagram of an arrangement of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 3A This is a schematic diagram of an arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0033] Figure 3BA schematic diagram of an arrangement of a circuit unit according to an exemplary embodiment of the present disclosure;

[0034] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit of an exemplary embodiment of the present disclosure;

[0035] Figure 5 This is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 6 This is a schematic diagram of the embodiment of the present disclosure after forming a first transparent conductive layer pattern;

[0037] Figure 7A and Figure 7B A schematic diagram of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0038] Figure 8A and Figure 8B A schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0039] Figure 9A and Figure 9B This is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0040] Figure 10 This is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0041] Figure 11A and Figure 11B This is a schematic diagram of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0042] Figure 12 This is a schematic diagram of the embodiment of the present disclosure after forming patterns of a planar layer and a fourth insulating layer;

[0043] Figure 13A and Figure 13B This is a schematic diagram of the embodiment of the present disclosure after forming a second transparent conductive layer pattern;

[0044] Figure 14A and Figure 14B This is a schematic diagram of a reflective conductive layer pattern formed according to an embodiment of the present disclosure;

[0045] Figure 15 This is a schematic diagram of a cathode pattern formed in an embodiment of the present disclosure;

[0046] Figure 16 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 17 for Figure 16 A schematic diagram of the embodiment after forming a cathode pattern;

[0048] Figure 18A This is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0049] Figure 18B A schematic diagram of another arrangement of circuit units according to an exemplary embodiment of the present disclosure;

[0050] Figure 19 FIG. 4 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.

[0051] Description of the accompanying drawings:

[0052] 11—first electrode plate; 12—second electrode plate; 13—third electrode plate;

[0053] 14—fourth electrode plate; 15—fifth electrode plate; 16—shielding electrode;

[0054] 21—first active layer; 22—second active layer; 23—third active layer;

[0055] 30—scanning signal line; 31—first gate line; 32—second gate electrode;

[0056] 33—third gate line; 34—data connection line; 35—power auxiliary line;

[0057] 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode;

[0058] 50—data connection electrode; 51—eleventh connection electrode; 52—twelfth connection electrode;

[0059] 53—thirteenth connecting electrode; 54—first anode connecting electrode; 61—twenty-first connecting electrode;

[0060] 62—22nd connecting electrode; 63—23rd connecting electrode; 64—second anode connecting electrode;

[0061] 71—first power line; 72—second power line; 73—data signal line;

[0062] 74—compensation signal line; 75—first auxiliary electrode; 76—second auxiliary electrode;

[0063] 77—third auxiliary electrode; 81—first anode; 81-1—main body;

[0064] 81-2—connecting portion; 82—second anode; 82-1—first sub-anode;

[0065] 82-2—second sub-anode; 82-3—sub-connecting electrode; 83—third anode;

[0066] 83-1—first reflective electrode; 83-2—second reflective electrode; 91—first cathode;

[0067] 92—second cathode; 93—third cathode; 94—pixel definition layer;

[0068] 95—organic light-emitting layer; 96—color filter layer; 97—black matrix;

[0069] 98—cover plate; 100—repeating unit; 110—display unit;

[0070] 120—Light-transmitting unit. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0072] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0073] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0074] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0075] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0076] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0077] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0078] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0079] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0080] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0081] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0082] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0083] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one circuit unit Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using the grayscale values ​​and control signals received from the timing controller, where n can be a natural number. For example, the data driver can sample the grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller, where m can be a natural number. For example, the scan driver can be constructed in the form of a shift register and can generate scan signals by sequentially transmitting the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0084] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to display images on both sides, and the light-transmitting unit being configured to transmit light; in a direction perpendicular to the display substrate, the display substrate comprises at least a driving circuit layer arranged on a base and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base, the driving circuit layer of the display unit comprising 2n circuit units, the light-emitting structure layer of the display unit comprising 2n light-emitting units, the circuit unit comprising at least a pixel driving circuit, the light-emitting unit comprising at least a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, where n is 3 or 4; the 2n light-emitting units comprising n first-type light-emitting units and n second-type light-emitting units, the light-emitting light of the first-type light-emitting units being bottom-emitting, the light-emitting light of the second-type light-emitting units being top-emitting, or the light-emitting light of the first-type light-emitting units being top-emitting. The light is top-emitted, and the light emitted by the second type of light-emitting unit is bottom-emitted; the 2n circuit units include n first-type circuit units and n second-type circuit units, the middle pixel driving circuit of the first-type circuit unit is connected to the light-emitting device in the first type of light-emitting unit, and the middle pixel driving circuit of the second-type circuit unit is connected to the light-emitting device in the second type of light-emitting unit; the pixel driving circuit at least includes a first transistor, a second transistor, a third transistor, a first node electrode with a first node potential and a second node electrode with a second node potential, the second electrode of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second electrode of the second transistor and the second electrode of the third transistor are connected to the second node electrode; in at least one circuit unit, the first transistor, the second transistor and the third transistor are arranged in sequence along the first direction, and in at least one repeating unit, the 2n circuit units are arranged in sequence along the second direction, and the first direction and the second direction intersect.

[0085] In an exemplary embodiment, at least one repeating unit further includes a scan signal line, which is in the shape of a straight line or a broken line extending along the first direction, and the first transistor and the third transistor in the 2n circuit units in the repeating unit are connected to the same scan signal line.

[0086] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, and a structure of the storage capacitor in the first type of circuit unit is different from a structure of the storage capacitor in the second type of circuit unit.

[0087] In an exemplary embodiment, the light emitted by the first type of light-emitting unit is bottom-emitting, and the light emitted by the second type of light-emitting unit is top-emitting. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from the structure of the second anode.

[0088] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0089] Figure 2 FIG. 1 is a schematic diagram showing an arrangement of a display substrate according to an exemplary embodiment of the present disclosure. Figure 2 As shown, on a plane parallel to the display substrate, the display substrate may include a plurality of regularly arranged repeating units 100. Repeating units 100 are the basic units that constitute the display substrate. Repeating and continuously arranged along at least one direction form the display substrate, i.e., the display substrate is composed of a plurality of repeating units. In an exemplary embodiment, at least one repeating unit 100 may include a display unit 110 and a light-transmitting unit 120. The display unit 110 is configured for bilateral image display. The light-transmitting unit 120 may be located on at least one side of the display unit 110 and is configured to transmit light. This allows the display substrate composed of a plurality of repeating units 100 to display images on both the front and back surfaces in a transparent state, i.e., bilateral transparent display.

[0090] In an exemplary embodiment, the display substrate may include at least a driving circuit layer disposed on a base, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, in a direction perpendicular to the display substrate. In at least one repeating unit, the driving circuit layer of the display unit may include 2n circuit units, and the light-emitting structure layer of the display unit may include 2n light-emitting units. The circuit units may include at least pixel driving circuits, and the light-emitting units may include at least light-emitting devices. The light-emitting devices are connected to the pixel driving circuits of corresponding circuit units, and the light-emitting devices are configured to emit light of corresponding brightness in response to current output by the pixel driving circuits.

[0091] In an exemplary embodiment, n may be 3, or n may be 4.

[0092] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0093] Figure 3AFIG. 1 is a schematic diagram of an arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Figure 3B This is a schematic diagram of an arrangement of circuit units according to an exemplary embodiment of the present disclosure, illustrating the case where n is 3. On a plane parallel to the display substrate, at least one repeating unit may include a display unit 110 and a light-transmitting unit 120. Display unit 110 may be located on one side of light-transmitting unit 120 in a first direction X. Display unit 110 may include six circuit units and six light-emitting units.

[0094] like Figure 3A As shown, the six light-emitting units in at least one display unit 110 may include three first-type light-emitting units and three second-type light-emitting units. The light emitted by the first-type light-emitting units may be bottom-emitting, and the light emitted by the second-type light-emitting units may be top-emitting. The three first-type light-emitting units may be a first bottom-emitting light-emitting unit P1_B, a second bottom-emitting light-emitting unit P2_B, and a third bottom-emitting light-emitting unit P3_B. The three second-type light-emitting units may be a first top-emitting light-emitting unit P1_T, a second top-emitting light-emitting unit P2_T, and a third top-emitting light-emitting unit P3_T.

[0095] In an exemplary embodiment, in at least one display unit 110, the first bottom-emitting light-emitting unit P1_B, the second bottom-emitting light-emitting unit P2_B, and the third bottom-emitting light-emitting unit P3_B can be arranged in sequence along the second direction Y to form a first light-emitting unit group, the first top-emitting light-emitting unit P1_T, the second top-emitting light-emitting unit P2_T, and the third top-emitting light-emitting unit P3_T can be arranged in sequence along the second direction Y to form a second light-emitting unit group, and the first light-emitting unit group can be arranged on one side of the second light-emitting unit group in the first direction X.

[0096] In an exemplary embodiment, the first bottom-emitting light-emitting cell P1_B and the first top-emitting light-emitting cell P1_T may be red light-emitting cells (R) that emit red light, the second bottom-emitting light-emitting cell P2_B and the second top-emitting light-emitting cell P2_T may be green light-emitting cells (G) that emit green light, and the third bottom-emitting light-emitting cell P3_B and the third top-emitting light-emitting cell P3_T may be blue light-emitting cells (B) that emit blue light. In some possible embodiments, the arrangement of RGB can be adjusted according to actual needs, and this disclosure is not limited thereto.

[0097] In a possible implementation, the first type of light emitting unit may be configured to emit light in a top emission manner, and the second type of light emitting unit may be configured to emit light in a bottom emission manner, which is not limited in the present disclosure.

[0098] like Figure 3BAs shown, the six circuit units in at least one display unit 110 may include three first-type circuit units and three second-type circuit units. The first-type circuit units are connected to the first-type light-emitting units, and the second-type circuit units are connected to the second-type light-emitting units. In exemplary embodiments, the connection between a circuit unit and a light-emitting unit in the present disclosure refers to the connection between the pixel driving circuit in the circuit unit and the light-emitting device in the light-emitting unit. The three first-type circuit units may be a first bottom-emitting circuit unit Q1_B, a second bottom-emitting circuit unit Q2_B, and a third bottom-emitting circuit unit Q3_B, respectively. The three second-type circuit units may be a first top-emitting circuit unit Q1_T, a second top-emitting circuit unit Q2_T, and a third top-emitting circuit unit Q3_T, respectively.

[0099] In an exemplary embodiment, in at least one display unit 110, the first bottom-emitting circuit unit Q1_B, the first top-emitting circuit unit Q1_T, the second bottom-emitting circuit unit Q2_B, the second top-emitting circuit unit Q2_T, the third bottom-emitting circuit unit Q3_B, and the third top-emitting circuit unit Q3_T may be sequentially arranged along the second direction Y, with the six circuit units arranged vertically, and the bottom-emitting circuit units and the top-emitting circuit units being arranged crosswise.

[0100] In an exemplary embodiment, the light transmitting unit 120 may be located on a side of the display unit 110 in an opposite direction to a first direction X, where the first direction X crosses the second direction Y.

[0101] Figure 4 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit of an exemplary embodiment of the present disclosure, illustrating a structure in which a repeating unit includes 6 pixel driving circuits. Figure 4 As shown, at least one repeating unit may include 6 pixel driving circuits, the 6 pixel driving circuits may be arranged vertically, and each pixel driving circuit may have a 3T1C structure.

[0102] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 71, the data signal line 73, and the compensation signal line 74.

[0103] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0104] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0105] In an exemplary embodiment, the first transistor T1 may function as a data writing transistor, a gate electrode of the first transistor T1 is connected to the scan signal line 30 , a first electrode of the first transistor T1 is connected to the data signal line 73 , and a second electrode of the first transistor T1 is connected to the first node N1 .

[0106] In an exemplary embodiment, the second transistor T2 may function as a driving transistor, a gate electrode of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first power line 71 , and a second electrode of the second transistor T2 is connected to the second node N2 .

[0107] In an exemplary embodiment, the third transistor T3 may function as a compensation transistor, a gate electrode of the third transistor T3 is connected to the scan signal line 30 , a first electrode of the third transistor T3 is connected to the compensation signal line 74 , and a second electrode of the third transistor T3 is connected to the second node N2 .

[0108] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0109] In an exemplary embodiment, in the six pixel driving circuits of at least one repeating unit, the gate electrodes of the six first transistors T1 and the gate electrodes of the six third transistors T3 are connected to the same scan signal line 30 .

[0110] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line 72. The light-emitting device EL emits light of a corresponding brightness in response to the current of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0111] In an exemplary embodiment, the signal of the first power line 71 is a continuously provided high-level signal, and the signal of the second power line 72 is a continuously provided low-level signal.

[0112] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0113] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0114] Figure 5 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure in which a repeating unit includes six circuit units. Figure 5As shown, the display substrate may include a plurality of regularly arranged repeating units, at least one repeating unit may include a display unit 110 and a light-transmitting unit 120 located on at least one side of the display unit 110, the display unit 110 is configured to perform double-sided image display, and the light-transmitting unit 120 is configured to transmit light. The display unit 110 may include a first bottom-emitting circuit unit Q1_B, a first top-emitting circuit unit Q1_T, a second bottom-emitting circuit unit Q2_B, a second top-emitting circuit unit Q2_T, a third bottom-emitting circuit unit Q3_B, and a third top-emitting circuit unit Q3_T arranged in a vertical manner. The first top-emitting circuit unit Q1_T may be disposed on one side of the first bottom-emitting circuit unit Q1_B in the second direction Y, the second bottom-emitting circuit unit Q2_B may be disposed on one side of the first top-emitting circuit unit Q1_T in the second direction Y, the second top-emitting circuit unit Q2_T may be disposed on one side of the second bottom-emitting circuit unit Q2_B in the second direction Y, the third bottom-emitting circuit unit Q3_B may be disposed on one side of the second top-emitting circuit unit Q2_T in the second direction Y, and the third top-emitting circuit unit Q3_T may be disposed on one side of the third bottom-emitting circuit unit Q3_B in the second direction Y. At least one circuit unit may include a pixel driving circuit, the pixel driving circuit of the bottom emission circuit unit is connected to the light-emitting device that emits light in a bottom emission manner, and the pixel driving circuit of the top emission circuit unit is connected to the light-emitting device that emits light in a top emission manner, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0115] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit may be connected to the scan signal line 30, the first power line 71, the data signal line 73, and the compensation signal line 74, respectively, and the light-emitting device connected to the pixel driving circuit is connected to the second power line 72. The scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power line 71 is configured to provide a first power signal to the pixel driving circuit, the second power line 72 is configured to provide a second power signal to the light-emitting device, the data signal line 73 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 74 is configured to provide a compensation signal to the pixel driving circuit.

[0116] In an exemplary embodiment, the scan signal line 30 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on a side of the first bottom-emitting circuit unit Q1_B away from the first top-emitting circuit unit Q1_T. The first transistors T1 and the third transistors T3 of the six circuit units in the repeating unit are connected to the same scan signal line 30.

[0117] In an exemplary embodiment, at least one repeating unit may further include a first gate line 31 and a third gate line 33. In the first direction X, the third gate line 33 may be disposed on one side of the first gate line 31 in the first direction X. In the second direction Y, the first gate line 31 and the third gate line 33 may be disposed on one side of the scan signal line 30 in the second direction Y. The first gate line 31 and the third gate line 33 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first ends of the first gate line 31 and the third gate line 33 are connected to the scan signal line 30. The first ends of the first gate line 31 and the third gate line 33 extend along the second direction Y from the first bottom-emitting circuit unit Q1_B to the third top-emitting circuit unit Q3_T. The first gate line 31 is connected to the gate electrodes of the first transistors T1 of the six circuit units, and the third gate line 33 is connected to the gate electrodes of the third transistors T3 of the six circuit units.

[0118] In an exemplary embodiment, at least one repeating unit may include a first power line 71, a second power line 72, a compensation signal line 74 and six data signal lines 73. The shapes of the first power line 71, the second power line 72, the data signal line 73 and the compensation signal line 74 may be straight lines or broken lines with the main parts extending along the second direction Y. The cathodes of the six light-emitting devices in the repeating unit are connected to the same second power line 72, the first electrodes of the second transistors T2 of the six circuit units in the repeating unit are connected to the same first power line 71, the first electrodes of the third transistors T3 of the six circuit units in the repeating unit are connected to the same compensation signal line 74, and the first electrodes of the first transistors T1 of the six circuit units in the repeating unit are respectively connected to the six data signal lines 73.

[0119] In an exemplary embodiment, in at least one repeating unit, in the first direction X, the second power line 72 may be disposed on a side of the first gate line 31 away from the third gate line 33, the compensation signal line 74 may be disposed on a side of the third gate line 33 away from the first gate line 31, six data signal lines 73 may be disposed between the first gate line 31 and the second power line 72, and the first power line 71 may be disposed between the first gate line 31 and the third gate line 33.

[0120] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit may include at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, a first node electrode having a first node potential, and a second node electrode having a second node potential. The first electrode of the first transistor T1 is connected to the data signal line 73, the second electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected to the first node electrode, the first electrode of the second transistor T2 is connected to the first power line 71, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected to the second node electrode, and the first electrode of the third transistor T3 is connected to the compensation signal line 74.

[0121] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit may further include a storage capacitor, and the structure of the storage capacitor in the bottom emission circuit unit is different from that of the storage capacitor in the top emission circuit unit.

[0122] In an exemplary embodiment, in at least one of the first bottom-emitting circuit unit Q1_B, the second bottom-emitting circuit unit Q2_B, and the third bottom-emitting circuit unit Q3_B, the storage capacitor may include at least a transparent first electrode plate 11 and a transparent second electrode plate 12, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate.

[0123] In an exemplary embodiment, the first electrode plate 11 is connected to the second electrode of the second transistor T2 via at least the twelfth connecting electrode 52, and is connected to the second electrode of the third transistor T3 via at least the thirteenth connecting electrode 53. This interconnection among the first electrode plate 11, the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is achieved, forming a second node N2 of the pixel driving circuit. In an exemplary embodiment, the twelfth connecting electrode 52 and the thirteenth connecting electrode 53 can serve as the second node electrode in the bottom emission circuit unit of the present disclosure.

[0124] In an exemplary embodiment, the second electrode 12 is connected to the second electrode of the first transistor T1 on one hand, and is connected to the gate electrode of the second transistor T2 on the other hand via at least the eleventh connecting electrode 51. This interconnects the second electrode 12, the second electrode of the first transistor T1, and the gate electrode of the second transistor T2, thereby forming a first node N1 of the pixel driving circuit. In an exemplary embodiment, the eleventh connecting electrode 51 can serve as the first node electrode in the bottom emission circuit unit of the present disclosure.

[0125] In an exemplary embodiment, the first plate 11 having the second node potential and the second plate 12 having the first node potential constitute a storage capacitor in the bottom emission circuit unit.

[0126] In an exemplary embodiment, in at least one of the first top-emitting circuit unit Q1_T, the second top-emitting circuit unit Q2_T, and the third top-emitting circuit unit Q3_T, the storage capacitor may include at least a third plate 13, a fourth plate 14, and a fifth plate 15, wherein an orthographic projection of the fourth plate 14 on the substrate at least partially overlaps with an orthographic projection of the third plate 13 on the substrate, and an orthographic projection of the fifth plate 15 on the substrate at least partially overlaps with an orthographic projection of the fourth plate 14 on the substrate.

[0127] In an exemplary embodiment, the third plate 13 is connected to the second electrode of the third transistor T3 via at least the twenty-third connecting electrode 63, and is connected to the fifth plate 15 via a via. The fifth plate 15 is connected to the twenty-second connecting electrode 62, which is in turn connected to the second electrode of the second transistor T2. This interconnects the third plate 13, the fifth plate 15, the second electrode of the second transistor T2, and the second electrode of the third transistor T3, forming a second node N2 of the pixel driving circuit. In an exemplary embodiment, the twenty-second connecting electrode 62 and the twenty-third connecting electrode 63 can serve as the second node electrode in the top-emitting circuit unit of the present disclosure.

[0128] In an exemplary embodiment, the fourth electrode 14 is connected to the second electrode of the first transistor T1 on one hand, and is connected to the gate electrode of the second transistor T2 on the other hand via at least the twenty-first connection electrode 61. This interconnects the fourth electrode 14, the second electrode of the first transistor T1, and the gate electrode of the second transistor T2, thereby forming a first node N1 of the pixel driving circuit. In an exemplary embodiment, the twenty-first connection electrode 61 can serve as the first node electrode in the top emission circuit unit of the present disclosure.

[0129] In an exemplary embodiment, the third plate 13 having the second node potential and the fourth plate 14 having the first node potential constitute a first sub-capacitor, the fourth plate 14 having the first node potential and the fifth plate 15 having the second node potential constitute a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor connected in parallel constitute a storage capacitor in the top emission circuit unit.

[0130] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on a side of the first conductive layer away from the substrate, a second conductive layer disposed on a side of the semiconductor layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate. The first electrode 11 may be disposed in the first transparent conductive layer, the third electrode 13 may be disposed in the first conductive layer, the second electrode 12 and the fourth electrode 14 may be disposed in the semiconductor layer, and the fifth electrode 15 may be disposed in the third conductive layer.

[0131] In the exemplary embodiment, since the first electrode 11 is provided in the transparent first transparent conductive layer and the second electrode 12 is provided in the transparent semiconductor layer, the storage capacitor in the bottom emission circuit unit is a transparent storage capacitor.

[0132] In an exemplary embodiment, the scan signal line 30 , the first gate line 31 , and the third gate line 33 may be disposed in the second conductive layer, and the first power line 71 , the second power line 72 , the data signal line 73 , and the compensation signal line 74 may be disposed in the third conductive layer.

[0133] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating an organic material, mask exposure, and development for organic materials. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0134] In an exemplary embodiment, taking an example in which a repeating unit includes six circuit units (a first bottom-emitting circuit unit Q1_B, a first top-emitting circuit unit Q1_T, a second bottom-emitting circuit unit Q2_B, a second top-emitting circuit unit Q2_T, a third bottom-emitting circuit unit Q3_B, and a third top-emitting circuit unit Q3_T), the preparation process of the display substrate of this embodiment may include the following operations.

[0135] (1) Forming a first transparent conductive layer pattern. In an exemplary embodiment, forming the first transparent conductive layer pattern includes: depositing a first transparent conductive film on a substrate, patterning the first transparent conductive film through a patterning process, and forming a first transparent conductive layer pattern on the substrate, such as Figure 6 In an exemplary embodiment, the first transparent conductive layer may be referred to as a 1st ITO (1ITO) layer.

[0136] In an exemplary embodiment, the first transparent conductive layer pattern of each bottom emission circuit unit in the repeating unit may include at least the first plate 11 of the storage capacitor, and each top emission circuit unit is not patterned.

[0137] In an exemplary embodiment, the shape of the first electrode 11 can be a block (such as a rectangle), the corners of the block shape can be chamfered, protruded or grooved, the edge of the block shape can be a broken line, and the first electrode 11 can serve as a transparent lower electrode of the storage capacitor in the bottom emission circuit unit. The first electrode 11 is configured to form a storage capacitor in the bottom emission circuit unit with the subsequently formed second electrode.

[0138] In an exemplary embodiment, the first transparent conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0139] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, such as Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A In an exemplary embodiment, the first conductive layer may be referred to as a light shielding layer (SHL).

[0140] In an exemplary embodiment, the first conductive layer of each bottom emission circuit unit in the repeating unit may include at least the shielding electrode 16 and the first connection electrode 41 .

[0141] In an exemplary embodiment, the shielding electrode 16 may be block-shaped (e.g., rectangular), with chamfers, protrusions, or grooves provided at the corners of the rectangle. The orthographic projection of the shielding electrode 16 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate, and overlaps the first electrode plate 11. The shielding electrode 16 is configured to shield the second transistor T2 in the bottom-emitting circuit unit from light, thereby reducing the intensity of light incident on the second transistor T2 and reducing leakage current of the second transistor T2, thereby alleviating the effect of light on the characteristics of the second transistor T2.

[0142] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip extending along the first direction X, and may be provided across the display unit 110 and the light-transmitting unit 120. The first connection electrode 41 may be provided on one side of the shielding electrode 16 in the first direction X, with a first end of the first connection electrode 41 connected to the shielding electrode 16, and a second end of the first connection electrode 41 extending along the first direction X to the light-transmitting unit 120.

[0143] In an exemplary embodiment, in at least one bottom emission circuit unit, the shielding electrode 16 and the first connection electrode 41 may be an integral structure connected to each other.

[0144] In an exemplary embodiment, a first connection block 41 - 1 and a first compensation connection block 41 - 2 may be disposed on the first connection electrode 41 .

[0145] In an exemplary embodiment, the shape of the first connection block 41-1 can be block-shaped (such as rectangular), and can be arranged at the end of the first connection electrode 41 away from the shielding electrode 16, located in the light-transmitting unit 120, and connected to the first connection electrode 41. The first connection block 41-1 is configured to be connected to the first anode connection electrode formed subsequently.

[0146] In an exemplary embodiment, the shape of the first compensation connection block 41-2 can be block-shaped (such as rectangular), can be arranged between the blocking electrode 16 and the first connection block 41-1, and connected to the first connection electrode 41, and the first compensation connection block 41-2 is configured to be connected to the thirteenth connection electrode formed subsequently.

[0147] In an exemplary embodiment, the first conductive layer of each top emission circuit unit in the repeating unit may include at least the third electrode 13 , the second connection electrode 42 , and the third connection electrode 43 .

[0148] In an exemplary embodiment, the shape of the third electrode plate 13 can be a block shape (such as a rectangle), the corners of the block shape can be provided with chamfers, protrusions or grooves, the edges of the block shape can be a broken line, and the third electrode plate 13 can serve as the lower electrode plate of the storage capacitor in the top emission circuit unit. The third electrode plate 13 is configured to form a first sub-capacitor of the storage capacitor in the top emission circuit unit with the subsequently formed fourth electrode plate.

[0149] In an exemplary embodiment, the third electrode plate 13 is further configured to shield the second transistor T2 in the top emission circuit unit from light, reduce the intensity of light irradiated on the second transistor T2, reduce the leakage current of the second transistor T2, and thus reduce the influence of light on the characteristics of the second transistor T2.

[0150] In an exemplary embodiment, the second connection electrode 42 may be in the shape of a strip extending along the first direction X and may be provided across the display unit 110 and the light-transmitting unit 120. The second connection electrode 42 may be provided on a side of the third electrode plate 13 in the opposite direction of the first direction X, with a first end of the second connection electrode 42 connected to the third electrode plate 13 and a second end of the second connection electrode 42 extending in the opposite direction of the first direction X to the light-transmitting unit 120.

[0151] In an exemplary embodiment, in at least one top emission circuit unit, the third electrode plate 13 and the second connection electrode 42 may be an integral structure connected to each other.

[0152] In an exemplary embodiment, a second connection block 42-1 may be provided on the second connection electrode 42. The second connection block 42-1 may be block-shaped (e.g., rectangular) and may be provided at an end of the second connection electrode 42 away from the third electrode plate 13, located within the light-transmitting unit 120, and connected to the second connection electrode 42. The second connection block 42-1 is configured to be connected to a second anode connection electrode formed subsequently.

[0153] In an exemplary embodiment, the third connection electrode 43 may be in the shape of a strip extending along the first direction X and may be disposed on one side of the third electrode plate 13 in the first direction X. A first end of the third connection electrode 43 is connected to the third electrode plate 13 , and a second end of the third connection electrode 43 extends along the first direction X.

[0154] In an exemplary embodiment, in at least one top emission circuit unit, the third electrode plate 13 and the third connection electrode 43 may be an integral structure connected to each other.

[0155] In an exemplary embodiment, a second compensation connection block 43-1 may be provided on the third connection electrode 43. The second compensation connection block 43-1 may be block-shaped (e.g., rectangular) and may be provided at an end of the third connection electrode 43 away from the third electrode plate 13 and connected to the third connection electrode 43. The second compensation connection block 43-1 is configured to be connected to a subsequently formed twenty-third connection electrode.

[0156] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, such as Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A Schematic diagram of the semiconductor layer.

[0157] In an exemplary embodiment, the semiconductor layer of each bottom emission circuit unit in the repeating unit may include at least a second electrode plate 12 , a first active layer 21 , a second active layer 22 , and a third active layer 23 .

[0158] In an exemplary embodiment, the shape of the second electrode plate 12 can be a block shape (such as a rectangle), and the corners of the block shape can be provided with chamfers, protrusions or grooves. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as a transparent upper electrode plate of the storage capacitor in the bottom emission circuit unit, and the first electrode plate 11 and the second electrode plate 12 form a transparent storage capacitor in the bottom emission circuit unit.

[0159] In an exemplary embodiment, the first active layer 21, the second active layer 22, and the third active layer 23 may have a strip shape extending along the first direction X. The first active layer 21 may serve as the active layer of the first transistor T1, the second active layer 22 may serve as the active layer of the second transistor T2, and the third active layer 23 may serve as the active layer of the third transistor T3. The active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0160] In an exemplary embodiment, the first active layer 21 may be disposed on a side of the second electrode plate 12 in a direction opposite to the first direction X. The first region of the first active layer 21 may be disposed on a side of the channel region of the first active layer 21 away from the second electrode plate 12, and the second region of the first active layer 21 may be disposed on a side of the channel region of the first active layer 21 close to the second electrode plate 12 and connected to the second electrode plate 12.

[0161] In an exemplary embodiment, the second active layer 22 may be disposed on one side of the second electrode plate 12 in the first direction X. The first region of the second active layer 22 may be disposed on a side of the channel region of the second active layer 22 away from the second electrode plate 12 , and the second region of the second active layer 22 may be disposed on a side of the channel region of the second active layer 22 close to the second electrode plate 12 .

[0162] In an exemplary embodiment, the orthographic projections of the channel region and the second region of the second active layer 22 on the substrate are located within the range of the orthographic projection of the shielding electrode 16 on the substrate, so that the shielding electrode 16 can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0163] In an exemplary embodiment, in at least one bottom emission circuit unit, the second electrode plate 12 and the first active layer 21 may be an interconnected integral structure, which not only saves space but also reduces via connection structures and simplifies the manufacturing process.

[0164] In an exemplary embodiment, the third active layer 23 may be disposed on one side of the second active layer 22 in the first direction X. The first region of the third active layer 23 may be disposed on a side of the channel region of the third active layer 23 away from the second active layer 22, and the second region of the third active layer 23 may be disposed on a side of the channel region of the third active layer 23 close to the second active layer 22.

[0165] In an exemplary embodiment, the semiconductor layer of each top emission circuit unit in the repeating unit may include at least a fourth electrode 14 , a first active layer 21 , a second active layer 22 , and a third active layer 23 .

[0166] In an exemplary embodiment, the shape of the fourth plate 14 can be a block shape (such as a rectangle), and the corners of the block shape can be provided with chamfers, protrusions or grooves. The orthographic projection of the fourth plate 14 on the substrate at least partially overlaps with the orthographic projection of the third plate 13 on the substrate. The fourth plate 14 can serve as the intermediate plate of the storage capacitor in the top emission circuit unit. The fourth plate 14 and the third plate 13 form the first sub-capacitor of the storage capacitor in the top emission circuit unit, and the fourth plate 14 and the subsequently formed fifth plate form the second sub-capacitor of the storage capacitor in the top emission circuit unit.

[0167] In an exemplary embodiment, the first active layer 21 may be disposed on a side of the fourth electrode plate 14 in a direction opposite to the first direction X. The first region of the first active layer 21 may be disposed on a side of the channel region of the first active layer 21 away from the fourth electrode plate 14 , and the second region of the first active layer 21 may be disposed on a side of the channel region of the first active layer 21 close to the fourth electrode plate 14 and connected to the fourth electrode plate 14 .

[0168] In an exemplary embodiment, in at least one top-emitting circuit unit, the fourth electrode 14 and the first active layer 21 may be an integrated structure connected to each other, which not only saves space but also reduces the via connection structure and simplifies the manufacturing process.

[0169] In an exemplary embodiment, the second active layer 22 may be disposed on one side of the fourth electrode plate 14 in the first direction X. The first region of the second active layer 22 may be disposed on a side of the channel region of the second active layer 22 away from the fourth electrode plate 14 , and the second region of the second active layer 22 may be disposed on a side of the channel region of the second active layer 22 close to the fourth electrode plate 14 .

[0170] In an exemplary embodiment, the orthographic projections of the channel region and the second region of the second active layer 22 on the substrate are located within the range of the orthographic projection of the third electrode plate 13 on the substrate, so that the third electrode plate 13 serving as a shielding electrode can shield the channel region of the second transistor T2, thereby preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0171] In an exemplary embodiment, the third active layer 23 may be disposed on one side of the second active layer 22 in the first direction X. The first region of the third active layer 23 may be disposed on a side of the channel region of the third active layer 23 away from the second active layer 22, and the second region of the third active layer 23 may be disposed on a side of the channel region of the third active layer 23 close to the second active layer 22.

[0172] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0173] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, and forming the second conductive layer pattern on the second insulating layer, such as Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A In an exemplary embodiment, the second conductive layer may be referred to as a gate metal layer (GATE).

[0174] In an exemplary embodiment, the second conductive layer in the repeating unit may include at least the scan signal line 30 .

[0175] In an exemplary embodiment, the scan signal line 30 may be in the shape of a straight line or a zigzag line extending along a first direction X. In the first direction X, the scan signal line 30 may be continuously arranged in multiple repeating units, i.e., extending from the light-transmitting unit 120 of a repeating unit to the display unit 110 of the repeating unit, and from the display unit 110 of the repeating unit to the light-transmitting unit 120 of an adjacent repeating unit. In the second direction Y, the scan signal line 30 may be arranged on a side of the repeating unit opposite to the second direction Y, i.e., on a side of the first bottom-emitting circuit unit Q1_B away from the first top-emitting circuit unit Q1_T.

[0176] In an exemplary embodiment, in at least one repeating unit, at least a first concave structure 30A and a second concave structure 30B may be provided on the scan signal line 30. The first concave structure 30A and the second concave structure 30B may be in the shape of an inverted "C," with both ends of the "C" shape connected to the scan signal line 30. The scan signal line 30 and the first concave structure 30A form a first ring structure, and the scan signal line 30 and the second concave structure 30B form a second ring structure.

[0177] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the first and second annular structures on the substrate at least partially overlap with the orthographic projections of subsequently formed second power lines, data signal lines, and compensation signal lines on the substrate. The scan signal line structure comprising the first and second annular structures exhibits repairability. If a short circuit occurs in the overlapping region between a scan signal line and the second power line, data signal line, or compensation signal line, laser cutting can be used to sever the scan signal lines 30 on both sides of the short circuit point, thereby repairing the short circuit.

[0178] In an exemplary embodiment, in at least one repeating unit, the scan signal line 30 , the first concave structure 30A, and the second concave structure 30B may be an integral structure connected to each other.

[0179] In an exemplary embodiment, the second conductive layer of each circuit unit in the repeating unit (i.e., each bottom emission circuit unit and each top emission circuit unit, the same below) may include at least a first gate line 31, a second gate electrode 32, a third gate line 33 and a data connection line 34.

[0180] In an exemplary embodiment, the first gate line 31 may be in the shape of a straight line or a zigzag line extending along the second direction Y. A first end of the first gate line 31 is connected to the scan signal line 30, and a second end of the first gate line 31 may extend along the second direction Y from the first bottom-emitting circuit unit Q1_B to the third top-emitting circuit unit Q3_T. The region where the first gate line 31 overlaps with the first active layer in each circuit unit may serve as the gate electrode of the first transistor T1. That is, the first gate line 31 is connected to the gate electrodes of the first transistors T1 in the six circuit units in the repeating unit. Thus, the scan signal line 30 can control the conduction or disconnection of the first transistors T1 in the six circuit units in the repeating unit.

[0181] In an exemplary embodiment, the second gate electrode 32 in each bottom emission circuit unit may be in the shape of a strip extending along the second direction Y, and the region where the second gate electrode 32 overlaps with the second active layer in each bottom emission circuit unit may serve as the gate electrode of the second transistor T2 in the bottom emission circuit unit.

[0182] In an exemplary embodiment, in at least one bottom emission circuit unit, the orthographic projection of the second gate electrode 32 on the substrate may be located within the range of the orthographic projection of the shielding electrode 16 on the substrate.

[0183] In an exemplary embodiment, the second gate electrode 32 in each top emission circuit unit may be shaped like an inverted "L", and the region where the second gate electrode 32 overlaps with the second active layer in each top emission circuit unit may serve as the gate electrode of the second transistor T2 in the top emission circuit unit.

[0184] In an exemplary embodiment, in at least one top emission circuit unit, the orthographic projection of the second gate electrode 32 on the substrate may be located within the range of the orthographic projection of the third electrode plate 13 on the substrate.

[0185] In an exemplary embodiment, the third gate line 33 may be in the shape of a straight line or a zigzag line extending along the second direction Y. A first end of the third gate line 33 is connected to the scan signal line 30, and a second end of the third gate line 33 may extend along the second direction Y from the first bottom-emitting circuit unit Q1_B to the third top-emitting circuit unit Q3_T. The region where the third gate line 33 overlaps with the third active layer in each circuit unit may serve as the gate electrode of the third transistor T3. That is, the third gate line 33 is connected to the gate electrodes of the third transistors T3 in the six circuit units in the repeating unit. Thus, the scan signal line 30 can control the conduction or disconnection of the third transistors T3 in the six circuit units in the repeating unit.

[0186] In an exemplary embodiment, in at least one circuit unit, the second gate electrode 32 may be disposed between the first gate line 31 and the third gate line 33 .

[0187] In an exemplary embodiment, in at least one repeating unit, the scan signal line 30 , the first gate line 31 , and the third gate line 33 may be an integral structure connected to each other.

[0188] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0189] In an exemplary embodiment, in at least one repetition unit, the gate electrodes of the six first transistors T1 and the gate electrodes of the six third transistors T3 are connected to the same scan signal line 30 .

[0190] In an exemplary embodiment, the data connection line 34 may be in the shape of a strip extending along the first direction X, and may be disposed on a side of the first gate line 31 away from the third gate line 33. A first end of the data connection line 34 is configured to be connected to a subsequently formed data signal line, and a second end of the data connection line 34 is configured to be connected to the first region of the first active layer through a subsequently formed data connection electrode.

[0191] In an exemplary embodiment, in at least one repeating unit, the data connection line 34 in the bottom-emitting circuit unit and the data connection line 34 in the top-emitting circuit unit may have different shapes and extension lengths, the data connection lines 34 in the three bottom-emitting circuit units may have different shapes and extension lengths, and the data connection lines 34 in the three top-emitting circuit units may have different shapes and extension lengths to accommodate the data connection lines 34 connecting to different data signal lines, which is not limited in the present disclosure.

[0192] In an exemplary embodiment, the second conductive layer in the repeating unit may further include a power auxiliary line 35 .

[0193] In an exemplary embodiment, the auxiliary power supply line 35 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the data connection line 34 away from the first gate line 31. The auxiliary power supply line 35 is configured to connect to a second power supply line formed subsequently. In an exemplary embodiment, there may be multiple auxiliary power supply lines 35 in a repeating unit, and the multiple auxiliary power supply lines 35 may be spaced apart along the second direction Y.

[0194] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of via holes are provided on the third insulating layer, such as Figure 10 shown.

[0195] In an exemplary embodiment, the plurality of vias of each circuit unit in the repeating unit may include at least a first via V1 , a second via V2 , a third via V3 , a fourth via V4 , a fifth via V5 , and a sixth via V6 .

[0196] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed data connection electrode to the first region of the first active layer through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first region of the second active layer, and the second via hole V2 is configured to connect a subsequently formed first power line to the first region of the second active layer through the via hole.

[0198] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the third active layer on the substrate, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first region of the third active layer, and the third via hole V3 is configured to connect a subsequently formed compensation signal line to the first region of the third active layer through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the second region of the third active layer, and the fourth via hole V4 is configured to connect the subsequently formed thirteenth connecting electrode or the twenty-third connecting electrode to the second region of the third active layer through the via hole.

[0200] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first end of the data link line 34 on the substrate, the third insulating layer in the fifth via hole V5 is etched away to expose the surface of the first end of the data link line 34, and the fifth via hole V5 is configured to connect a subsequently formed data signal line to the first end of the data link line 34 through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second end of the data connection line 34 on the substrate, the third insulating layer in the sixth via hole V6 is etched away to expose the surface of the second end of the data connection line 34, and the sixth via hole V6 is configured to connect the subsequently formed data connection electrode to the second end of the data connection line 34 through the via hole.

[0202] In an exemplary embodiment, the plurality of via holes of each bottom emission circuit unit in the repeating unit may further include an eleventh via hole V11 , a twelfth via hole V12 , a thirteenth via hole V13 , and a fourteenth via hole V14 .

[0203] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projections of the second electrode plate 12 and the second gate electrode 32 on the substrate. The eleventh via hole V11 is a transfer via hole, comprising a shallow half hole and a deep half hole. The third insulating layer in the shallow half hole is etched away, exposing the surface of the second gate electrode 32. The third and second insulating layers in the deep half hole are etched away, exposing the surface of the second electrode plate 12. The eleventh via hole V11 is configured to allow a subsequently formed eleventh connecting electrode to be connected to both the second electrode plate 12 and the second gate electrode 32 through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projections of the shielding electrode 16 and the second region of the second active layer on the substrate. The twelfth via hole V12 is a transfer via hole, comprising a shallow half-hole and a deep half-hole. The third and second insulating layers within the shallow half-hole are etched away, exposing the surface of the second region of the second active layer. The third, second, and first insulating layers within the deep half-hole are etched away, exposing the surface of the shielding electrode 16. The twelfth via hole V12 is configured to allow a subsequently formed twelfth connecting electrode to simultaneously connect to the shielding electrode 16 and the second region of the second active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first connection block 41-1 on the first connection electrode 41 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first connection block 41-1, and the thirteenth via hole V13 is configured to connect the subsequently formed first anode connection electrode to the first connection block 41-1 through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first compensation connection block 41-2 on the first connection electrode 41 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fourteenth via V14 are etched away to expose the surface of the first compensation connection block 41-2, and the fourteenth via V14 is configured to connect the subsequently formed thirteenth connection electrode to the first compensation connection block 41-2 through the via.

[0207] In an exemplary embodiment, the plurality of vias of each top-emitting circuit unit in the repeating unit may further include a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0208] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the third insulating layer and the second insulating layer within the twenty-first via V21 are etched away to expose the surface of the second region of the second active layer, and the twenty-first via V21 is configured to connect the subsequently formed twenty-second connecting electrode to the second region of the second active layer through the via.

[0209] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the third electrode plate 13 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twenty-second via V22 are etched away to expose the surface of the third electrode plate 13, and the twenty-second via V22 is configured to connect the subsequently formed fifth electrode plate to the third electrode plate 13 through the via.

[0210] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 14 on the substrate, the third insulating layer and the second insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the fourth electrode plate 14, and the twenty-third via hole V23 is configured to connect the subsequently formed twenty-first connecting electrode to the fourth electrode plate 14 through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the second gate electrode 32 on the substrate, the third insulating layer in the twenty-fourth via V24 is etched away to expose the surface of the second gate electrode 32, and the twenty-fourth via V24 is configured to connect the subsequently formed twenty-first connecting electrode to the second gate electrode 32 through the via.

[0212] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second compensation connection block 43-1 on the third connection electrode 43 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twenty-fifth via V25 are etched away to expose the surface of the second compensation connection block 43-1, and the twenty-fifth via V25 is configured to connect the subsequently formed twenty-third connection electrode to the second compensation connection block 43-1 through the via.

[0213] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the second connection block 42-1 on the second connection electrode 42 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the twenty-sixth via V26 are etched away to expose the surface of the second connection block 42-1, and the twenty-sixth via V26 is configured to connect the subsequently formed second anode connection electrode to the second connection block 42-1 through the via.

[0214] In an exemplary embodiment, the repeating unit may further include a plurality of 30th vias V30. The orthographic projection of the 30th via V30 on the substrate is within the range of the orthographic projection of the auxiliary power supply line 35 on the substrate. The third insulating layer within the 30th via V30 is etched away, exposing the surface of the auxiliary power supply line 35. The 30th via V30 is configured to connect a subsequently formed second power supply line to the auxiliary power supply line 35 through the via. In an exemplary embodiment, there may be multiple 30th vias V30, and the multiple 30th vias V30 may be arranged sequentially along the second direction Y to increase connection reliability.

[0215] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming the third conductive layer pattern on the third insulating layer, such as Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal layer (SD).

[0216] In an exemplary embodiment, the third conductive layer in the repeating unit may include at least one first power line 71 , one second power line 72 , six data signal lines 73 , and one compensation signal line 74 .

[0217] In an exemplary embodiment, the shapes of the first power line 71, the second power line 72, the data signal line 73 and the compensation signal line 74 can be straight lines or broken lines with the main portion extending along the second direction Y. The second power line 72 can be located on the side of the first gate line 31 away from the third gate line 33, the compensation signal line 74 can be located on the side of the third gate line 33 away from the first gate line 31, the first power line 71 and the six data signal lines 73 can be located between the second power line 72 and the compensation signal line 74, and the six data signal lines 73 can be located between the first gate line 31 and the second power line 72. The first power line 71 can be located between the first gate line 31 and the third gate line 33.

[0218] In an exemplary embodiment, the first power line 71 can be connected to the first region of the second active layer of each circuit unit through the second via V2 of each circuit unit, thereby achieving that one first power line 71 can write the first power signal into the first electrodes of the second transistors T2 of the six circuit units in the repeating unit.

[0219] In an exemplary embodiment, the first power line 71 disposed between the first gate line 31 and the third gate line 33 can effectively shield the first gate line 31 and the third gate line 33 from mutual influence, thereby ensuring the stability of the pixel driving circuit.

[0220] In an exemplary embodiment, the one-to-six structure of the first power line in a repeating unit can effectively save the number of signal lines, reduce the occupied space, have a simple structure, a reasonable layout, fully utilize the layout space, improve space utilization, and help improve resolution and transparency.

[0221] In an exemplary embodiment, the second power line 72 can be arranged on the side of the data connection line 34 away from the first gate line 31, and the positive projection of the second power line 72 on the substrate at least partially overlaps with the positive projection of the multiple power auxiliary lines 35 on the substrate. The second power line 72 can be connected to the multiple power auxiliary lines 35 through multiple thirtieth vias V30. The power auxiliary lines 35 and the second power line 72 form a double-layer routing structure, which not only ensures the reliability of power signal transmission, but also effectively reduces the resistance of the second power line, effectively reduces the voltage drop of the second power signal, and improves the display effect.

[0222] In an exemplary embodiment, the compensation signal line 74 can be set on a side of the third gate line 33 away from the first gate line 31, and the compensation signal line 74 can be connected to the first area of ​​the third active layer of each circuit unit through the third via V3 of each circuit unit, thereby achieving that one compensation signal line 74 can write the compensation signal into the first electrode of the third transistor T3 of the six circuit units in the repeating unit.

[0223] In an exemplary embodiment, the one-to-six structure of compensation signal lines in a repeating unit can effectively save the number of signal lines, reduce the occupied space, have a simple structure, a reasonable layout, fully utilize the layout space, improve space utilization, and help improve resolution and transparency.

[0224] In an exemplary embodiment, the compensation signal line 74 is directly connected to the first region of the third active layer of each circuit unit through a via hole, which can ensure that the RC delay of writing the compensation signal into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0225] In an exemplary embodiment, six data signal lines 73 may be disposed between the first gate line 31 and the second power line 72. The six data signal lines 73 may include a first data signal line 73-1, a second data signal line 73-2, a third data signal line 73-3, a fourth data signal line 73-4, a fifth data signal line 73-5, and a sixth data signal line 73-6 arranged sequentially along the first direction X. The first data signal line 73-1 may be located on one side of the second power line 72 in the first direction X and may be connected to the first end of the data link line 34 in the first bottom-emission circuit unit Q1_B via a fifth via V5. The second data signal line 73-2 may be located on one side of the first data signal line 73-1 in the first direction X and may be connected to the first end of the data link line 34 in the second bottom-emission circuit unit Q2_B via a fifth via V5. The third data signal line 73-3 may be located on one side of the second data signal line 73-2 in the first direction X and may be connected to the first end of the data link line 34 in the second top-emission circuit unit Q2_T via a fifth via V5. The fourth data signal line 73-4 may be located on one side of the third data signal line 73-3 in the first direction X and may be connected to the first end of the data link line 34 in the first top-emission circuit unit Q1_T via a fifth via V5. The fifth data signal line 73-5 may be located on one side of the fourth data signal line 73-4 in the first direction X and may be connected to the first end of the data link line 34 in the third bottom-emission circuit unit Q3_B via a fifth via V5. The sixth data signal line 73-6 may be located on one side of the fifth data signal line 73-5 in the first direction X and may be connected to the first end of the data link line 34 in the third top-emission circuit unit Q3_T via a fifth via V5.

[0226] In an exemplary embodiment, the first power line 71, the second power line 72, the data signal line 73 and the compensation signal line 74 can be straight lines or folded lines with variable widths. Using straight lines or folded lines with variable widths can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0227] In an exemplary embodiment, the third conductive layer of each circuit unit in the repeating unit may include at least the data connection electrode 50 .

[0228] In an exemplary embodiment, the data connection electrode 50 may be in the shape of a strip extending along the second direction Y and may be disposed between the first gate line 31 and the sixth data signal line 73-6. The first end of the data connection electrode 50 is connected to the first region of the first active layer via a first via hole V1, and the second end of the data connection electrode 50 is connected to the second end of the data connection line 34 via a sixth via hole V6. Since the first end of the data connection line 34 is connected to one data signal line 73, one data signal line 73 is used to write a data signal to the first electrode of the first transistor T1 in one circuit unit.

[0229] In an exemplary embodiment, the third conductive layer of each bottom emission circuit unit in the repeating unit may include at least an eleventh connection electrode 51 , a twelfth connection electrode 52 , a thirteenth connection electrode 53 and a first anode connection electrode 54 .

[0230] In an exemplary embodiment, the eleventh connecting electrode 51 may be in a block shape (e.g., a rectangle), and may be connected to both the second electrode plate 12 and the second gate electrode 32 via an eleventh via hole V11. Since the second electrode plate 12 is connected to the second region of the first active layer, the eleventh connecting electrode 51 interconnects the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 12, forming a first node N1 of the pixel driving circuit in the bottom emission circuit unit. The eleventh connecting electrode 51 and the second electrode plate 12 in the bottom emission circuit unit have a first node potential, and the eleventh connecting electrode 51 may serve as the first node electrode in the bottom emission circuit unit of the present disclosure.

[0231] In an exemplary embodiment, the twelfth connection electrode 52 may be in a block shape (eg, rectangular) and may be connected to both the shielding electrode 16 and the second region of the second active layer through the twelfth via hole V12 .

[0232] In an exemplary embodiment, the shape of the thirteenth connection electrode 53 can be a strip shape extending along the second direction Y, the first end of the thirteenth connection electrode 53 can be connected to the second region of the third active layer through the fourth via hole V4, and the second end of the thirteenth connection electrode 53 can be connected to the first compensation connection block 41-2 through the fourteenth via hole V14.

[0233] In an exemplary embodiment, since the first compensation connection block 41-2 is connected to the first connection electrode 41, the first connection electrode 41 is connected to the shielding electrode 16, the shielding electrode 16 is connected to the second region of the second active layer through the twelfth connection electrode 52 on the one hand, and is overlapped with the first electrode plate 11 on the other hand, so that the twelfth connection electrode 52 and the thirteenth connection electrode 53 realize the mutual connection between the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11, forming the second node N2 of the pixel driving circuit in the bottom emission circuit unit, the twelfth connection electrode 52, the thirteenth connection electrode 53 and the first electrode plate 11 in the bottom emission circuit unit have a second node potential, and the twelfth connection electrode 52 and the thirteenth connection electrode 53 can serve as the second node electrode in the bottom emission circuit unit of the present disclosure.

[0234] In an exemplary embodiment, in the bottom emission circuit unit, the first plate 11 located in the first transparent conductive layer and having the second node potential and the second plate 12 located in the semiconductor layer and having the first node potential constitute a transparent storage capacitor in the bottom emission circuit unit.

[0235] In an exemplary embodiment, the first anode connection electrode 54 may be in a block shape (e.g., a rectangular shape) and may be connected to the first connection block 41-1 via a thirteenth via hole V13. Since the first connection block 41-1 is connected to the first connection electrode 41, and the first connection electrode 41 is connected to the first electrode plate 11 via the shielding electrode 16, the first electrode plate 11 has a second node potential, and thus the first anode connection electrode 54 in the bottom emission circuit unit has a second node potential.

[0236] In an exemplary embodiment, the third conductive layer of each top emission circuit unit in the repeating unit may include at least a fifth plate 15 , a twenty-first connection electrode 61 , a twenty-second connection electrode 62 , a twenty-third connection electrode 63 and a second anode connection electrode 64 .

[0237] In an exemplary embodiment, the shape of the fifth electrode plate 15 can be a block shape (such as a rectangle), the corners of the block shape can be provided with chamfers, protrusions or grooves, the edges of the block shape can be a broken line, the orthographic projection of the fifth electrode plate 15 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate, the fifth electrode plate 15 can serve as the upper electrode plate of the storage capacitor in the top emission circuit unit, and the fifth electrode plate 15 and the fourth electrode plate 14 form the second sub-capacitor of the storage capacitor in the top emission circuit unit.

[0238] In an exemplary embodiment, the fifth electrode plate 15 may be connected to the third electrode plate 13 through the twenty-second via hole V22 , so that the third electrode plate 13 and the fifth electrode plate 15 have the same potential.

[0239] In an exemplary embodiment, the twenty-first connection electrode 61 may be in the shape of a strip extending along the second direction Y. The first end of the twenty-first connection electrode 61 may be connected to the fourth electrode plate 14 via a twenty-third via hole V23, and the second end of the twenty-first connection electrode 61 may be connected to the second gate electrode 32 via a twenty-fourth via hole V24. Because the fourth electrode plate 14 is connected to the second region of the first active layer, the twenty-first connection electrode 61 interconnects the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the fourth electrode plate 14, forming a first node N1 of the pixel driving circuit in the top emission circuit unit. The twenty-first connection electrode 61 and the fourth electrode plate 14 in the top emission circuit unit have a first node potential. The twenty-first connection electrode 61 may serve as the first node electrode in the top emission circuit unit of the present disclosure.

[0240] In exemplary embodiments, the shape of the twenty-second connection electrode 62 may be a bar shape extending along the second direction Y, and the twenty-second connection electrode 62 may be connected to the second region of the second active layer through the twenty-first via hole V21 .

[0241] In an exemplary embodiment, in at least one top emission circuit unit, the fifth electrode plate 15 and the twenty-second connection electrode 62 may be an integral structure connected to each other.

[0242] In an exemplary embodiment, the shape of the twenty-third connecting electrode 63 can be a strip shape extending along the second direction Y, the first end of the twenty-third connecting electrode 63 can be connected to the second region of the third active layer through the fourth via hole V4, and the second end of the twenty-third connecting electrode 63 can be connected to the second compensation connection block 43-1 through the twenty-fifth via hole V25.

[0243] In an exemplary embodiment, since the second compensation connection block 43-1 is connected to the third connection electrode 43, the third connection electrode 43 is connected to the third plate 13, the third plate 13 is connected to the fifth plate 15 through a via, the fifth plate 15 is connected to the twenty-second connection electrode 62, and the twenty-second connection electrode 62 is connected to the second region of the second active layer through a via, the twenty-second connection electrode 62 and the twenty-third connection electrode 63 realize the interconnection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the third plate 13, and the fifth plate 15, forming the second node N2 of the pixel driving circuit in the top emission circuit unit. The twenty-second connection electrode 62, the twenty-third connection electrode 63, the third plate 13, and the fifth plate 15 in the top emission circuit unit have a second node potential, and the twenty-second connection electrode 62 and the twenty-third connection electrode 63 can serve as the second node electrode in the top emission circuit unit of the present disclosure.

[0244] In an exemplary embodiment, in the top emission circuit unit, the third plate 13 located in the first conductive layer and having the second node potential and the fourth plate 14 located in the semiconductor layer and having the first node potential constitute a first sub-capacitor of the storage capacitor in the top emission circuit unit, the fourth plate 14 located in the semiconductor layer and having the first node potential and the fifth plate 15 located in the third conductive layer and having the second node potential constitute a second sub-capacitor of the storage capacitor in the top emission circuit unit, and the first sub-capacitor and the second sub-capacitor connected in parallel constitute the storage capacitor of the pixel driving circuit in the top emission circuit unit.

[0245] In an exemplary embodiment, the second anode connection electrode 64 may be in a block shape (e.g., a rectangular shape) and may be connected to the second connection block 42-1 via a twenty-sixth via hole V26. Since the second connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the third electrode plate 13, and the third electrode plate 13 has a second node potential, the second anode connection electrode 64 in the top emission circuit unit has a second node potential.

[0246] In an exemplary embodiment, the first anode connecting electrode 54 and the second anode connecting electrode 64 can be arranged in the light-transmitting unit 120 to change the light-transmitting area into an irregular shape. When the light passes through the irregularly shaped light-transmitting area, the positions at which the diffraction stripes are generated are different and the directions in which the diffraction stripes are generated are different. Therefore, the diffraction stripes generated by the light will not diffuse in one direction, but will diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0247] In an exemplary embodiment, the third conductive layer in the repeating unit may further include at least one first auxiliary electrode 75 and at least one auxiliary connecting bar 75 - 1 .

[0248] In an exemplary embodiment, the first auxiliary electrode 75 may be in a block shape (e.g., a rectangular shape) and may be disposed in the light-transmitting unit 120 near the second power line 72. The first auxiliary electrode 75 is configured to be connected to a second auxiliary electrode formed subsequently. The auxiliary connecting bar 75-1 may be in a bar shape extending along the first direction X and may be disposed between the second power line 72 and the first auxiliary electrode 75. A first end of the auxiliary connecting bar 75-1 is connected to the second power line 72, and a second end of the auxiliary connecting bar 75-1 is connected to the first auxiliary electrode 75.

[0249] In an exemplary embodiment, in at least one repeating unit, the second power line 72 , at least one first auxiliary electrode 75 , and at least one auxiliary connection bar 75 - 1 may be an integral structure connected to each other.

[0250] In an exemplary embodiment, the first auxiliary electrode 75 is provided in the light-transmitting unit 120 to change the light-transmitting area into an irregular shape. When light passes through the irregularly shaped light-transmitting area, the positions at which diffraction stripes are generated are different, and the directions in which diffraction stripes are generated are different. Therefore, the diffraction stripes generated by the light do not diffuse in one direction, but diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0251] (7) Forming a flat layer and a fourth insulating layer pattern. In an exemplary embodiment, forming the flat layer and the fourth insulating layer pattern may include: first coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film through a patterning process, then depositing a fourth insulating film, patterning the fourth insulating film through a patterning process, forming a flat layer covering the third conductive layer and a fourth insulating layer pattern disposed on the flat layer, wherein the flat layer is provided with a flat opening, and the fourth insulating layer is provided with a plurality of via holes, such as Figure 12 shown.

[0252] In an exemplary embodiment, the planar layer covers the display unit 110 on one hand and covers the area of ​​the light-transmitting unit 120 where the scanning signal lines 30 are located on the other hand. A planar opening TV1 provided on the planar layer can be located outside the area of ​​the light-transmitting unit 120 where the scanning signal lines 30 are located. The planar film within the planar opening TV1 is removed, exposing the third conductive layer.

[0253] In an exemplary embodiment, the shape of the flat opening TV can be rectangular, and the corners of the rectangle can be provided with grooves or chamfers, and the first anode connecting electrode 54, the second anode connecting electrode 64 and the first auxiliary electrode 75 in the light-transmitting unit 120 can all be located within the range of the flat opening TV, that is, the flat film above the first anode connecting electrode 54, the second anode connecting electrode 64 and the first auxiliary electrode 75 is removed.

[0254] In an exemplary embodiment, the plurality of via holes of at least one repeating unit may include at least three thirty-first via holes V31 , three thirty-second via holes V32 , and at least one thirty-third via hole V33 .

[0255] In an exemplary embodiment, the thirty-first via hole V31 can be arranged in the light-transmitting unit 120, and the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 54 on the substrate. The fourth insulating layer in the thirty-first via hole V31 is etched away to expose the surface of the first anode connecting electrode 54. The thirty-first via hole V31 is configured to connect the first anode in the subsequently formed bottom emission circuit unit to the first anode connecting electrode 54 through the via hole.

[0256] In an exemplary embodiment, the thirty-second via hole V32 can be arranged in the light-transmitting unit 120, and the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the second anode connecting electrode 64 on the substrate. The fourth insulating layer in the thirty-second via hole V32 is etched away to expose the surface of the second anode connecting electrode 64. The thirty-second via hole V32 is configured to connect the second anode in the subsequently formed top-emitting circuit unit to the second anode connecting electrode 64 through the via hole.

[0257] In an exemplary embodiment, the thirty-third via hole V33 can be arranged in the light-transmitting unit 120, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the first auxiliary electrode 75 on the substrate, the fourth insulating layer in the thirty-third via hole V33 is etched away to expose the surface of the first auxiliary electrode 75, and the thirty-third via hole V33 is configured to connect the subsequently formed second auxiliary electrode to the first auxiliary electrode 75 through the via hole.

[0258] In an exemplary embodiment, orthographic projections of the thirty-first via hole V31 , the thirty-second via hole V32 , and the thirty-third via hole V33 on the substrate may all be located within the range of the orthographic projection of the flat opening TV on the substrate.

[0259] (8) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming the second transparent conductive layer pattern may include: depositing a second transparent conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second transparent conductive film through a patterning process to form a second transparent conductive layer pattern, such as Figure 13A and Figure 13B As shown, Figure 13B for Figure 13A Schematic diagram of the second transparent conductive layer in FIG.

[0260] In an exemplary embodiment, the second transparent conductive layer of the repeating unit may include at least three first anodes 81 , and the first anodes 81 may serve as anodes in the bottom-emission light emitting unit.

[0261] In an exemplary embodiment, at least one first anode 81 may include at least a main portion 81-1 and a connecting portion 81-2. The main portion 81-1 may be in a block shape (e.g., rectangular) and may be disposed on a flat layer of the display unit 110. The connecting portion 81-2 may be in a strip shape extending along the first direction X and may be disposed on one side of the main portion 81-1 in the first direction X. The first end of the connecting portion 81-2 is connected to the main portion 81-1, and the second end of the connecting portion 81-2 extends to the light-transmitting unit 120 and is connected to the first anode connecting electrode 54 through a thirty-first via hole V31. Since the first anode connecting electrode 54 has a second node potential, the first anode 81 is connected to the second node N2 of the pixel driving circuit in the bottom emission circuit unit.

[0262] In an exemplary embodiment, in at least one bottom-emission light emitting unit, the main body portion 81 - 1 and the connection portion 81 - 2 may be an integral structure connected to each other.

[0263] In an exemplary embodiment, the second transparent conductive layer of the repeating unit may further include three second anodes 82 , and the second anode 82 may serve as one anode in the top-emission light emitting unit.

[0264] In an exemplary embodiment, the at least one second anode 82 may include at least a first sub-anode 82-1, a second sub-anode 82-2, and a sub-connecting electrode 82-3. The first sub-anode 82-1 and the second sub-anode 82-2 may be block-shaped (e.g., rectangular) and may be disposed on a flat layer of the display unit 110. The first sub-anode 82-1 and the second sub-anode 82-2 may be disposed sequentially along the second direction Y, and the first sub-anode 82-1 and the second sub-anode 82-2 may be isolated from each other.

[0265] In an exemplary embodiment, the main portion of the sub-connecting electrode 82-3 may be disposed on the fourth insulating layer of the light-transmitting unit 120. The sub-connecting electrode 71-3 may be shaped like an "F," with the end of the first horizontal strip connected to the first sub-anode 82-1, the end of the second horizontal strip connected to the second sub-anode 82-2, and the end of the vertical strip away from the horizontal strip connected to the second anode connecting electrode 64 via the thirty-second via hole V32. Because the second anode connecting electrode 64 has a second node potential, it connects the second anode 82 to the second node N2 of the pixel driving circuit in the top emission circuit unit.

[0266] In an exemplary embodiment, in at least one top-emitting light emitting unit, the first sub-anode 82 - 1 , the second sub-anode 82 - 2 , and the sub-connecting electrode 82 - 3 may be an integral structure connected to each other.

[0267] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the first horizontal strip or the second horizontal strip can be cut off by laser cutting, so that one of the first sub-anode 82-1 and the second sub-anode 82-2 is connected to the second node N2, and the other is floated, thereby repairing the bright spot defect.

[0268] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate does not overlap with the orthographic projection of the main body 81-1 of the first anode 81 on the substrate, and the orthographic projection of the thirty-second via hole V32 on the substrate does not overlap with the orthographic projection of the first sub-anode 82-1 and the second sub-anode 82-2 of the second anode 82 on the substrate. This not only improves the success rate of repairing bright spot defects and avoids the impact of the repair on the pixel driving circuit, but also ensures the flatness of the first anode and the second anode, improves the light output quality of the light-emitting device, and improves the display effect.

[0269] In an exemplary embodiment, the three first anodes 81 in a repeating unit can be arranged in a vertical manner, the first first anode 81 is connected to the pixel driving circuit in the first bottom emission circuit unit Q1_B, the second first anode 81 is connected to the pixel driving circuit in the second bottom emission circuit unit Q2_B, and the third first anode 81 is connected to the pixel driving circuit in the third bottom emission circuit unit Q3_B. The three first anodes 81 can be arranged in sequence along the second direction Y to form a first light-emitting unit group.

[0270] In an exemplary embodiment, the three second anodes 82 in a repeating unit can be arranged vertically, the first second anode 82 is connected to the pixel driving circuit in the first top emission circuit unit Q1_T, the second second anode 82 is connected to the pixel driving circuit in the second top emission circuit unit Q2_T, and the third second anode 82 is connected to the pixel driving circuit in the third top emission circuit unit Q3_T. The three second anodes 82 can be arranged sequentially along the second direction Y to form a second light-emitting unit group.

[0271] In an exemplary embodiment, the three first anodes 81 in a repeating unit can be arranged on one side of the three second anodes 82 in the first direction X, that is, the first light-emitting unit group is arranged on one side of the second light-emitting unit group in the first direction X. In some possible implementations, the arrangement of the first anodes and the second anodes can be adjusted according to actual needs, and this disclosure is not limited thereto.

[0272] In an exemplary embodiment, since the bottom-emission process essentially eliminates the dark spot issue, and to maximize the aperture ratio of the bottom-emission circuit unit, the first anode is a monolithic structure and lacks a repair structure. Since the top-emission process is prone to dark spot defects, the second anode is provided with a repair structure. The second anode is divided into two sub-anodes with separate structures, allowing for dark spot repair to improve product yield. The proposed solution of not providing a repair structure for the bottom-emission light-emitting unit and providing a repair structure for the top-emission light-emitting unit fully considers process capabilities and aperture ratio, and can achieve optimized product yield and maximized aperture ratio.

[0273] In an exemplary embodiment, the second transparent conductive layer of at least one repeating unit may further include at least one second auxiliary electrode 76. The second auxiliary electrode 76 may be in a block shape (e.g., a rectangle), and the orthographic projection of the second auxiliary electrode 76 on the substrate at least partially overlaps with the orthographic projection of the first auxiliary electrode 75 on the substrate. The second auxiliary electrode 76 may be connected to the first auxiliary electrode 75 through a thirty-third via hole V33, and the second auxiliary electrode 76 is configured to be connected to a third auxiliary electrode formed subsequently.

[0274] In an exemplary embodiment, the second transparent conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0275] (9) Forming a reflective conductive layer pattern. In an exemplary embodiment, forming the reflective conductive layer pattern may include: depositing a reflective conductive film on the substrate having the aforementioned pattern formed thereon, patterning the reflective conductive film through a patterning process to form a reflective conductive layer pattern, such as Figure 14A and Figure 14B As shown, Figure 14B for Figure 14A Schematic diagram of the reflective conductive layer.

[0276] In exemplary embodiments, the reflective conductive layer in the repeating unit may include three third anodes 83 .

[0277] In an exemplary embodiment, at least one third anode 83 may include a first reflective electrode 83-1 and a second reflective electrode 83-2 arranged in sequence along the second direction Y. The shapes of the first reflective electrode 83-1 and the second reflective electrode 83-2 may be block-shaped (such as a rectangle). The first reflective electrode 83-1 and the second reflective electrode 83-2 may be arranged in sequence along the second direction Y, and the first reflective electrode 83-1 and the second reflective electrode 83-2 are isolated from each other.

[0278] In an exemplary embodiment, the orthographic projection of the first reflective electrode 83-1 on the substrate at least partially overlaps the orthographic projection of the first sub-anode 82-1 on the substrate, and the first reflective electrode 83-1 directly overlaps the first sub-anode 82-1. The orthographic projection of the second reflective electrode 83-2 on the substrate at least partially overlaps the orthographic projection of the second sub-anode 82-2 on the substrate, and the second reflective electrode 83-2 directly overlaps the second sub-anode 82-2.

[0279] In an exemplary embodiment, the reflective conductive layer of at least one repeating unit may further include a third auxiliary electrode 77. The third auxiliary electrode 77 may be in a block shape (e.g., a rectangle), and the orthographic projection of the third auxiliary electrode 77 on the substrate at least partially overlaps the orthographic projection of the second auxiliary electrode 76 on the substrate, and the third auxiliary electrode 77 directly overlaps the second auxiliary electrode 76.

[0280] In an exemplary embodiment, the stacked first auxiliary electrode 75 , the second auxiliary electrode 76 , and the third auxiliary electrode 77 may constitute an auxiliary cathode.

[0281] In an exemplary embodiment, the third auxiliary electrode 77 is configured to be connected to a subsequently formed cathode, thereby achieving a connection between the second power line 72 and the cathode. Considering the voltage drop (IR drop) problem that exists in large-scale transparent displays, the present disclosure provides a second power line that transmits a second voltage signal in each repeating unit. The second power line is connected to the cathode in the subsequently formed light-emitting structure layer through the auxiliary cathode. This can effectively reduce the voltage drop of the cathode, effectively solve the voltage drop problem that exists in large-scale transparent displays, and ensure display uniformity.

[0282] In an exemplary embodiment, the auxiliary cathode can adopt an isolation column (RIB) structure, and the cross-sectional shape of the auxiliary cathode can be an inverted trapezoid or an "I" shape, so that the subsequently formed organic light-emitting layer can be disconnected at the side edge of the auxiliary cathode to form an isolated and isolated organic light-emitting block, which can effectively avoid the interference of the organic light-emitting block on the outgoing light, improve the quality of the outgoing light, and help improve the display quality.

[0283] (10) Sequentially forming a pixel definition layer, an organic light emitting layer, and a cathode pattern. In an exemplary embodiment, sequentially forming a pixel definition layer, an organic light emitting layer, and a cathode pattern may include:

[0284] First, a pixel definition layer 94 is formed. The pixel definition layer 94 is provided with at least a first pixel opening K1 and a second pixel opening K2. The first pixel opening K1 exposes the surface of the first anode 81, and the second pixel opening K2 exposes the surface of the third anode 83. Then, an organic light-emitting layer 95 is formed on the display unit 110. The organic light-emitting layer 95 is connected to the first anode 81 and the third anode 83 through the first pixel opening K1 and the second pixel opening K2, respectively. Then, a first cathode 91 and a second cathode 92 isolated from each other are formed in sequence through two patterning processes. The first cathode 91 and the second cathode 92 are connected to the organic light-emitting layer, as shown in FIG. Figure 15 shown.

[0285] In an exemplary embodiment, the light emitted by the first type of light emitting unit is bottom-emitting, and the light emitted by the second type of light emitting unit is top-emitting. The first cathode 91 arranged in the first type of light emitting unit can adopt a reflective material to realize bottom-side light emission, and the second cathode 92 arranged in the second type of light emitting unit can adopt a transparent material to realize top-side light emission.

[0286] In an exemplary embodiment, the pixel definition layer 91 may further be provided with a light-transmitting opening, the light-transmitting opening may be provided in the light-transmitting unit 120 , and the cathode formed by the light-transmitting unit 120 may be connected to the third auxiliary electrode.

[0287] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0288] like Figure 15 As shown, when the light emitted by the organic light-emitting layer is white light, the preparation process of the display substrate may further include forming a color filter layer 96 and a black matrix 97. In an exemplary embodiment, the color filter layer 96 of the bottom-emitting light-emitting unit can be disposed between the third conductive layer and the planar layer, forming a CF-On-Array structure. The light emitted by the bottom-emitting light-emitting unit passes through the color filter structure of the CF-On-Array structure to achieve full-color display. The color filter layer 96 of the top-emitting light-emitting unit can be disposed on a cover plate 98, forming a CF-On-Cover Glass structure. The light emitted by the top-emitting light-emitting unit passes through the color filter structure of the CF-On-Cover Glass structure to achieve full-color display.

[0289] In some possible implementations, the position of the color filter layer can be adjusted according to actual needs. For example, the color filter layers of both bottom-emitting and top-emitting light-emitting units can adopt a CF On Array structure. In another example, the color filter layer of the bottom-emitting light-emitting unit can be disposed on the substrate, while the color filter layer of the top-emitting light-emitting unit can be disposed on the cover plate. This disclosure is not limited to this.

[0290] In an exemplary embodiment, the preparation process of the display substrate may further include forming an encapsulation structure layer pattern. The formation of the encapsulation structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first encapsulation layer. Subsequently, an organic material is inkjet printed on the first encapsulation layer using an inkjet printing process, and after curing into a film, a second encapsulation layer is formed. Subsequently, a second inorganic thin film is deposited using an open mask to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second encapsulation layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer. At this point, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed.

[0291] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0292] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0293] The exemplary embodiments of the present disclosure provide an OLED transparent display device. Through the organic combination of a top-emitting structure and a bottom-emitting structure in a repeating unit, it can not only achieve double-sided transparent display, but also ensure unobstructed interaction between the two light-emitting surfaces, providing technical support for OLED double-sided transparent display.

[0294] In the embodiment of the present disclosure, a first transistor, a second transistor, and a third transistor are arranged in sequence along a first direction in a circuit unit, and a plurality of pixel driving circuits are arranged in sequence along a second direction in a repeating unit. This has a simple structure, a reasonable layout, and fully utilizes the layout space. This not only ensures unobstructed interaction between the two light-emitting surfaces, but also improves space utilization, which is beneficial to improving resolution and product yield.

[0295] The disclosed embodiment of the present invention effectively improves the aperture ratio of the bottom-emitting circuit unit by disposing a first electrode in the first transparent conductive layer and a second electrode in the semiconductor layer. The first electrode and the second electrode form a transparent storage capacitor of the bottom-emitting circuit unit. The disclosed embodiment of the present invention effectively improves the aperture ratio of the bottom-emitting circuit unit by disposing a third electrode in the first conductive layer, a fourth electrode in the semiconductor layer, and a fifth electrode in the third conductive layer. The third and fourth electrodes form a first sub-capacitor, the fourth and fifth electrodes form a second sub-capacitor, and the first and second sub-capacitors connected in parallel form the storage capacitor of the top-emitting circuit unit. On the one hand, the capacitance value of the storage capacitor can be effectively increased. On the other hand, the electrode area can be reduced while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area of ​​the pixel driving circuit, which is conducive to achieving high-resolution display.

[0296] The disclosed embodiment, by omitting the bottom-emitting light-emitting unit and providing a repair structure for the top-emitting light-emitting unit, fully considers process capabilities and aperture ratio, achieving optimized product yield and maximized aperture ratio. The top-emitting light-emitting unit provided with a repair structure in the disclosed embodiment not only improves the success rate of repairing defective bright spots, avoids the impact of the repair on the pixel drive circuit, and prevents other defects, resulting in a high repair success rate, but also ensures the flatness of the anode, improving the light output quality of the light-emitting device and enhancing the display effect.

[0297] The exemplary embodiment of the present disclosure provides a ring structure on the scan signal line, so that the scan signal line has a repair capability, and can repair a short circuit defect, which is beneficial to improving product yield.

[0298] The present disclosure exemplarily provides a one-to-six structure for the first power lines and a one-to-six structure for the compensation signal lines, thereby saving the number of signal lines, reducing the occupied space, improving space utilization, and facilitating improved resolution.

[0299] The exemplary embodiment of the present disclosure provides a second power line and an auxiliary cathode, and the second power line is connected to the cathode through the auxiliary cathode, which can effectively reduce the voltage drop of the power signal, ensure display uniformity, and improve display effect.

[0300] The embodiment of the present disclosure arranges the anode connection electrode and the auxiliary electrode in the light-transmitting unit, and uses the anode connection electrode and the auxiliary electrode to change the light-transmitting unit into an irregular shape, thereby effectively reducing the diffraction effect of the light-transmitting unit and effectively improving the transparent display effect.

[0301] The preparation process of the exemplary embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0302] Figure 16 FIG. 1 is a schematic diagram of another structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 16 As shown, this embodiment shows the main structure of the substrate and Figure 5 The illustrated embodiments are essentially the same, except that the second anode is arranged differently.

[0303] In the exemplary embodiment, the present embodiment shows the structure of the bottom emission circuit unit and the top emission circuit unit in the substrate. Figure 5 The embodiment shown is basically the same, the structure of the first anode 81 is the same as Figure 5 The embodiments shown are essentially identical.

[0304] In an exemplary embodiment, the at least one second anode 82 may include a first sub-anode 82-1, a second sub-anode 82-2, and a sub-connecting electrode 82-3. The first sub-anode 82-1 may be in a block shape (e.g., rectangular), and the second sub-anode 82-2 may be in a strip shape extending along the first direction X. In the first direction X, the first sub-anode 82-1 may be disposed on a side of the first anode 81 in the opposite direction of the first direction X, and in the second direction Y, the second sub-anode 82-2 may be disposed on a side of the first anode 81 and the first sub-anode 82-1 in the second direction Y.

[0305] In an exemplary embodiment, this example shows the preparation process of the substrate. Figure 5 The embodiments shown are basically the same, except that, in preparing the cathode pattern, a first cathode 91 of a reflective material is first formed by a patterning process, and then a transparent conductive material is deposited to form a transparent conductive layer on the entire surface, forming a second cathode 92 provided in the second type of light-emitting unit and a third cathode 93 provided in the first type of light-emitting unit. The third cathode 93 overlaps the first cathode 91, and the second cathode 92 and the third cathode 93 are provided in the same layer and are an integrated structure connected to each other, as shown in FIG. Figure 17 shown.

[0306] This embodiment can maximize the aperture ratio through the arrangement of the second anode. By forming a transparent conductive layer on the entire surface, it not only ensures that the top-emitting and bottom-emitting cathodes are shared, but also reduces one patterning process, thereby improving production efficiency and reducing production costs.

[0307] Figure 18A FIG. 1 is a schematic diagram of another arrangement of light-emitting units according to an exemplary embodiment of the present disclosure. Figure 18B FIG. 1 is a schematic diagram of another arrangement of circuit units according to an exemplary embodiment of the present disclosure, illustrating the case where n is 3.

[0308] like Figure 18A As shown, in at least one display unit 110, the first bottom-emitting light-emitting unit P1_B, the second bottom-emitting light-emitting unit P2_B and the third bottom-emitting light-emitting unit P3_B can be arranged in sequence along the second direction Y to form a third light-emitting unit group, the first top-emitting light-emitting unit P1_T and the second top-emitting light-emitting unit P2_T can be arranged in sequence along the second direction Y to form a fourth light-emitting unit group, the third light-emitting unit group can be arranged on one side of the fourth light-emitting unit group in the first direction X, and the third top-emitting light-emitting unit P3_T can be arranged on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction Y.

[0309] like Figure 18BAs shown, in at least one display unit 110, the first bottom-emitting circuit unit Q1_B, the second bottom-emitting circuit unit Q2_B, the third bottom-emitting circuit unit Q3_B, the first top-emitting circuit unit Q1_T, the second top-emitting circuit unit Q2_T, and the third top-emitting circuit unit Q3_T can be arranged in sequence along the second direction Y. The six circuit units are arranged vertically, and the bottom-emitting circuit units and the top-emitting circuit units are arranged separately.

[0310] Figure 19 FIG. 1 is a structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 19 As shown, this embodiment shows the main structure of the substrate and Figure 5 The illustrated embodiments are substantially the same, except that three bottom-emitting circuit units are arranged in one area and three top-emitting circuit units are arranged in another area, ie, the bottom-emitting circuit units and the top-emitting circuit units are arranged separately.

[0311] In an exemplary embodiment, this embodiment shows the structure of the pixel driving circuit in the circuit unit in the substrate. Figure 5 The embodiments shown are basically the same and will not be described in detail here.

[0312] In an exemplary embodiment, the three first anodes 81 in a repeating unit can be arranged in a vertical manner, the first first anode 81 is connected to the pixel driving circuit in the first bottom emission circuit unit Q1_B, the second first anode 81 is connected to the pixel driving circuit in the second bottom emission circuit unit Q2_B, and the third first anode 81 is connected to the pixel driving circuit in the third bottom emission circuit unit Q3_B. The three first anodes 81 can be arranged in sequence along the second direction Y to form a third light-emitting unit group.

[0313] In an exemplary embodiment, the two second anodes 82 in a repeating unit can be arranged vertically, the first second anode 82 is connected to the pixel driving circuit in the first top emission circuit unit Q1_T, and the second second anode 82 is connected to the pixel driving circuit in the second top emission circuit unit Q2_T. The two second anodes 82 can be arranged in sequence along the second direction Y to form a fourth light-emitting unit group.

[0314] In an exemplary embodiment, the three first anodes 81 in one repeating unit may be disposed on one side of the two second anodes 82 in the first direction X, that is, the third light-emitting cell group is disposed on one side of the fourth light-emitting cell group in the first direction X. The third second anode 82 may be disposed on one side of the third and fourth light-emitting cell groups in the second direction Y, and the third second anode 82 is connected to the pixel driving circuit in the third top emission circuit unit Q3_T.

[0315] This embodiment utilizes separate bottom-emitting and top-emitting circuit units, facilitating the layout of the pixel driver circuit and improving process quality. While longer sub-connecting electrodes are required in the transparent unit for bottom-emitting circuitry and aperture ratio considerations, these longer sub-connecting electrodes effectively mitigate diffraction effects and enhance transparent display performance.

[0316] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0317] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0318] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0319] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The invention comprises a plurality of repeating units, at least one of which comprises a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to display images on both sides, and the light-transmitting unit being configured to transmit light; in a direction perpendicular to the display substrate, the display substrate comprises at least a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer of the display unit comprises 2n circuit units, the light-emitting structure layer of the display unit comprises 2n light-emitting units, the circuit unit comprises at least a pixel driving circuit, the light-emitting unit comprises at least a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and n is 3 or 4; the 2n light-emitting units comprise n first-type light-emitting units and n second-type light-emitting units, the light emitted by the first-type light-emitting units is bottom-emitting, and the light emitted by the first-type light-emitting units is bottom-emitting. The light emitted by the second type of light-emitting unit is top-emitting, or the light emitted by the first type of light-emitting unit is top-emitting, and the light emitted by the second type of light-emitting unit is bottom-emitting; the 2n circuit units include n first type circuit units and n second type circuit units, the pixel driving circuit in the first type circuit unit is connected to the light-emitting device in the first type of light-emitting unit, and the pixel driving circuit in the second type circuit unit is connected to the light-emitting device in the second type of light-emitting unit; the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a first node electrode having a first node potential, and a second node electrode having a second node potential, the second electrode of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second electrode of the second transistor and the second electrode of the third transistor are connected to the second node electrode; In at least one circuit unit, the first transistor, the second transistor and the third transistor are arranged sequentially along a first direction, and in at least one repeating unit, the 2n circuit units are arranged sequentially along a second direction, and the first direction and the second direction intersect.

2. The display substrate according to claim 1, wherein: The n first-category light-emitting units at least include a first-category first light-emitting unit that emits a first color light, a first-category second light-emitting unit that emits a second color light, and a first-category third light-emitting unit that emits a third color light; the n second-category light-emitting units at least include a second-category first light-emitting unit that emits a first color light, a second-category second light-emitting unit that emits a second color light, and a second-category third light-emitting unit that emits a third color light; the n first-category circuit units at least include a first-category first circuit unit connected to the first-category first light-emitting unit, a first-category second circuit unit connected to the first-category second light-emitting unit, and a first-category third circuit unit connected to the first-category third light-emitting unit; the n second-category circuit units at least include a second-category first circuit unit connected to the second-category first light-emitting unit, a second-category second circuit unit connected to the second-category second light-emitting unit, and a second-category third circuit unit connected to the second-category third light-emitting unit; in at least one repeating unit, the first-category first circuit unit, the second-category first circuit unit, the first-category second circuit unit, the second-category second circuit unit, the first-category third circuit unit, and the second-category third circuit unit are arranged in sequence along the second direction.

3. The display substrate according to claim 2, wherein: The first light-emitting unit of the first category, the second light-emitting unit of the first category, and the third light-emitting unit of the first category are arranged in sequence along the second direction to form a first light-emitting unit group; the first light-emitting unit of the second category, the second light-emitting unit of the second category, and the third light-emitting unit of the second category are arranged in sequence along the second direction to form a second light-emitting unit group; the first light-emitting unit group is arranged on one side of the second light-emitting unit group in the first direction.

4. The display substrate according to claim 1, wherein The n first-category light-emitting units at least include a first-category first light-emitting unit that emits a first color light, a first-category second light-emitting unit that emits a second color light, and a first-category third light-emitting unit that emits a third color light; the n second-category light-emitting units at least include a second-category first light-emitting unit that emits a first color light, a second-category second light-emitting unit that emits a second color light, and a second-category third light-emitting unit that emits a third color light; the n first-category circuit units at least include a first-category first circuit unit connected to the first-category first light-emitting unit, a first-category second circuit unit connected to the first-category second light-emitting unit, and a first-category third circuit unit connected to the first-category third light-emitting unit; the n second-category circuit units at least include a second-category first circuit unit connected to the second-category first light-emitting unit, a second-category second circuit unit connected to the second-category second light-emitting unit, and a second-category third circuit unit connected to the second-category third light-emitting unit; in at least one repeating unit, the first-category first circuit unit, the first-category second circuit unit, the first-category third circuit unit, the second-category first circuit unit, the second-category second circuit unit, and the second-category third circuit unit are arranged in sequence along the second direction.

5. The display substrate according to claim 4, wherein: The first light-emitting unit of the first category, the second light-emitting unit of the first category and the third light-emitting unit of the first category are arranged in sequence along the second direction to form a third light-emitting unit group; the first light-emitting unit of the second category and the second light-emitting unit of the second category are arranged in sequence along the second direction to form a fourth light-emitting unit group; the third light-emitting unit group is arranged on one side of the fourth light-emitting unit group in the first direction, and the third light-emitting unit of the second category is arranged on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction.

6. The display substrate according to any one of claims 1 to 5, characterized in that: At least one repeating unit further includes a scanning signal line, which is in the shape of a straight line or a broken line extending along the first direction, and the first transistor and the third transistor in the 2n circuit units in the repeating unit are connected to the same scanning signal line.

7. The display substrate according to claim 6, wherein: At least one repeating unit further includes a first gate line and a third gate line connected to the scanning signal line, the first gate line and the third gate line are in the shape of a straight line or a broken line extending along the second direction, and the third gate line is arranged on one side of the first gate line in the first direction; the first gate line is respectively connected to the gate electrodes of the first transistors of 2n circuit units in the repeating unit, and the third gate line is respectively connected to the gate electrodes of the third transistors of the 2n circuit units in the repeating unit.

8. The display substrate according to claim 7, wherein: At least one repeating unit further includes a first power line, a second power line, a compensation signal line and 2n data signal lines, the first electrodes of the second transistors of the 2n circuit units in the repeating unit are connected to the same first power line, the first electrodes of the third transistors of the 2n circuit units in the repeating unit are connected to the same compensation signal line, and the first electrodes of the first transistors of the 2n circuit units in the repeating unit are respectively connected to the 2n data signal lines.

9. The display substrate according to claim 8, wherein: The first power line, the second power line, the compensation signal line and the data signal line are in the shape of straight lines or broken lines extending along the second direction; in at least one repeating unit, in the first direction, the second power line is arranged on the side of the first gate line away from the third gate line, the 2n data signal lines are arranged between the first gate line and the second power line, the compensation signal line is arranged on the side of the third gate line away from the first gate line, and the first power line is arranged between the first gate line and the third gate line.

10. The display substrate according to any one of claims 1 to 5, characterized in that: The pixel driving circuit further includes a storage capacitor, and a structure of the storage capacitor in the first type of circuit unit is different from a structure of the storage capacitor in the second type of circuit unit.

11. The display substrate according to claim 10, wherein: The emitted light of the first type of light-emitting unit is bottom-emitting, the emitted light of the second type of light-emitting unit is top-emitting, the first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit; in the bottom-emitting circuit unit, the storage capacitor includes at least a transparent first electrode and a transparent second electrode, the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate, the first electrode is connected to the second node electrode, the second electrode is connected to the first node electrode, and the first electrode and the second electrode form a transparent storage capacitor in the bottom-emitting circuit unit.

12. The display substrate according to claim 11, wherein: In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer arranged on a base, a first conductive layer arranged on a side of the first transparent conductive layer away from the base, and a semiconductor layer arranged on a side of the first conductive layer away from the base, the first electrode plate is arranged in the first transparent conductive layer, and the second electrode plate is arranged in the semiconductor layer.

13. The display substrate according to claim 10, wherein: The light emitted by the first type of light-emitting unit is bottom-emitting, the light emitted by the second type of light-emitting unit is top-emitting, the first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit; in at least one of the top-emitting circuit units, the storage capacitor includes at least a third plate, a fourth plate, and a fifth plate, the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate, the third plate and the fifth plate are connected to the second node electrode, the fourth plate is connected to the first node electrode, the third plate and the fourth plate form a first sub-capacitor, the fourth plate and the fifth plate form a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor connected in parallel form the storage capacitor in the top-emitting circuit unit.

14. The display substrate according to claim 13, wherein: In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer arranged on the substrate, a first conductive layer arranged on a side of the first transparent conductive layer away from the substrate, a semiconductor layer arranged on a side of the first conductive layer away from the substrate, a second conductive layer arranged on a side of the semiconductor layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate, the third electrode plate is arranged in the first conductive layer, the fourth electrode plate is arranged in the semiconductor layer, and the fifth electrode plate is arranged in the third conductive layer.

15. The display substrate according to any one of claims 1 to 5, characterized in that: The light emitted by the first type of light-emitting unit is bottom-emitting, and the light emitted by the second type of light-emitting unit is top-emitting. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from that of the second anode.

16. The display substrate according to claim 15, wherein: The first anode includes at least a main body and a connecting part, the main body is arranged in the display unit, the first end of the connecting part is connected to the main body, and the second end of the connecting part extends to the light-transmitting unit and is connected to the pixel driving circuit of the first type of circuit unit.

17. The display substrate according to claim 15, wherein: The second anode includes at least a first sub-anode, a second sub-anode and a sub-connecting electrode. The first sub-anode and the second sub-anode are arranged in the display unit and isolated from each other. One end of the sub-connecting electrode is respectively connected to the first sub-anode and the second sub-anode, and the other end of the sub-connecting electrode extends to the back of the light-transmitting unit and is connected to the pixel driving circuit of the second type circuit unit.

18. The display substrate according to claim 17, wherein: The second type of light-emitting unit also includes a third anode, and the third anode includes at least a first reflective electrode and a second reflective electrode. The first reflective electrode and the second reflective electrode are arranged in the display unit and isolated from each other. The orthographic projection of the first reflective electrode on the substrate at least partially overlaps with the orthographic projection of the first sub-anode on the substrate and is overlapped with the first sub-anode. The orthographic projection of the second reflective electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-anode on the substrate and is overlapped with the second sub-anode.

19. The display substrate according to claim 15, wherein The first type of light emitting unit further includes a first cathode, and the second type of light emitting unit further includes a second cathode. The first cathode and the second cathode are isolated from each other. The first cathode is made of a reflective material, and the second cathode is made of a transparent material.

20. The display substrate according to claim 19, wherein The first type of light emitting unit further includes a third cathode, which is overlapped with the first cathode. The second cathode and the third cathode are arranged in the same layer and are an integrated structure connected to each other.

21. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 20.

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