Electronic load current zero calibration circuit

Abstract

The utility model discloses an electronic load current zero calibration circuit which comprises a DAC current calibration circuit, a driving operational amplifier U1, an MOS tube M1, a current sampling circuit, a resistor R2, a resistor R3 and a resistor R4. The DAC current calibration circuit is connected with one end of a resistor R2 through double-channel output, and the other end of the resistor R2 is connected with a second pin of the inverted input end of the driving operational amplifier U1. A fifth pin of the output end of the driving operational amplifier U1 is connected with a grid electrode G of the MOS tube M1; the source electrode S of the MOS tube M1 is connected with the current sampling circuit; two ends of the resistor R4 are respectively connected with the driving operational amplifier U1 and the current sampling circuit; and two ends of the resistor R3 are respectively connected with a second pin of an inverted input end and a fifth pin of an output end of the driving operational amplifier U1. The electronic load current zero calibration circuit disclosed by the utility model can effectively improve the current load pulling slope of a low-voltage large-current electronic load.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic loads for measurement and testing, in particular to an electronic load current zero point calibration circuit. Background Art

[0002] An electronic load is an electronic device that can simulate certain characteristics of a real load. It can not only simulate combinations of resistors of different values, but also simulate certain characteristics of nonlinear loads. Electronic loads have the characteristics of easy adjustment, strong versatility, high precision, and good stability. They are the development direction of loads used in power supply tests.

[0003] With technological advancements, the voltage, current, and power performance of load devices are improving. Some users are also demanding higher load current ramp rates. Low-voltage, high-current applications require rapid high current draw, placing high demands on the components used in power modules. Traditional power unit circuit architectures use constant-current circuits to control the conduction of MOS transistors to control the load current. To achieve a fast current ramp rate, high performance requirements are placed on both the power transistors and the driver amplifiers. In existing products, some architectures use a feedback proportional resistor between the inverting input and output of the driver amplifier to pre-turn on the power transistor. This approach suffers from a loss in control accuracy. The power module has a certain turn-on voltage, and it can only begin to draw current when the DAC reaches a certain set value.

[0004] The current technical difficulties are that with the advancement of electronic technology, the product performance indicators of electronic loads are gradually improving, especially the requirements for power and current accuracy are becoming more stringent. The greater the power of the electronic load, the more power units are required. The op amp offset in each power unit varies, resulting in deviations in the starting point of the power module's current. Due to the physical characteristics of the power unit, the module will not begin to carry current until the DAC output reaches a certain code value. This method will lose the set current accuracy. The existing technology compensates for this loss of accuracy by adding a fixed voltage bias, but this presents certain problems in mass production. Due to module differences, the fixed bias cannot meet the current zero point calibration requirements for each device. To solve this problem, the modules need to be screened for consistency, which is costly. Utility Model Content

[0005] The technical problem to be solved by the present invention is to solve the problem that the existing fixed bias cannot satisfy the current zero point calibration of each device.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] An electronic load current zero point calibration circuit includes: a DAC current calibration circuit, a driving amplifier U1, a MOS tube M1, a current sampling circuit, resistors R2, R3 and R4;

[0008] The DAC current calibration circuit uses a dual-channel output connected to one end of resistor R2, and the other end of resistor R2 is connected to the inverting input pin 2 of the driver op amp U1; the output pin 5 of the driver op amp U1 is connected to the gate G of the MOS transistor M1; the source S of the MOS transistor M1 is connected to the current sampling circuit; the two ends of resistor R4 are connected to the driver op amp U1 and the current sampling circuit respectively; the two ends of resistor R3 are connected to the inverting input pin 2 and the output pin 5 of the driver op amp U1 respectively;

[0009] Among them, the DAC current calibration circuit includes a DAC digital-to-analog converter, and the dual channels of the DAC digital-to-analog converter include a DAC1 channel and a DAC2 channel; the set current value is output through the DAC1 channel; the calibrated current value is output through the DAC2 channel; and the calibrated current value is determined according to the voltage ratio of the resistor R3 to the resistor R2.

[0010] In one embodiment of the present invention, the DAC current calibration circuit includes an adder 10, an operator 20, and an inverter 30 connected in sequence; wherein the DAC1 channel and the DAC2 channel are both connected to the adder 10; and the output end of the inverter 30 is connected to the resistor R2.

[0011] In one embodiment of the present invention, the current sampling circuit includes an operational amplifier U2, a sampling resistor Rsense, and resistors R8, R9, R10, and R11;

[0012] One end of resistor R8 is connected to the non-inverting input pin 1 of the operational amplifier U2, and the other end is connected to the source S of the MOS tube M1; one end of the sampling resistor Rsense is connected to the source S of the MOS tube M1, and the other end is connected to resistor R9, and resistor R9 is connected to the inverting input pin 2 of the operational amplifier U2; one end of resistor R10 is connected to the non-inverting input pin 1 of the operational amplifier U2 and then grounded; the two ends of resistor R11 are respectively connected to the output pin 5 and the inverting input pin 2 of the operational amplifier U2.

[0013] In one embodiment of the present invention, two ends of the resistor R4 are connected to the output terminal pin 5 of the operational amplifier U2 and the inverting input terminal pin 2 of the driving operational amplifier U1 respectively.

[0014] In one embodiment of the present invention, the electronic load current zero point calibration circuit includes a resistor R1 and a capacitor C145; the capacitor C145 is connected in parallel with the resistor R3; one end of the resistor R1 is connected to the non-inverting input pin 1 of the driving operational amplifier U1, and the other end is grounded.

[0015] In one embodiment of the present invention, the electronic load current zero calibration circuit includes resistors R6 and R7; one end of resistor R6 is connected to pin 5 of the output terminal of the driver op amp U1, and the other end is connected to the gate G of the MOS transistor M1; the two ends of resistor R7 are respectively connected to the gate G and source S of the MOS transistor M1.

[0016] In one embodiment of the present invention, the drain D of the MOS transistor M1 is connected to the load.

[0017] Compared with the existing technology, the beneficial effects of the present invention are: by increasing the feedback resistor, the slope of the power unit load current is improved, and the output channel of a DAC digital-to-analog converter is used to replace the fixed resistor bias to achieve zero point adjustment. This method can compensate for the module inconsistency caused by the offset voltage of the power module driving the operational amplifier, plays an important role in mass production, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of a power unit circuit according to an embodiment of the present invention.

[0019] Figure 2 Schematic diagram of a DAC current calibration circuit according to an embodiment of the present invention.

[0020] Figure 3 This is the functional block diagram of the fixed bias circuit for the DAC digital-to-analog converter. DETAILED DESCRIPTION

[0021] In order to facilitate those skilled in the art to understand the technical solution of the present invention, the technical solution of the present invention is further described in conjunction with the accompanying drawings.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0023] See also Figure 1 and Figure 2 As shown, the utility model discloses an electronic load current zero point calibration circuit, which includes a DAC current calibration circuit and a power unit circuit, wherein the output end of the DAC current calibration circuit is connected to the input end of the power unit circuit.

[0024] In one embodiment of the present invention, the power unit circuit includes a driving op amp U1, a MOS transistor M1, a current sampling circuit, resistors R2, R3, R4, R6, and R7, a capacitor C145, and a current sampling circuit including an op amp U2, a sampling resistor Rsense, and resistors R8, R9, R10, and R11.

[0025] In this embodiment, the DAC current calibration circuit uses a dual-channel output connected to one end of resistor R2, the other end of which is connected to the inverting input pin 2 of the driver op amp U1. The output pin 5 of the driver op amp U1 is connected to the gate G of MOS transistor M1, the source S of MOS transistor M1 is connected to the current sampling circuit, the two ends of resistor R4 are connected to the driver op amp U1 and the current sampling circuit, respectively, and the two ends of resistor R3 are connected to the inverting input pin 2 and the output pin 5 of the driver op amp U1, respectively.

[0026] In this embodiment, the two ends of resistor R4 are connected to output pin 5 of op amp U2 and inverting input pin 2 of driver op amp U1, respectively. Capacitor C145 is connected in parallel with resistor R3. One end of resistor R1 is connected to the non-inverting input pin 1 of driver op amp U1, and the other end is grounded. One end of resistor R6 is connected to output pin 5 of driver op amp U1, and the other end is connected to gate G of MOS transistor M1. The two ends of resistor R7 are connected to gate G and source S of MOS transistor M1, respectively. Finally, drain D of MOS transistor M1 is connected to the load.

[0027] In this embodiment, one end of resistor R8 is connected to the non-inverting input pin 1 of op amp U2, and the other end is connected to the source electrode S of MOS transistor M1. One end of sampling resistor Rsense is connected to the source electrode S of MOS transistor M1, and the other end is connected to resistor R9. Resistor R9 is connected to the inverting input pin 2 of op amp U2. One end of resistor R10 is connected to the non-inverting input pin 1 of op amp U2 and then to ground. The two ends of resistor R11 are respectively connected to the output pin 5 and the inverting input pin 2 of op amp U2. In this embodiment, both driver op amp U1 and op amp U2 are commercially available mature products, such as the AD4007.

[0028] In one embodiment of the present invention, I_SET is the output current value from the DAC current calibration circuit, which drives the op amp U1 to generate the VGS voltage to control the opening degree of the MOS tube M1. The current sampling resistor Rsense, the op amp U2 and the resistors R8, R9, R10, and R11 together form a differential current sampling circuit. The sampling result is connected to the inverting input terminal of the op amp U1 through the resistor R4 to form a closed-loop control. The relationship between the current and the set voltage is as follows:

[0029]

[0030] The control method of a single power unit is as follows Figure 1 As shown, each power unit forms a small self-closed loop. When n power units are connected in parallel, the same current setting value can carry n times the current, achieving high current carrying capacity. Due to the addition of resistor R3, the turn-on voltage vgs of the MOS tube M1 is controlled to be equal to I_SET*R3 / R2. It can only work when the turn-on voltage vgs is greater than the threshold voltage vgs(th) of the MOS tube M1. When the current I_SET is small, the MOS tube M1 cannot be turned on, which loses accuracy when setting the DAC. Therefore, a bias voltage needs to be added, as shown in Figure 3 As shown in the figure, when the setting value is 0, the offset voltage Voffset is a fixed offset. Setting the offset voltage Voffset is difficult. If it is set too low, more code values ​​will be lost. If it is set too high, there will be a situation where the current is still drawn even if the setting is 0A.

[0031] To solve the above problems, dual-channel DAC adjustment settings are used, such as Figure 2 As shown. Specifically, the DAC current calibration circuit includes an adder 10, an operator 20, and an inverter 30 connected in sequence. Among them, the DAC1 channel and the DAC2 channel are both connected to the adder 10, and the output end of the inverter 30 is connected to the resistor R2. The DAC2 channel is used to find the zero point, and the DAC1 channel is used for current setting. This method can make the current zero point adjustable, which is suitable for the production of batch modules. In this embodiment, the DAC digital-to-analog converter, the operator 20, and the inverter 30 are all mature products on the market.

[0032] Assuming the turn-on voltage of power MOS tube M1 is 2V, and the ratio of the voltage across resistor R3 to the voltage across resistor R2 is a 10x amplification factor, current drawing begins only when the set value is 0.2V. To reduce DAC code value loss, a 0.2V bias voltage can be used. Specifically, the resistance values ​​of resistors R3 and R2 are fixed. After determining the bias voltage, the current value can be adjusted. However, this method requires high consistency in the power unit circuit. Therefore, an adjustable bias is adopted for the DAC current calibration circuit. During device calibration, the zero point of each device is found and recorded through a program.

[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the foregoing description. It is intended that all variations within the meaning and range of equivalents of the claims be encompassed within the present invention, and any reference numerals in the claims should not be construed as limiting the claims to which they relate.

[0034] The above-mentioned embodiments only represent the implementation methods of the utility model. The protection scope of the utility model is not limited to the above-mentioned embodiments. For those skilled in the art, several modifications and improvements can be made without departing from the concept of the utility model, which all fall within the protection scope of the utility model.

Claims

1. An electronic load current zero point calibration circuit, characterized in that: include: DAC current calibration circuit, driver amplifier U1, MOS tube M1, current sampling circuit, resistors R2, R3 and R4; The DAC current calibration circuit uses a dual-channel output connected to one end of resistor R2, and the other end of resistor R2 is connected to the inverting input pin 2 of the driver op amp U1; the output pin 5 of the driver op amp U1 is connected to the gate G of the MOS transistor M1; the source S of the MOS transistor M1 is connected to the current sampling circuit; the two ends of resistor R4 are connected to the driver op amp U1 and the current sampling circuit respectively; the two ends of resistor R3 are connected to the inverting input pin 2 and the output pin 5 of the driver op amp U1 respectively; Among them, the DAC current calibration circuit includes a DAC digital-to-analog converter, and the dual channels of the DAC digital-to-analog converter include a DAC1 channel and a DAC2 channel; the set current value is output through the DAC1 channel; the calibrated current value is output through the DAC2 channel; and the calibrated current value is determined according to the voltage ratio of the resistor R3 to the resistor R2.

2. The electronic load current zero point calibration circuit according to claim 1, characterized in that: The DAC current calibration circuit comprises an adder (10), an operator (20) and an inverter (30) connected in sequence; wherein the DAC1 channel and the DAC2 channel are both connected to the adder (10); and the output end of the inverter (30) is connected to the resistor R2.

3. The electronic load current zero point calibration circuit according to claim 1, characterized in that: The current sampling circuit includes an op amp U2, a sampling resistor Rsense, and resistors R8, R9, R10, and R11; One end of resistor R8 is connected to the non-inverting input pin 1 of the operational amplifier U2, and the other end is connected to the source S of the MOS tube M1; one end of the sampling resistor Rsense is connected to the source S of the MOS tube M1, and the other end is connected to resistor R9, and resistor R9 is connected to the inverting input pin 2 of the operational amplifier U2; one end of resistor R10 is connected to the non-inverting input pin 1 of the operational amplifier U2 and then grounded; the two ends of resistor R11 are respectively connected to the output pin 5 and the inverting input pin 2 of the operational amplifier U2.

4. The electronic load current zero point calibration circuit according to claim 3, characterized in that: The two ends of the resistor R4 are respectively connected to the output terminal pin 5 of the operational amplifier U2 and the inverting input terminal pin 2 of the driving operational amplifier U1.

5. The electronic load current zero point calibration circuit according to claim 1, characterized in that: The electronic load current zero point calibration circuit includes a resistor R1 and a capacitor C145; the capacitor C145 is connected in parallel with the resistor R3; one end of the resistor R1 is connected to the non-inverting input pin 1 of the driving operational amplifier U1, and the other end is grounded.

6. The electronic load current zero point calibration circuit according to claim 1, characterized in that: The electronic load current zero point calibration circuit includes resistors R6 and R7; one end of resistor R6 is connected to pin 5 of the output terminal of the driving operational amplifier U1, and the other end is connected to the gate G of the MOS tube M1; the two ends of resistor R7 are respectively connected to the gate G and source S of the MOS tube M1.

7. The electronic load current zero point calibration circuit according to claim 6, characterized in that: The drain D of the MOS tube M1 is connected to the load.

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