Clock management circuit and device

Abstract

The utility model discloses a clock management circuit and a clock management device. The clock management circuit comprises a clock signal generation module, a control module and a filtering module, the first end of the filtering module is connected with the first end of the clock signal generation module, and the second end of the filtering module is connected with the first end of the control module; the clock signal generation module is used for providing a reference clock signal for the control module; the second end of the control module is connected with a PPS signal, the control module and the filtering module calibrate the clock signal generation module, and the clock signal generation module outputs a local clock signal after calibration. According to the technical scheme provided by the embodiment of the utility model, an accessed PPS signal is taken as a reference signal, the control module is used for carrying out phase compensation calibration on a reference clock signal and outputting a voltage signal, and the filtering module is used for controlling the voltage of the accessed clock signal so as to adjust the frequency of the clock signal generation module; therefore, the clock signal generation module outputs a precise local clock signal, and the precision and efficiency of clock calibration are improved.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and in particular to a clock management circuit and device. Background Art

[0002] In traditional technology applications, the time accuracy of instruments relies entirely on the characteristics of the clock source itself. Over time, the clock source drifts more and more rapidly. Currently, manual voltage adjustment is commonly used to calibrate the clock source, but this adjustment has low accuracy and is difficult to overcome the problem of long-term aging drift, requiring frequent adjustments. Utility Model Content

[0003] The utility model provides a clock management circuit and device to improve the accuracy and efficiency of clock regulation.

[0004] According to one aspect of the present utility model, a clock management circuit is provided, comprising: a clock signal generating module, a control module and a filtering module;

[0005] The first end of the filtering module is connected to the first end of the clock signal generating module, and the second end of the filtering module is connected to the first end of the control module;

[0006] The clock signal generating module is used to provide a reference clock signal for the control module; the second end of the control module is connected to the PPS signal, the control module and the filtering module calibrate the clock signal generating module, and the clock signal generating module outputs a local clock signal after calibration.

[0007] Optionally, the control module includes a processing unit and a digital-to-analog conversion unit, and the processing unit is connected to the filtering module via the digital-to-analog conversion unit;

[0008] The processing unit includes a PPS signal receiving end, a reference clock signal receiving end and a processing signal output end, the processing signal output end is connected to the first end of the digital-to-analog conversion unit, and the second end of the digital-to-analog conversion unit is connected to the filtering module.

[0009] Optionally, the filtering module includes a first capacitor and a first resistor;

[0010] One end of the first resistor is connected to the first end of the clock signal generating module and one end of the first capacitor respectively, the other end of the first resistor is connected to the digital-to-analog conversion unit, and the other end of the first capacitor is grounded.

[0011] Optionally, it further includes a first signal holding module;

[0012] The first signal holding module includes a first signal holding unit, a second capacitor, a third capacitor, a second resistor, a third resistor and a fourth resistor; the first end of the first capacitor is connected to the second end of the clock signal generating module, the second end of the second capacitor is connected to the first end of the first signal holding unit, and the second end of the first signal holding unit is connected to the fourth resistor; the first end of the second resistor is connected to the second end of the second capacitor, the second end of the second resistor is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded; the first end of the third resistor is connected to the second end of the second capacitor, and the second end of the third resistor is grounded.

[0013] Optionally, a second signal holding module is also included, which includes a second signal holding unit, a fourth capacitor and a fifth resistor; the first end of the second signal holding unit is connected to the third end of the control module; the first end of the fourth capacitor is connected to the second end of the second signal holding module, and the second end of the fourth capacitor is grounded; the first end of the fifth resistor is connected to the first end of the second signal holding unit, and the second end of the fifth resistor is grounded.

[0014] Optionally, a voltage stabilizing module is further included, the input end of the voltage stabilizing module is connected to the power supply, and the output end of the voltage stabilizing module is respectively connected to the clock signal generating module, the control module, the first signal holding module and the second signal holding module.

[0015] Optionally, the voltage stabilizing module further includes a fifth capacitor and a sixth capacitor, one end of the fifth capacitor is connected to the input end of the voltage stabilizing module, and the other end of the fifth capacitor is grounded, one end of the sixth capacitor is connected to the output end of the voltage stabilizing module, and the other end of the sixth capacitor is grounded.

[0016] Optionally, the control module includes an MCU chip.

[0017] Optionally, the voltage stabilization module includes an LDO chip.

[0018] According to another aspect of the present invention, a clock management device is provided, comprising the clock management circuit described in any one of the first aspects.

[0019] The technical solution provided by the embodiment of the present utility model uses the external PPS signal connected as a reference, performs phase compensation calibration on the reference clock signal provided by the clock signal generation module through the control module and outputs a voltage signal, and controls the voltage size connected to the clock signal generation module through the filtering module to adjust the frequency of the clock signal generation module, so that the clock signal generation module outputs a precise local clock signal, thereby improving the accuracy and efficiency of clock calibration.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic structural diagram of a clock management circuit provided by an embodiment of the present utility model;

[0023] Figure 2 A schematic structural diagram of another clock management circuit provided by an embodiment of the present utility model;

[0024] Figure 3 This is a structural diagram of another clock management circuit provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0025] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Figure 1This is a schematic diagram of the structure of a clock management circuit provided by an embodiment of the present utility model. Figure 1 As shown, the clock management circuit includes: a clock signal generating module 100, a control module 200 and a filtering module 300; the first end of the filtering module 300 is connected to the first end of the clock signal generating module 100, and the second end of the filtering module 300 is connected to the first end of the control module 200; the clock signal generating module 100 is used to provide a reference clock signal for the control module 200; the second end of the control module 200 is connected to the PPS signal, the control module 200 and the filtering module 300 calibrate the clock signal generating module 300, and the clock signal generating module 100 outputs a local clock signal after calibration.

[0028] Specifically, the clock signal generating module 100 can be an RTC chip (Real Time Clock). The RTC chip can provide a pulse signal to the control module 200 as a reference clock signal that needs to be calibrated. The control module 200 can be an MCU chip (Micro Controller Unit) with phase compensation technology. The PPS signal (Pulse Per Second) is a time synchronization signal generated by a high-precision clock device, which is used to provide an accurate time mark so that different systems or devices can operate or record data at the same time point, thereby ensuring the consistency and accuracy of data in different systems or devices. The control module 200 outputs a voltage signal after phase synchronization of the reference clock signal based on the input PPS signal as a reference signal, and controls the voltage of the RTC chip through the filter module 300 to make the pulse frequency of the RTC chip equal to the pulse frequency of the PPS signal, so that the clock signal generating module 100 can output an accurate local clock signal.

[0029] The technical solution provided by the embodiment of the present utility model uses the accessed PPS signal as the reference signal, performs phase compensation calibration on the reference clock signal provided by the clock signal generation module through the control module and outputs a voltage signal, and controls the magnitude of the voltage signal through the filtering module to adjust the frequency of the clock signal generation module, so that the clock signal generation module outputs a precise local clock signal, thereby improving the accuracy and efficiency of clock calibration.

[0030] Optionally, Figure 2 This is a schematic diagram of the structure of another clock management circuit provided by the embodiment of the present utility model. Figure 1 and Figure 2The control module 200 includes a processing unit 210 and a digital-to-analog conversion unit 220. The processing unit 210 is connected to the filtering module 300 via the digital-to-analog conversion unit 220. The processing unit 210 includes a PPS signal receiving terminal A1, a reference clock signal receiving terminal A2, and a processed signal output terminal B. The processed signal output terminal B is connected to a first terminal of the digital-to-analog conversion unit 220, and a second terminal of the digital-to-analog conversion unit 220 is connected to the filtering module 300.

[0031] Specifically, the processing unit 210 may be the portion of the control module 200 that performs phase compensation. The PPS signal receiving terminal A1 and the reference clock signal receiving terminal A2 of the processing unit 210 receive the PPS signal and the reference clock signal, respectively. The processing unit 210 performs a synchronization algorithm on the received PPS signal and the reference clock signal, thereby calculating the difference between the PPS signal and the reference clock signal. The digital-to-analog conversion unit 220 converts the processing result of the processing unit 210 into a voltage signal and transmits it to the clock signal generation module 100 via the filtering module 300, thereby achieving frequency calibration for the clock signal generation module 100.

[0032] Optionally, Figure 3 This is a schematic diagram of the structure of another clock management circuit provided by the embodiment of the present utility model. Figure 2 and Figure 3 The filtering module 300 includes a first capacitor C1 and a first resistor R1; one end of the first resistor R1 is connected to the first end of the clock signal generating module 100 and one end of the first capacitor C1 respectively, the other end of the first resistor R1 is connected to the digital-to-analog conversion unit 220, and the other end of the first capacitor C1 is grounded.

[0033] Specifically, port 1 of the clock signal generation module 100 can receive the voltage signal output by the control module 200 after phase compensation. After calibration, the clock signal generation module 100 outputs the local clock signal through port 2. Port 3 of the clock signal generation module 100 is a power interface, which is powered by a DC voltage signal. The voltage signal output by the digital-to-analog conversion unit 220 passes through the first resistor R1 and is filtered and adjusted by the first capacitor C1, thereby changing the magnitude of the voltage signal input to port 1 of the clock signal generation module 100. The digital-to-analog conversion unit 220 and the filtering module 300 can form a voltage control processing circuit. By adjusting the voltage input to the clock signal generation module 100, the pulse frequency of the clock signal generation module 100 is synchronized with the frequency of the PPS signal, thereby achieving calibration of the clock signal generation module 100.

[0034] Optionally, based on the above embodiment, see Figure 3The clock management circuit also includes a first signal holding module 400; the first signal holding module 400 includes a first signal holding unit 410, a second capacitor C2, a third capacitor C3, a second resistor R2, a third resistor R3 and a fourth resistor R4; a first end of the second capacitor C2 is connected to the second end of the clock signal generating module 100, a second end of the second capacitor C2 is connected to the first end of the first signal holding unit 410, and a second end of the first signal holding unit 410 is connected to the fourth resistor R4; a first end of the second resistor R2 is connected to the second end of the second capacitor C2, a second end of the second resistor R2 is connected to the first end of the third capacitor C3, and a second end of the third capacitor C3 is grounded; a first end of the third resistor R3 is connected to the second end of the second capacitor C2, and a second end of the third resistor R3 is grounded.

[0035] Specifically, the first signal holding unit 410 can be an interface chip with a signal holding function. The local clock signal output by the clock signal generating module 100 after calibration can be further improved to a certain order of magnitude in terms of time accuracy and frequency accuracy through the first signal holding unit 410. Port 1 of the first signal holding unit 410 receives the local clock signal output by the clock signal generating module 100 after calibration. Port 2 of the first signal holding unit 410 can be connected to other devices externally, thereby providing other devices with a local clock signal with a certain order of magnitude of frequency accuracy and time accuracy, thereby improving the scalability of the clock management circuit. Port 3 of the first signal holding unit 410 can be a power supply interface, which supplies power to the first signal holding unit 410 by connecting a DC voltage signal. The third capacitor C3 can be used to maintain the voltage stability connected to the first signal holding unit 410, thereby reducing voltage fluctuations and reducing the overall power consumption of the circuit.

[0036] Optionally, based on the above embodiment, see Figure 3 The clock management circuit further includes a second signal holding module 500, which includes a second signal holding unit 510, a fourth capacitor C4, and a fifth resistor R5; a first end of the second signal holding unit 510 is connected to the third end of the control module 200; a first end of the fourth capacitor C4 is connected to the second end of the second signal holding module 510, and a second end of the fourth capacitor is grounded; a first end of the fifth resistor R5 is connected to the first end of the second signal holding unit 510, and a second end of the fifth resistor is grounded.

[0037] Specifically, the second signal holding unit 510 can be an interface chip that also has a signal holding function. The control module 200 can convert the external PPS signal into a local PPS signal suitable for the local device. The local PPS signal output by port 3 of the control module 200 passes through the second signal holding unit 510, which can improve the time accuracy and frequency precision of the local PPS signal by a certain order of magnitude. Port 1 of the second signal holding unit 510 receives the local PPS signal output by the control module 200. Port 3 of the second signal holding unit 510 can be connected to other devices, thereby providing them with a local PPS signal with a certain level of frequency accuracy and time precision, further improving the scalability of the clock management circuit. Port 2 of the second signal holding unit 510 can be a power interface, which supplies power to the second signal holding unit 510 by receiving a DC voltage signal. The fourth capacitor C4 can be used to maintain the voltage stability of the second signal holding unit 510, further reducing voltage fluctuations and reducing the overall power consumption of the circuit.

[0038] Optionally, a voltage stabilizing module 600 is further included, the input end of the voltage stabilizing module 600 is connected to the power supply VCC, and the output end of the voltage stabilizing module 600 is respectively connected to the clock signal generating module 100, the control module 200, the first signal holding module 400 and the second signal holding module 500.

[0039] Specifically, the voltage stabilizing module 600 may be an LDO chip (Low Dropout Regulator). Port 1 of the voltage stabilizing module 600 is connected to the power supply VCC, and port 2 of the voltage stabilizing module 600 is connected to port 3 of the clock signal generating module 100, port 4 of the control module 200, port 3 of the first signal holding unit 410, and port 3 of the second signal holding unit 510, respectively. The voltage stabilizing module 600 can reduce the higher input voltage of the power supply VCC to a stable lower output voltage, while also providing power to the clock signal generating module 100, the control module 200, the first signal holding module 400, and the second signal holding module 500.

[0040] Optionally, the voltage stabilizing module 600 also includes a fifth capacitor C5 and a sixth capacitor C6, one end of the fifth capacitor C5 is connected to the input end of the voltage stabilizing module 600, and the other end of the fifth capacitor C5 is grounded, one end of the sixth capacitor C6 is connected to the output end of the voltage stabilizing module 600, and the other end of the sixth capacitor C6 is grounded.

[0041] Specifically, the fifth capacitor C5 and the sixth capacitor C6 can be filter capacitors. One end of the fifth capacitor C5 is connected to port 1 of the voltage stabilizing module 600, and the other end is grounded, thereby reducing the voltage fluctuation input to the voltage stabilizing module 600 and providing a stable power supply voltage for the voltage stabilizing module 600. One end of the sixth capacitor C6 is connected to the output end of the voltage stabilizing module 600, and the other end is grounded. The sixth capacitor C6 can further reduce the voltage fluctuation output by the voltage stabilizing module 600, thereby providing a more stable DC voltage for the clock signal generating module 100, the control module 200, the first signal holding module 400, and the second signal holding module 500, thereby reducing the additional power consumption of the clock management circuit caused by voltage fluctuations.

[0042] An embodiment of the present invention further provides a clock management device, which includes the clock management circuit provided by any of the above embodiments and has the same beneficial effects as the clock management circuit provided by any of the above embodiments, which will not be described in detail here.

[0043] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this utility model can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this utility model can be achieved. This is not limited herein.

[0044] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A clock management circuit, characterized in that: include: Clock signal generation module, control module and filtering module; The first end of the filtering module is connected to the first end of the clock signal generating module, and the second end of the filtering module is connected to the first end of the control module; The clock signal generating module is used to provide a reference clock signal for the control module; the second end of the control module is connected to the PPS signal, the control module and the filtering module calibrate the clock signal generating module, and the clock signal generating module outputs a local clock signal after calibration.

2. The clock management circuit according to claim 1, wherein: The control module includes a processing unit and a digital-to-analog conversion unit, and the processing unit is connected to the filtering module via the digital-to-analog conversion unit; The processing unit includes a PPS signal receiving end, a reference clock signal receiving end and a processing signal output end, the processing signal output end is connected to the first end of the digital-to-analog conversion unit, and the second end of the digital-to-analog conversion unit is connected to the filtering module.

3. The clock management circuit according to claim 2, wherein: The filtering module includes a first capacitor and a first resistor; One end of the first resistor is connected to the first end of the clock signal generating module and one end of the first capacitor respectively, the other end of the first resistor is connected to the digital-to-analog conversion unit, and the other end of the first capacitor is grounded.

4. The clock management circuit according to claim 1, wherein: Also included is a first signal holding module; The first signal holding module includes a first signal holding unit, a second capacitor, a third capacitor, a second resistor, a third resistor and a fourth resistor; the first end of the second capacitor is connected to the second end of the clock signal generating module, the second end of the second capacitor is connected to the first end of the first signal holding unit, and the second end of the first signal holding unit is connected to the fourth resistor; the first end of the second resistor is connected to the second end of the second capacitor, the second end of the second resistor is connected to the first end of the third capacitor, and the second end of the third capacitor is grounded; the first end of the third resistor is connected to the second end of the second capacitor, and the second end of the third resistor is grounded.

5. The clock management circuit according to claim 4, characterized in that: It also includes a second signal holding module, which includes a second signal holding unit, a fourth capacitor and a fifth resistor; the first end of the second signal holding unit is connected to the third end of the control module; the first end of the fourth capacitor is connected to the second end of the second signal holding module, and the second end of the fourth capacitor is grounded; the first end of the fifth resistor is connected to the first end of the second signal holding unit, and the second end of the fifth resistor is grounded.

6. The clock management circuit according to claim 5, characterized in that: It also includes a voltage stabilizing module, the input end of the voltage stabilizing module is connected to the power supply, and the output end of the voltage stabilizing module is respectively connected to the clock signal generating module, the control module, the first signal holding module and the second signal holding module.

7. The clock management circuit according to claim 6, wherein: The voltage stabilizing module also includes a fifth capacitor and a sixth capacitor, one end of the fifth capacitor is connected to the input end of the voltage stabilizing module, and the other end of the fifth capacitor is grounded, one end of the sixth capacitor is connected to the output end of the voltage stabilizing module, and the other end of the sixth capacitor is grounded.

8. The clock management circuit according to claim 1, wherein: The control module includes an MCU chip.

9. The clock management circuit according to claim 6, wherein: The voltage stabilizing module includes an LDO chip.

10. A clock management device, characterized in that: The clock management circuit comprises the clock management circuit according to any one of claims 1 to 9.

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