Automatic testing and burning device

Abstract

The utility model relates to an automatic testing and burning device which is used for chip burning and testing. The device integrates an MCU, a level conversion circuit, a switching circuit, a chip socket, a power supply circuit, a starting circuit, a reset circuit and a display module. According to the device, through simplified level conversion and voltage regulation circuit design, the accuracy of chip signal control logic is improved, the cost is reduced, and the complexity and the cost of circuit design are reduced. Abnormal conditions are fed back in time through the display module, and the error probability in the burning process is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of chip burning, in particular to an automatic testing burning device. Background Art

[0002] Programming is the process of writing programs or data into a chip. Through programming, the chip acquires the required firmware, operating system, or specific application, enabling it to function as intended. Common programming methods include online programming via interfaces such as USB, JTAG, SPI, and I2C, as well as offline programming using dedicated programmers. Modern programming technology emphasizes not only speed and efficiency but also consistent performance of the programmed chip.

[0003] The programming process for most current chips is irreversible. Any programming error can lead to permanent functional damage or even chip failure. Due to manufacturing variations, the programming address for each chip is not exactly the same. However, current programming equipment typically only has a programming function and a fixed address, resulting in poor performance consistency after programming. Furthermore, the inherent uncertainty of manually constructing the programming waveform significantly impacts programming accuracy. These factors collectively increase the risk and complexity of the programming process.

[0004] Furthermore, different chips or circuits may operate at different voltages. Therefore, during the programming process, control signals often require level conversion to ensure that the signal level can be correctly recognized by the target chip. Common programming interfaces, such as SPI, JTAG, and I2C, may experience voltage mismatches between the host and target chips. The function of a level conversion circuit is to adjust the signal level output by the host controller (such as an MCU) to the level required by the target chip to ensure the correctness and reliability of the programming signal. However, existing level conversion circuits may suffer from insufficient conversion speed in high-frequency applications, resulting in signal waveform distortion or timing errors, affecting programming stability and accuracy. Traditional level conversion circuit designs may involve complex integrated circuits, increasing the complexity and cost of circuit design, making them unsuitable for cost-effective programming equipment.

[0005] Therefore, how to avoid manual burning errors and debug burning more accurately and at a lower cost has become a key problem to be solved. Utility Model Content

[0006] The present invention provides an automated testing and programming device. To achieve the purpose of the present invention, the present invention adopts the following scheme:

[0007] An automated test and programming device includes an MCU, a level conversion circuit, a switch circuit, a chip socket, a power supply circuit, a start circuit, a reset circuit, and a display module;

[0008] The level conversion circuit includes a first level conversion circuit and a second level conversion circuit;

[0009] The general enable signal output terminal and the test burning enable signal output terminal of the MCU are respectively connected to the first input terminal and the second input terminal of the first level conversion circuit, and the first input terminal and the second input terminal of the first level conversion circuit are respectively used for inputting the general enable signal and the test burning enable signal; the first output terminal and the second output terminal of the first level conversion circuit are respectively used for outputting the general enable signal and the test burning enable signal, and the first output terminal and the second output terminal of the first level conversion circuit are respectively connected to the first input terminal and the second input terminal of the switch circuit;

[0010] The clock signal output terminal and the test burning data signal output terminal of the MCU are respectively connected to the first input terminal and the second input terminal of the second level conversion circuit, the first input terminal and the second input terminal of the second level conversion circuit are respectively used for inputting the clock signal and the test burning data signal; the first input terminal and the second input terminal of the second level conversion circuit are respectively used for inputting the clock signal and the test burning data signal; the first output terminal and the second output terminal of the second level conversion circuit are respectively connected to the third input terminal and the fourth input terminal of the switch circuit;

[0011] The first input terminal and the second input terminal of the switch circuit are respectively used for inputting the general enable signal and the test burning enable signal; the third input terminal and the fourth input terminal of the switch circuit are respectively used for inputting the clock signal and the test burning data signal;

[0012] The first output end of the switch circuit is used to output a general enable signal and is connected to the enable pin of the chip slot;

[0013] The second output end of the switch circuit is used to output a test burning enable signal and is connected to a mode selection pin of the chip slot;

[0014] The third output terminal of the switch circuit is used to output a clock signal and is connected to a clock input pin of the chip slot;

[0015] The fourth output end of the switch circuit is used to output a test burning data signal and is connected to a data input pin of the chip slot;

[0016] The data output pin of the chip slot is connected to an input pin of the MCU for feeding back the test pin of the chip;

[0017] The first step-down output terminal of the power supply circuit is connected to the power pin of the MCU, and the second step-down output terminal of the power supply circuit is connected to the power pin of the chip socket.

[0018] Furthermore, the power supply circuit includes a power supply interface, a first step-down circuit, a second step-down circuit and a power supply filter circuit;

[0019] The input end of the power interface is connected to the power input, and the output end of the power interface is connected to the input end of the first step-down circuit and the input end of the second step-down circuit for providing a standard power supply voltage;

[0020] The output end of the second step-down circuit serves as the second step-down output end of the power supply circuit;

[0021] The output end of the first step-down circuit is connected to the input end of the power supply filter circuit;

[0022] The output end of the power supply filter circuit serves as the first step-down output end of the power supply circuit.

[0023] Furthermore, the first level conversion circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS transistor and a second NMOS transistor;

[0024] One end of the first resistor is connected to the gate of the first NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the first resistor is connected to the source of the first NMOS transistor and serves as a general enable signal input terminal of the first level conversion circuit;

[0025] The drain of the first NMOS transistor is connected to one end of the second resistor and serves as the general enable signal output end of the first level conversion circuit, and the other end of the second resistor is connected to the second step-down output end of the power supply circuit as a high voltage reference end;

[0026] One end of the third resistor is connected to the gate of the second NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the third resistor is connected to the source of the second NMOS transistor and serves as a test burning enable signal input terminal of the first level conversion circuit;

[0027] The drain of the NMOS tube is connected to one end of the fourth resistor and serves as the test burning enable signal output end of the first level conversion circuit. The other end of the fourth resistor is connected to the second step-down output end of the power supply circuit as a high voltage reference end.

[0028] Furthermore, the second level conversion circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a third NMOS transistor and a fourth NMOS transistor;

[0029] One end of the fifth resistor is connected to the gate of the third NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the fifth resistor is connected to the source of the third NMOS transistor and serves as a clock signal input terminal of the second level conversion circuit;

[0030] The drain of the third NMOS transistor is connected to one end of the sixth resistor and serves as the clock signal output end of the second level conversion circuit, and the other end of the sixth resistor is connected to the power interface output end of the power circuit as the high voltage reference end;

[0031] One end of the seventh resistor is connected to the gate of the fourth NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the seventh resistor is connected to the source of the fourth NMOS transistor and serves as a test burning data signal input terminal of the second level conversion circuit;

[0032] The drain of the fourth NMOS tube is connected to one end of the eighth resistor and serves as the test burning data signal output end of the second level conversion circuit. The other end of the eighth resistor is connected to the power interface output end of the power circuit as a high voltage reference end.

[0033] Preferably, the switch circuit is used to switch between automatic test and burning modes. When the switch is in the first position, the circuit enters the test mode; when the switch is in the second position, the circuit enters the burning mode; in the test mode, the switch circuit allows the test signal to pass; in the burning mode, the switch circuit allows the burning signal to pass.

[0034] Furthermore, the startup reset circuit includes a startup circuit and a reset circuit, the startup circuit is connected to the startup pin of the MCU, and the reset circuit is connected to the reset pin of the MCU; the MCU feeds back the user's operation by detecting the potential changes of the startup pin and the reset pin.

[0035] Preferably, the display module is an OLED display screen.

[0036] Compared with the prior art, the technical solution of the utility model has the following beneficial effects:

[0037] This new design improves the accuracy of chip signal control logic and reduces the complexity and cost of circuit design by simplifying the level conversion and voltage regulation circuit design. Even if an abnormality occurs during the test programming process, the MCU can provide timely feedback to the operator through the display module, reducing the probability of errors during the programming process. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A module connection diagram provided for an embodiment of the present utility model.

[0039] Figure 2 A level conversion circuit diagram provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0040] The following describes in detail embodiments of the present invention, examples of which are shown in the accompanying drawings. The exemplary embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein. On the contrary, these embodiments are provided to make the present invention more comprehensive and complete and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0041] In the description of the present invention, it should be noted that, unless otherwise clearly stipulated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] In this embodiment, the module connection diagram of the automatic test burning device is as follows: Figure 1 As shown, it includes an MCU, a first level conversion circuit, a second level conversion circuit, a switch circuit, a chip socket, a power supply circuit, a startup circuit, a reset circuit and a display module.

[0043] The power supply circuit in this embodiment includes a power interface, a first step-down circuit, a second step-down circuit, and a power filter circuit. The 5V voltage provided by the external power supply at the power interface is stepped down to 3.3V by the first step-down circuit LDO1 and the power filter circuit and then provided to the MCU. The voltage is then stepped down to 4.5V by the first step-down circuit LDO2 and provided to the chip socket.

[0044] During testing and burning, the MCU is programmed according to the FT test instructions to build, generate and send four signal waveforms, namely the general enable signal, the test burning enable signal, the reference clock signal and the test burning DATA address signal.

[0045] The level conversion circuit of this embodiment is as follows Figure 2 As shown, it includes a first level conversion circuit 1 and a second level conversion circuit 2, wherein the first level conversion circuit 1 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS transistor U1 and a second NMOS transistor U2;

[0046] One end of the first resistor R1 is connected to the gate of the first NMOS transistor U1 and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the first resistor R1 is connected to the source of the first NMOS transistor U1 and serves as the general enable signal input terminal of the first level conversion circuit 1;

[0047] The drain of the first NMOS transistor U1 is connected to one end of the second resistor R2 and serves as the general enable signal output end of the first level conversion circuit 1. The other end of the second resistor R2 is connected to the second step-down output end of the power supply circuit as a high voltage reference end.

[0048] One end of the third resistor R3 is connected to the gate of the second NMOS transistor U2 and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the third resistor R3 is connected to the source of the second NMOS transistor U2 and serves as a test burning enable signal input terminal of the first level conversion circuit 1;

[0049] The drain of the NMOS tube is connected to one end of the fourth resistor R4 and serves as the test burning enable signal output end of the first level conversion circuit 1. The other end of the fourth resistor R4 is connected to the second step-down output end of the power supply circuit as a high voltage reference end.

[0050] The second level conversion circuit 2 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third NMOS transistor U3 and a fourth NMOS transistor U4;

[0051] One end of the fifth resistor R5 is connected to the gate of the third NMOS transistor U3 and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the fifth resistor is connected to the source of the third NMOS transistor U3 and serves as a clock signal input terminal of the second level conversion circuit 2;

[0052] The drain of the third NMOS transistor U3 is connected to one end of the sixth resistor R6 and serves as the clock signal output end of the second level conversion circuit 2. The other end of the sixth resistor R6 is connected to the power interface output end of the power circuit as a high voltage reference end.

[0053] One end of the seventh resistor R7 is connected to the gate of the fourth NMOS transistor U4 and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor U4 and serves as a test burning data signal input terminal of the second level conversion circuit 2;

[0054] The drain of the fourth NMOS transistor U4 is connected to one end of the eighth resistor R8 and serves as the test programming data signal output end of the second level conversion circuit 2. The other end of the eighth resistor R8 is connected to the power interface output end of the power circuit as a high voltage reference end.

[0055] In this embodiment, the general enable signal and the test burn enable signal pass through the first level conversion circuit 1 to convert the signal voltage from 3.3V to 4.5V, and the reference clock signal and the test burn DATA address signal pass through the second level conversion circuit 2 to convert the signal voltage from 3.3V to 5V.

[0056] The specific functions of the level conversion circuit are:

[0057] The first level conversion circuit 1 is connected to its corresponding NMOS transistor source stage through MCU pins (PA9, PA3, PA11, PA10 correspond to the general enable signal, the test burning enable signal, the reference clock signal, and the test burning data signal respectively).

[0058] The 3.3V voltage output by the first step-down circuit LDO1 maintains the gate of the NMOS tube at 3.3V in the working state. When the MCU control pin outputs a low level (0V), the source voltage of the NMOS tube is 0V, the gate voltage is 3.3V, and the NMOS tube is turned on. The 4.5V voltage output by the second step-down circuit is transmitted to the output end of the boost circuit through the resistor (R8 or R10) on the side of the high voltage reference end, thereby realizing the level conversion from 3.3V to 4.5V; when the MCU control pin outputs a high level of 3.3V, the source voltage of the NMOS tube is equal to the gate voltage, the NMOS tube will not be turned on, the output end remains in a high impedance state, and the 4.5V voltage will not be transmitted to the output end.

[0059] The principle of level conversion in the second level conversion circuit 2 is the same as above, and its high voltage reference terminal is connected to the output voltage 5V of the power interface.

[0060] The general enable signal and the test burn enable signal undergo level conversion in the first level conversion circuit 1, raising the signal voltage from 3.3V to 4.5V. The signal is then input to the corresponding input terminals of the chip card slot via a switching circuit. The reference clock signal and the test burn DATA address signal undergo voltage boosting in the second level conversion circuit 2, raising the voltage signal from 3.3V to 5V. The signal is then input to the corresponding input terminals of the chip card slot via a switching circuit. Therefore, by simplifying the level conversion and voltage regulation circuit design, the present invention improves the accuracy of the chip signal control logic and reduces the complexity and cost of the circuit design.

[0061] The switch circuit used in this embodiment is used to switch between automated test and programming modes. When the switch is in the first position, the circuit enters test mode; when the switch is in the second position, the circuit enters programming mode. In test mode, the switch circuit allows test signals to pass; in programming mode, the switch circuit allows programming signals to pass. The switch circuit receives a general enable signal to determine whether the chip is operating. In this embodiment, a high level is set to be active, so it should remain at a high level during operation. The switch circuit receives a test and programming enable signal and controls whether the chip operates in test mode or programming mode by switching the switch between high and low levels. The active operating level selects programming mode. In this embodiment, a high level is selected as the active level. Therefore, if a test operation is required, the signal should remain at a low level, and if a programming operation is required, it should remain at a high level. In test mode, the chip will generate an output as the test result. The reference clock signal will provide a clock for the test programming DATA signal, forming a two-wire communication with the test programming DATA signal. The reference clock signal must contain N clks, where N is equal to the number of address bits of the chip under test + 1. For example, for a 32-bit chip, N = 33, and the reference clock signal must contain 33 clks. The test programming DATA signal selects the address bit to be tested or programmed, and a high level is active. For example, if testing or programming bits 1, 2, or 3, a high level must be output at each of the 1st, 2nd, and 3rd clks of the reference clock signal.

[0062] The automated test process of this embodiment is as follows: after the user triggers the start circuit, the MCU sends a test instruction, and the system enters the test mode to test the chip. The MCU first determines whether the chip has been burned. If so, the test is terminated and FALL is displayed on the OLED display. If the chip has been burned, the default DATA address test is read to determine whether the actual test value data of the chip is within the design value range. If it is within the design value range, the test is stopped and the OLED display shows PASS. If it is not within the design range, the corresponding DATA address is found and re-burned. After the burning is completed, the test is tested again and compared with the design value. If it is within the design value range, the OLED displays PASS. If it is not within the design value range, the OLED displays FALL. The MCU is connected to the start circuit and the reset circuit respectively. By detecting the potential changes of the start circuit and the reset circuit respectively, the user's start or reset operation is fed back. After the first chip completes the burning test, press RST to reset the operation, and then press start to enter the next chip test. The utility model provides feedback through the display module, and can provide timely feedback when abnormal conditions occur during the burning test, thereby greatly reducing the probability of errors during the burning process.

[0063] This new design improves the accuracy of chip signal control logic and reduces the complexity and cost of circuit design by simplifying the level conversion and voltage regulation circuit design. Even if an abnormality occurs during the test programming process, the MCU can provide timely feedback to the operator through the display module, reducing the probability of errors during the programming process.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. An automated test and programming device, characterized in that: Including MCU, level conversion circuit, switch circuit, chip socket, power supply circuit, startup circuit, reset circuit and display module; The level conversion circuit includes a first level conversion circuit and a second level conversion circuit; The general enable signal output terminal and the test burning enable signal output terminal of the MCU are respectively connected to the first input terminal and the second input terminal of the first level conversion circuit, and the first input terminal and the second input terminal of the first level conversion circuit are respectively used for inputting the general enable signal and the test burning enable signal; the first output terminal and the second output terminal of the first level conversion circuit are respectively used for outputting the general enable signal and the test burning enable signal, and the first output terminal and the second output terminal of the first level conversion circuit are respectively connected to the first input terminal and the second input terminal of the switch circuit; The clock signal output terminal and the test burning data signal output terminal of the MCU are respectively connected to the first input terminal and the second input terminal of the second level conversion circuit, the first input terminal and the second input terminal of the second level conversion circuit are respectively used for inputting the clock signal and the test burning data signal; the first input terminal and the second input terminal of the second level conversion circuit are respectively used for inputting the clock signal and the test burning data signal; the first output terminal and the second output terminal of the second level conversion circuit are respectively connected to the third input terminal and the fourth input terminal of the switch circuit; The first input terminal and the second input terminal of the switch circuit are respectively used for inputting the general enable signal and the test burning enable signal; the third input terminal and the fourth input terminal of the switch circuit are respectively used for inputting the clock signal and the test burning data signal; The first output end of the switch circuit is used to output a general enable signal and is connected to the enable pin of the chip slot; The second output end of the switch circuit is used to output a test burning enable signal and is connected to a mode selection pin of the chip slot; The third output terminal of the switch circuit is used to output a clock signal and is connected to a clock input pin of the chip slot; The fourth output end of the switch circuit is used to output a test burning data signal and is connected to a data input pin of the chip slot; The data output pin of the chip slot is connected to an input pin of the MCU for feeding back the test pin of the chip; The first step-down output terminal of the power supply circuit is connected to the power pin of the MCU, and the second step-down output terminal of the power supply circuit is connected to the power pin of the chip socket.

2. An automated test and programming device according to claim 1, characterized in that: The power supply circuit includes a power supply interface, a first step-down circuit, a second step-down circuit and a power supply filter circuit; The input end of the power interface is connected to the power input, and the output end of the power interface is connected to the input end of the first step-down circuit and the input end of the second step-down circuit for providing a standard power supply voltage; The output end of the second step-down circuit serves as the second step-down output end of the power supply circuit; The output end of the first step-down circuit is connected to the input end of the power supply filter circuit; The output end of the power supply filter circuit serves as the first step-down output end of the power supply circuit.

3. An automated test and programming device according to claim 1, characterized in that: The first level conversion circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS transistor and a second NMOS transistor; One end of the first resistor is connected to the gate of the first NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the first resistor is connected to the source of the first NMOS transistor and serves as a general enable signal input terminal of the first level conversion circuit; The drain of the first NMOS transistor is connected to one end of the second resistor and serves as the general enable signal output end of the first level conversion circuit, and the other end of the second resistor is connected to the second step-down output end of the power supply circuit as a high voltage reference end; One end of the third resistor is connected to the gate of the second NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the third resistor is connected to the source of the second NMOS transistor and serves as a test burning enable signal input terminal of the first level conversion circuit; The drain of the NMOS tube is connected to one end of the fourth resistor and serves as the test burning enable signal output end of the first level conversion circuit. The other end of the fourth resistor is connected to the second step-down output end of the power supply circuit as a high voltage reference end.

4. An automated test and programming device according to claim 1, characterized in that: The second level conversion circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a third NMOS transistor and a fourth NMOS transistor; One end of the fifth resistor is connected to the gate of the third NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the fifth resistor is connected to the source of the third NMOS transistor and serves as a clock signal input terminal of the second level conversion circuit; The drain of the third NMOS transistor is connected to one end of the sixth resistor and serves as the clock signal output end of the second level conversion circuit, and the other end of the sixth resistor is connected to the power interface output end of the power circuit as the high voltage reference end; One end of the seventh resistor is connected to the gate of the fourth NMOS transistor and the first step-down output terminal of the power supply circuit as a low voltage reference terminal, and the other end of the seventh resistor is connected to the source of the fourth NMOS transistor and serves as a test burning data signal input terminal of the second level conversion circuit; The drain of the fourth NMOS tube is connected to one end of the eighth resistor and serves as the test burning data signal output end of the second level conversion circuit. The other end of the eighth resistor is connected to the power interface output end of the power circuit as a high voltage reference end.

5. An automated test and programming device according to claim 1, characterized in that: The switch circuit is used to switch between automatic test mode and burning mode. When the switch is in the first position, the circuit enters the test mode; when the switch is in the second position, the circuit enters the burning mode. In the test mode, the switch circuit allows the test signal to pass; in the burning mode, the switch circuit allows the burning signal to pass.

6. An automated test and programming device according to claim 1, characterized in that: The startup reset circuit includes a startup circuit and a reset circuit. The startup circuit is connected to the startup pin of the MCU, and the reset circuit is connected to the reset pin of the MCU. The MCU feeds back the user's operation by detecting the potential changes of the startup pin and the reset pin.

7. An automated test and programming device according to claim 1, characterized in that: The startup circuit is connected to the startup pin of the MCU; The reset circuit is connected to the reset pin of the MCU.

8. An automated test and programming device according to claim 1, characterized in that: The MCU is connected to the display module via an I2C interface; The display module is an OLED display screen.

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