Firmware recovery device

Abstract

The utility model discloses a firmware recovery device, which relates to the technical field of servers and comprises a basic input output system (BIOS), a complex programmable logic device (CPLD), a baseboard management controller (BMC), a first group of storage units and a second group of storage units, the first group of storage units comprises a main BIOS storage unit and a standby BIOS storage unit; the second storage unit comprises a main CPLD storage unit and a standby CPLD storage unit; the BMC is respectively connected with the BIOS (Basic Input / Output System) and the CPLD (Complex Programmable Logic Device). According to the scheme, automatic recovery of the BIOS and the CPLD can be achieved, and the starting effect of the server is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a firmware recovery device. Background Art

[0002] For server products, the computer is mainly booted through the BIOS (Basic Input / Output System).

[0003] During the server boot process, a complex programmable logic device (CPLD) is required to control the server's motherboard power-on sequence. Correct timing is a crucial prerequisite for booting. Furthermore, a baseboard management controller (BMC) is required to monitor and manage the server. BIOS or CPLD anomalies can prevent the server from booting properly. Therefore, to prevent BIOS or CPLD firmware anomalies from causing device boot failures or impacting device reliability, a recovery solution that takes both BIOS and CPLD into account is urgently needed to ensure proper server booting. Utility Model Content

[0004] The present application provides a firmware recovery device to improve the reliability of server startup.

[0005] The device includes a basic input and output system BIOS, a complex programmable logic device CPLD, a baseboard management controller BMC, a first group of storage units and a second group of storage units; the first group of storage units includes a main BIOS storage unit and a backup BIOS storage unit; the second group of storage units includes a main CPLD storage unit and a backup CPLD storage unit;

[0006] The baseboard management controller BMC is connected to the basic input and output system BIOS and the complex programmable logic device CPLD respectively to monitor the status of the basic input and output system BIOS and the complex programmable logic device CPLD;

[0007] When the basic input and output system BIOS is in an abnormal state, the basic input and output system BIOS switches from being connected to the main BIOS storage unit to being connected to the standby BIOS storage unit; the baseboard management controller BMC switches from being connected to the standby BIOS storage unit to being connected to the main BIOS storage unit;

[0008] When the complex programmable logic device CPLD is in an abnormal state, the complex programmable logic device CPLD switches from being connected to the main CPLD storage unit to being connected to the backup CPLD storage unit; the baseboard management controller BMC switches from being connected to the backup CPLD storage unit to being connected to the main CPLD storage unit.

[0009] In a possible implementation, the basic input and output system BIOS and the baseboard management controller BMC are connected to the first group of storage units through a first gate and a second gate respectively; the baseboard management controller BMC is connected to a control end of the first gate and a control end of the second gate;

[0010] The first selector is used to select the basic input and output system BIOS to be connected to the main BIOS storage unit or the standby BIOS storage unit; the second selector is used to select the baseboard management controller BMC to be connected to the main BIOS storage unit or the standby BIOS storage unit.

[0011] In a possible implementation, the baseboard management controller BMC and the complex programmable logic device CPLD are connected to the second group of storage units through a third gate and a fourth gate respectively; the baseboard management controller BMC is connected to a control end of the third gate and a control end of the fourth gate;

[0012] The third selector is used to select the baseboard management controller BMC to be connected to the main CPLD storage unit or the standby CPLD storage unit; the fourth selector is used to select the complex programmable logic device CPLD to be connected to the main CPLD storage unit or the standby CPLD storage unit.

[0013] In a possible implementation, a central processing unit (CPU) is provided in the basic input / output system (BIOS); and the baseboard management controller (BMC) is connected to the central processing unit (CPU) of the basic input / output system (BIOS).

[0014] In a possible implementation, the device further includes a third group of storage units; a main BMC storage unit and a backup BMC storage unit of the third group of storage units;

[0015] When the baseboard management controller BMC is in an abnormal state, the baseboard management controller BMC switches from being connected to the primary BMC storage unit to being connected to the backup BMC storage unit; the central processing unit CPU switches from being connected to the backup BMC storage unit to being connected to the primary BMC storage unit.

[0016] In a possible implementation, the central processing unit (CPU) and the baseboard management controller (BMC) are connected to the third group of storage units via a fifth gate and a sixth gate, respectively; the central processing unit (CPU) is connected to a control end of the fifth gate and a control end of the sixth gate;

[0017] The fifth selector is used to select the central processing unit CPU to be connected to the main BMC storage unit or the standby BMC storage unit; the sixth selector is used to select the baseboard management controller BMC to be connected to the main BMC storage unit or the standby BMC storage unit.

[0018] In a possible implementation, the complex programmable logic device (CPLD) includes a target register; the working state of the target register is used to indicate the power-on state of the server;

[0019] When the power-on state of the server is abnormal, the power-on control terminal of each device to be powered on in the server switches from being connected to the complex programmable logic device CPLD to being connected to the baseboard management controller BMC.

[0020] In one possible implementation, the device also includes a seventh selector, which is used to select each device to be powered on in the server to be connected to the baseboard management controller BMC or to the complex programmable logic device CPLD; the baseboard management controller BMC is connected to the control end of the seventh selector.

[0021] The technical solution provided by this application may have the following beneficial effects:

[0022] The present application provides a firmware recovery device, comprising a basic input / output system (BIOS), a complex programmable logic device (CPLD), a baseboard management controller (BMC), a first group of storage units, and a second group of storage units; the first group of storage units includes a primary BIOS storage unit and a backup BIOS storage unit; the second storage unit includes a primary CPLD storage unit and a backup CPLD storage unit; the baseboard management controller (BMC) is connected to the basic input / output system (BIOS) and the complex programmable logic device (CPLD) respectively to monitor the status of the basic input / output system (BIOS) and the complex programmable logic device (CPLD). The firmware recovery device provided by the above scheme can enable the baseboard management controller (BMC) to monitor the startup process of the basic input / output system (BIOS) and the complex programmable logic device (CPLD). When an abnormality occurs in the basic input / output system (BIOS) and / or the complex programmable logic device (CPLD), the BMC controls the abnormal BIOS to communicate with the backup BIOS storage unit and / or the abnormal CPLD to communicate with the corresponding backup CPLD storage unit to read the backup firmware for startup. The BMC also synchronizes with the primary BIOS storage unit and / or the primary CPLD storage unit to flash the corresponding stored backup firmware, thereby automatically recovering the BIOS and CPLD and ensuring the startup effect of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 The figure is a schematic diagram showing a firmware recovery device according to an exemplary embodiment.

[0025] Figure 2 A schematic structural diagram of a firmware recovery device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0027] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0028] Figure 1 FIG. 1 is a schematic diagram of a firmware recovery device according to an exemplary embodiment. Figure 1 As shown, the device includes a basic input and output system BIOS, a complex programmable logic device CPLD, a baseboard management controller BMC, a first group of storage units and a second group of storage units; the first group of storage units includes a main BIOS storage unit and a backup BIOS storage unit; the second group of storage units includes a main CPLD storage unit and a backup CPLD storage unit;

[0029] The baseboard management controller BMC is connected to the basic input and output system BIOS and the complex programmable logic device CPLD respectively to monitor the status of the basic input and output system BIOS and the complex programmable logic device CPLD;

[0030] When the basic input and output system BIOS is in an abnormal state, the basic input and output system BIOS switches from being connected to the main BIOS storage unit to being connected to the standby BIOS storage unit; the baseboard management controller BMC switches from being connected to the standby BIOS storage unit to being connected to the main BIOS storage unit;

[0031] When the complex programmable logic device CPLD is in an abnormal state, the complex programmable logic device CPLD switches from being connected to the main CPLD storage unit to being connected to the backup CPLD storage unit; the baseboard management controller BMC switches from being connected to the backup CPLD storage unit to being connected to the main CPLD storage unit.

[0032] In the above scheme, the baseboard management controller BMC can monitor the status of the basic input and output system BIOS and the complex programmable logic device CPLD. When the BIOS and the CPLD are working normally, the BMC is connected to the backup BIOS storage unit and the backup CPLD storage unit to copy the firmware to the BMC storage; when it is detected that the BIOS is abnormal, the BMC switches from connecting with the backup BIOS storage unit to connecting with the main BIOS storage unit, and rewrites the stored backup firmware to the main BIOS storage unit, and the BIOS switches from connecting with the main BIOS storage unit to connecting with the backup BIOS storage unit, and is started by the firmware stored on the backup BIOS storage unit; when it is detected that the CPLD is abnormal, the BMC switches from connecting with the backup CPLD storage unit to connecting with the main CPLD storage unit, and rewrites the stored backup firmware to the main CPLD storage unit, and the CPLD switches from connecting with the main CPLD storage unit to connecting with the backup CPLD storage unit, and is started by the firmware stored on the backup CPLD storage unit.

[0033] Optional, Figure 2 FIG. 1 shows a schematic diagram of the structure of a firmware recovery device according to an embodiment of the present application. Figure 2 As shown, the basic input and output system BIOS and the baseboard management controller BMC are connected to the first group of storage units through the first selector 101 and the second selector 102 respectively; the baseboard management controller BMC is connected to the control end of the first selector 101 and the control end of the second selector 102.

[0034] Optional, such as Figure 2 As shown, the baseboard management controller BMC and the complex programmable logic device CPLD are connected to the second group of storage units through the third gate 103 and the fourth gate 104 respectively; the baseboard management controller BMC is connected to the control end of the third gate 103 and the control end of the fourth gate 104.

[0035] That is, the basic input and output system BIOS and the baseboard management controller BMC can choose to connect to the main BIOS storage unit or the backup BIOS storage unit in the first group of storage units through the first selector 101 and the second selector 102, and the baseboard management controller BMC can control the selection state of the first selector 101 and the second selector 102 by sending SW (switch) signals to the control ends of the first selector 101 and the second selector 102.

[0036] The third selector 103 is used to select the baseboard management controller BMC to be connected to the main CPLD storage unit or the backup CPLD storage unit; the fourth selector 104 is used to select the complex programmable logic device CPLD to be connected to the main CPLD storage unit or the backup CPLD storage unit.

[0037] Similarly, the complex programmable logic device CPLD and the baseboard management controller BMC can choose to connect to the main CPLD storage unit in the second group of storage units or to the backup CPLD storage unit through the third selector 103 and the fourth selector 104, and the baseboard management controller BMC can control the selection state of the third selector 103 and the fourth selector 104 by sending SW (switch) signals to the control ends of the third selector 103 and the fourth selector 104.

[0038] like Figure 2 As shown, the main BIOS storage unit in the first group of storage units is as follows Figure 2 The main BIOSFlash shown in the figure, the backup BIOS storage unit is as follows Figure 2 The backup BIOS Flash shown in FIG. 1 and FIG. 2 both store BIOS firmware; the main CPLD storage unit in the second group of storage units is as follows: Figure 2 The main CPLD Flash shown in FIG; the backup CPLD memory unit in the second group of memory units is as follows Figure 2 The standby CPLD Flash shown in the figure; both store the CPLD firmware.

[0039] Furthermore, a central processing unit (CPU) is provided in the basic input / output system (BIOS); and the baseboard management controller (BMC) is connected to the central processing unit (CPU) of the basic input / output system (BIOS).

[0040] Furthermore, the device further includes a third group of storage units; a main BMC storage unit and a backup BMC storage unit of the third group of storage units;

[0041] When the baseboard management controller BMC is in an abnormal state, the baseboard management controller BMC switches from being connected to the primary BMC storage unit to being connected to the backup BMC storage unit; the central processing unit CPU switches from being connected to the backup BMC storage unit to being connected to the primary BMC storage unit.

[0042] The above solution enables the CPU in the BIOS to monitor the BMC status while the BMC detects the BIOS and CPLD status. When an abnormality is detected, the CPLD is started through the standby CPLD storage unit, the BIOS is started through the standby BIOS storage unit, and the BMC is started through the standby BMC storage unit. The BMC also performs firmware flash recovery on the primary BIOS storage unit and the primary CPLD storage unit, and the CPU performs firmware flash recovery on the primary BMC storage unit, thus achieving mutual monitoring and recovery of the firmware.

[0043] Further, such as Figure 2 As shown, the central processing unit CPU and the baseboard management controller BMC are connected to the third group of storage units through the fifth gate 105 and the sixth gate 106 respectively; the central processing unit CPU is connected to the control end of the fifth gate 105 and the control end of the sixth gate 106;

[0044] The fifth selector 105 is used to select the central processing unit CPU to be connected to the main BMC storage unit or the backup BMC storage unit; the sixth selector 106 is used to select the baseboard management controller BMC to be connected to the main BMC storage unit or the backup BMC storage unit.

[0045] The first gate 101 to the sixth gate 106 are all SPI MUX switching channels.

[0046] The main BMC storage unit in the third group of storage units is as follows: Figure 2 The main BMC Flash shown in the figure; the backup BMC storage unit in the third group of storage units is as follows Figure 2 The backup BMC Flash shown in the figure both store the BMC firmware.

[0047] In the embodiment of the present application, the BMC and CPLD / BIOS send monitoring signals to each other. If one of them does not receive the monitoring signal, it is possible that the firmware is abnormal. In this case, the backup firmware will be used to start the system, and the main firmware will be flashed and restored at the same time.

[0048] During normal power-on, the CPU, BMC, and CPLD all connect to the primary Flash to read the firmware for startup. Simultaneously, the BMC connects to the backup BIOS Flash and backup CPLD Flash to copy the firmware to the BMC storage, and the CPU connects to the backup BMC Flash to copy the firmware to the CPU storage.

[0049] When the BMC determines that the BIOS firmware is abnormal through the BIOS monitoring signal, it sends an SW signal to the SPI MUX switching channel corresponding to the first connector and the second connector, and the BIOS will connect with the backup BIOS Flash to read the backup firmware to start; at the same time, the BMC connects with the main BIOS Flash to rewrite the stored backup firmware to the main BIOS Flash; the next time the CPU is powered on, it will preferably connect with the main BIOS Flash to read the firmware to start.

[0050] Similarly, when the BMC determines that the CPLD firmware is abnormal through the CPLD monitoring signal, it sends an SW signal to the SPI MUX switching channel corresponding to the third and fourth connectors. The CPLD will connect to the backup CPLD Flash to read the backup firmware for startup. At the same time, the BMC connects to the primary CPLD Flash to rewrite the stored backup firmware to the primary CPLD Flash. The next time the CPU is powered on, it will preferentially connect to the primary CPLD Flash to read the firmware for startup.

[0051] Similarly, when the CPU determines that the BMC firmware is abnormal through the BMC monitoring signal, it sends an SW signal to the SPI MUX switching channel corresponding to the fifth and sixth connectors, and the BMC will connect with the backup BMC Flash to read the backup firmware for startup; at the same time, the CPU connects with the main BMC Flash to rewrite the stored backup firmware to the main BMC Flash; the next time the BMC is powered on, it will preferably connect with the main BMC Flash to read the firmware for startup.

[0052] In a possible implementation, the complex programmable logic device (CPLD) includes a target register; the working state of the target register is used to indicate the power-on state of the server.

[0053] When the power-on state of the server is abnormal, the power-on control terminal of each device to be powered on in the server switches from being connected to the complex programmable logic device CPLD to being connected to the baseboard management controller BMC.

[0054] In one possible implementation, the device also includes a seventh selector, which is used to select each device to be powered on in the server to be connected to the baseboard management controller BMC or to the complex programmable logic device CPLD; the baseboard management controller BMC is connected to the control end of the seventh selector.

[0055] In an embodiment of the present application, when the BMC determines that the CPLD firmware is abnormal through the CPLD monitoring signal, the BMC reads the register value of the CPLD and compares the read register value with the set register characteristic value to determine whether the power-on process is abnormal; when the read register value is different from the set register characteristic value, the power-on is abnormal, and a reset is sent to the CPLD to stop it from working; at the same time, the BMC controls the selection state of the seventh selector, so that the seventh selector switches from CH_A to CH_B, that is, each device to be powered on in the server is switched from being connected to the CPLD to being connected to the baseboard management controller BMC, and the abnormal point can be determined according to the register value and the BMC continues to drive the power-on sequence based on the abnormal point.

[0056] In summary, the present application provides a firmware recovery device, including a basic input and output system BIOS, a complex programmable logic device CPLD, a baseboard management controller BMC, a first group of storage units, a second group of storage units, and a third storage unit; the first group of storage units includes a main BIOS storage unit and a backup BIOS storage unit; the second storage unit includes a main CPLD storage unit and a backup CPLD storage unit, and the third storage unit includes a main BMC storage unit and a backup BMC storage unit; the BMC monitors the status of the BIOS and CPLD, the CPU in the BIOS monitors the status of the BMC, and the BMC takes over the power-on sequence when detecting a CPLD abnormality.

[0057] That is, the firmware recovery device provided by the above solution can realize the monitoring of the basic input and output system BIOS and the complex programmable logic device CPLD startup process by the baseboard management controller BMC, and when the basic input and output system BIOS and / or the complex programmable logic device CPLD are abnormal, the BMC controls the abnormal BIOS to connect with the backup BIOS storage unit and / or the abnormal CPLD to connect with the corresponding backup CPLD storage unit to read the backup firmware for startup, and the BMC synchronously connects with the main BIOS storage unit and / or the main CPLD storage unit to flash the corresponding stored backup firmware, thereby realizing automatic recovery of the BIOS and CPLD and ensuring the startup effect of the server;

[0058] Furthermore, in the firmware recovery device provided by the above solution, the CPU can also monitor the status of the BMC. When an abnormality occurs in the BMC, the CPU controls the abnormal BMC to connect to the backup BMC storage unit to read the backup firmware for startup, thereby realizing automatic recovery of the BMC.

[0059] In addition, the BMC in the firmware recovery device provided by the above solution can also detect CPLD firmware abnormalities, determine whether the power-on process is abnormal, and promote the power-on sequence through the BMC when an abnormality occurs, ensuring that all components in the server can be powered on normally when the CPLD is abnormal.

[0060] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0061] It will be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A firmware recovery device, characterized in that: The device includes a basic input and output system BIOS, a complex programmable logic device CPLD, a baseboard management controller BMC, a first group of storage units and a second group of storage units; the first group of storage units includes a main BIOS storage unit and a backup BIOS storage unit; the second group of storage units includes a main CPLD storage unit and a backup CPLD storage unit; The baseboard management controller BMC is connected to the basic input and output system BIOS and the complex programmable logic device CPLD respectively to monitor the status of the basic input and output system BIOS and the complex programmable logic device CPLD; When the basic input and output system BIOS is in an abnormal state, the basic input and output system BIOS switches from being connected to the main BIOS storage unit to being connected to the standby BIOS storage unit; the baseboard management controller BMC switches from being connected to the standby BIOS storage unit to being connected to the main BIOS storage unit; When the complex programmable logic device CPLD is in an abnormal state, the complex programmable logic device CPLD switches from being connected to the main CPLD storage unit to being connected to the backup CPLD storage unit; the baseboard management controller BMC switches from being connected to the backup CPLD storage unit to being connected to the main CPLD storage unit.

2. The device according to claim 1, characterized in that The basic input and output system BIOS and the baseboard management controller BMC are connected to the first group of storage units through a first gate and a second gate respectively; the baseboard management controller BMC is connected to the control end of the first gate and the control end of the second gate; The first selector is used to select the basic input and output system BIOS to be connected to the main BIOS storage unit or the standby BIOS storage unit; the second selector is used to select the baseboard management controller BMC to be connected to the main BIOS storage unit or the standby BIOS storage unit.

3. The device according to claim 2, characterized in that The baseboard management controller BMC and the complex programmable logic device CPLD are connected to the second group of storage units through a third gate and a fourth gate respectively; the baseboard management controller BMC is connected to the control end of the third gate and the control end of the fourth gate; The third selector is used to select the baseboard management controller BMC to be connected to the main CPLD storage unit or the standby CPLD storage unit; the fourth selector is used to select the complex programmable logic device CPLD to be connected to the main CPLD storage unit or the standby CPLD storage unit.

4. The device according to claim 3, characterized in that The basic input and output system BIOS is provided with a central processing unit CPU; the baseboard management controller BMC is connected to the central processing unit CPU of the basic input and output system BIOS.

5. The device according to claim 4, characterized in that The device further includes a third group of storage units; a main BMC storage unit and a backup BMC storage unit of the third group of storage units; When the baseboard management controller BMC is in an abnormal state, the baseboard management controller BMC switches from being connected to the primary BMC storage unit to being connected to the backup BMC storage unit; the central processing unit CPU switches from being connected to the backup BMC storage unit to being connected to the primary BMC storage unit.

6. The device according to claim 5, characterized in that The central processing unit CPU and the baseboard management controller BMC are connected to the third group of storage units through a fifth gate and a sixth gate respectively; the central processing unit CPU is connected to the control end of the fifth gate and the control end of the sixth gate; The fifth selector is used to select the central processing unit CPU to be connected to the main BMC storage unit or the standby BMC storage unit; the sixth selector is used to select the baseboard management controller BMC to be connected to the main BMC storage unit or the standby BMC storage unit.

7. The device according to any one of claims 1 to 6, characterized in that The complex programmable logic device CPLD includes a target register; the working state of the target register is used to indicate the power-on state of the server; When the power-on state of the server is abnormal, the power-on control terminal of each device to be powered on in the server switches from being connected to the complex programmable logic device CPLD to being connected to the baseboard management controller BMC.

8. The device according to claim 7, characterized in that The device also includes a seventh selector, which is used to select each device to be powered on in the server to be connected to the baseboard management controller BMC or to the complex programmable logic device CPLD; the baseboard management controller BMC is connected to the control end of the seventh selector.

Images