Direct-current converter and power-on slow start circuit thereof

Abstract

The utility model provides a direct-current converter and a power-on slow start circuit thereof. The capacitive surge current suppression effect does not change along with the capacitance value of an input capacitor. The power-on slow start circuit comprises an NMOS tube Smain, S1 and S2, capacitors C1 and C2, a resistor R1, a diode D1, two discharge circuits, a current detection circuit, and a controller which is connected with the output end of the current detection circuit and the grid electrode of S2 at the same time. The drain electrode of the S1 is connected with a power supply and is connected with the anode of the diode D1 and the drain electrode of the S2 through the R1; the grid electrode of the S1 is connected with the cathode of the diode D1 and one end of the C1; the source electrode of the S1 is connected with one end of the C2 and the grid electrode of the Smain; the source electrode of the Smain, the other end of the C2, the other end of the C1 and the source electrode of the S2 are all connected with the input negative electrode of the direct current converter; the drain electrode of the Smain is connected with the low-voltage end of the Cin; the first discharge circuit is connected in series with the C1; and the second discharge circuit is connected in series with the C2.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a DC converter and a power-on slow start circuit thereof. Background Art

[0002] A DC converter is a power electronic device used to convert one DC power source into another with different output characteristics. While a large capacitor connected to the input side of a DC converter (i.e., input capacitor) helps stabilize the input voltage, it can generate a large capacitive surge current at power-on due to its characteristics, potentially damaging downstream circuitry.

[0003] In order to suppress the capacitive surge current generated at the moment of power-on, a power-on slow-start circuit is usually used to limit the input current at the initial stage of power-on, so that the input capacitor charges at a relatively slow rate, thereby achieving a smooth and slow startup of the DC converter.

[0004] The slow-start time of existing power-on slow-start circuits is completely dependent on the charging time constant determined by the parameter values ​​of the resistor and capacitor within the circuit. When the capacitance of the input capacitor changes, in order to maintain the capacitive surge current suppression effect, the parameter values ​​of the resistor and capacitor must be readjusted to change the slow-start time accordingly, resulting in poor circuit flexibility and adaptability. Utility Model Content

[0005] In view of the above problems, the present application provides a DC converter and a power-on slow start circuit thereof to achieve a capacitive surge current suppression effect that does not change with changes in the input capacitor value. The specific solution is as follows:

[0006] The first aspect of the present application provides a power-on slow start circuit for a DC converter, comprising: an NMOS transistor S main , NMOS transistor S1, NMOS transistor S2, capacitor C1, capacitor C2, resistor R1, diode D1, first discharge circuit, second discharge circuit, current detection circuit and controller;

[0007] The drain of the NMOS transistor S1 is connected to the output end of the auxiliary power supply of the DC converter, and is connected to the anode of the diode D1 and the drain of the NMOS transistor S2 via the resistor R1;

[0008] The gate of the NMOS transistor S1 is connected to the cathode of the diode D1 and one end of the capacitor C1;

[0009] The source of the NMOS transistor S1 is connected to one end of the capacitor C2 and the NMOS transistor S main The gate;

[0010] The NMOS tube S mainThe source of the capacitor C2, the other end of the capacitor C1 and the source of the NMOS transistor S2 are all connected to the negative input electrode of the DC converter;

[0011] The NMOS tube S main The drain of the DC converter is connected to the input capacitor C in The low voltage end;

[0012] The first discharge circuit is connected in series with the capacitor C1 and is used to discharge the capacitor C1, and the discharge rate of the first discharge circuit to the capacitor C1 is lower than the charging rate of the capacitor C1;

[0013] The second discharge circuit is connected in series with the capacitor C2, and is used to discharge the capacitor C2, and its discharge rate for the capacitor C2 is lower than the charging rate of the capacitor C2;

[0014] The output end of the current detection circuit is connected to the input end of the controller; the current detection circuit is used to detect the input current of the DC converter and output it to the controller; the output end of the controller is connected to the gate of the NMOS tube S2.

[0015] In a possible implementation, the first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1;

[0016] The second discharge circuit includes: a diode D2, the resistor R2 and the NMOS transistor S1; the anode of the diode D2 is connected to the source of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1;

[0017] The resistance of the resistor R1 is smaller than the resistance of the resistor R2.

[0018] In a possible implementation, the NMOS transistor S main MOS tube using DPAK package.

[0019] In a possible implementation, the first discharge circuit includes: a resistor R2, wherein the resistor R2 is connected in parallel with the capacitor C1;

[0020] The second discharge circuit includes: a diode D2 and a resistor R2; the anode of the diode D2 is connected to the source of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1;

[0021] The resistance of the resistor R1 is smaller than the resistance of the resistor R2.

[0022] In a possible implementation, the first discharge circuit includes: a resistor R2, wherein the resistor R2 is connected in parallel with the capacitor C1;

[0023] The second discharge circuit includes: a resistor R3; the resistor R3 is connected in parallel with the capacitor C2;

[0024] The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

[0025] In a possible implementation, the first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1;

[0026] The second discharge circuit includes: a resistor R3; the resistor R3 is connected in parallel with the capacitor C2;

[0027] The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

[0028] In a possible implementation, the first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1;

[0029] The second discharge circuit includes: a resistor R3, a resistor R2 and an NMOS transistor S2; one end of the resistor R3 is connected to the source of the NMOS transistor S1, and the other end of the resistor R3 is connected to the cathode of the diode D1;

[0030] The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

[0031] In a possible implementation, the current detection circuit includes a current Hall sensor or a current sampling resistor.

[0032] A second aspect of the present application provides a DC converter, comprising: a power-on slow start circuit according to the first aspect or any implementation of the first aspect.

[0033] By means of the above technical solution, the working principle of the power-on slow start circuit provided by the present application is as follows: before the DC converter is powered on, all NMOS transistors are in the cut-off state, and the current and capacitor voltage are both zero. After power-on, the auxiliary power supply charges the capacitor C1 through the resistor R1 and the diode D1, turning on the NMOS transistor S1, and then charging the capacitor C2 through the NMOS transistor S1. When the voltage across the capacitor C2 reaches the NMOS transistor S1, the capacitor C2 is charged. main When the turn-on voltage of NMOS tube S main It is turned on and enters the variable resistance area, and the input current I in Start to increase, and the input capacitance C in Charging. The controller is based on the input current I in With the set value Iin_start The size of the NMOS tube S2 is compared to control the conduction and cutoff, thereby adjusting the input current I in and the voltage across capacitors C1 and C2, so that the input current I in Maintain at set value I in_start Nearby, input capacitor C in The voltage across both ends rises linearly; when the input capacitor C in When the voltage at both ends reaches the input voltage, the power-on slow start process ends. It can be seen that this circuit realizes the power-on slow start time with the input capacitor C in The capacitance value changes, but the input current I in The maximum value of the capacitive surge current remains constant (that is, the capacitive surge current suppression effect does not change with the input capacitor C in Capacitance change), shows the circuit's response to different input capacitance C in High adaptability and flexibility of configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0035] Figure 1 A schematic diagram of a power-on slow-start circuit for a DC converter provided in this application;

[0036] Figure 2 for Figure 1 The main working waveform of the power-on slow start circuit is shown in the figure;

[0037] Figure 3 for Figure 1 The PCB layout diagram of the power-on slow start circuit is shown;

[0038] Figure 4 A schematic diagram of a power-on slow-start circuit for another DC converter provided in this application;

[0039] Figure 5 A schematic diagram of a power-on slow-start circuit for another DC converter provided in this application;

[0040] Figure 6 A schematic diagram of a power-on slow-start circuit for another DC converter provided in this application;

[0041] Figure 7 This is a schematic diagram of a power-on slow start circuit of another DC converter provided in this application. DETAILED DESCRIPTION

[0042] In the following explanation, in order to ensure the accuracy of citations and the fluency of reading, the key technical terms, abbreviations or abbreviations involved in the article are summarized and explained as follows:

[0043] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor, referred to as MOS tube;

[0044] IGBT: Insulated Gate Bipolar Transistor, insulated gate bipolar transistor;

[0045] NMOS tube: N-type channel MOS tube;

[0046] PMOS tube: P-type channel MOS tube;

[0047] PCB: Printed Circuit Board, also known as printed circuit board.

[0048] A DC converter, also known as a DC-DC converter or DC-DC converter, converts one DC power source into another with different output characteristics. The DC converter operates by periodically turning on and off internal switching transistors (such as MOS transistors or IGBTs), intermittently applying the input voltage to the load. The output voltage is adjusted by varying the duty cycle of the internal switching transistors (the duty cycle is the ratio of the time the switch is on during a switching cycle to the total switching cycle). DC converters play a vital role in the field of power electronics and are widely used in portable electronic devices, electric vehicles, power systems, and other applications.

[0049] To ensure stable input voltage during DC converter operation and absorb ripple current to a certain extent, a large-capacitance capacitor, called an input capacitor, is typically connected to the input side of the DC converter. However, the introduction of an input capacitor also brings a potential problem: at the moment of power-on, if appropriate measures are not taken, a large capacitive surge current may be generated due to the characteristics of the capacitor.

[0050] Specifically, capacitive inrush current occurs because during the initial charging phase of a capacitor, the voltage across it rapidly rises from zero. To maintain its charge-voltage relationship (i.e., Q = CV, where Q represents the stored charge, C represents the capacitance, and V represents the voltage across it), the capacitor attempts to draw a large amount of current from the power supply to quickly charge. Large capacitors (i.e., large-value capacitors) have a larger capacitance, and according to the formula Q = CV, at the same voltage V, they need to store a larger charge (Q). Therefore, during the charging process, large capacitors attempt to draw more current than smaller capacitors (i.e., small-value capacitors), resulting in a larger capacitive inrush current. This large capacitive inrush current can damage downstream circuits.

[0051] To address this issue, a slow-start circuit is typically added to the DC converter's input side. This circuit limits the current during the initial power-up phase, allowing the capacitor to charge at a relatively slow rate. This prevents large capacitive surge currents from occurring when the DC converter is powered on (enabling a smooth and slow startup of the DC converter).

[0052] Existing power-on slow-start circuits typically connect a MOS transistor in series with the input circuit, along with components such as a resistor, capacitor, and Zener diode. The resistor and capacitor form a charging time constant circuit to control the MOS transistor's gate drive voltage to rise slowly during power-on, slowly increasing the MOS transistor's conduction level and thus limiting the rapid increase in capacitive surge current. The slow-start time of these existing power-on slow-start circuits (i.e., the time required from the start of power supply to the overall stable operating state of the slow-start circuit) is entirely dependent on the charging time constant τ of the charging time constant circuit. This value is determined by the parameters of the resistor and capacitor. Therefore, if the capacitance of the DC converter's input capacitor changes, the resistor and capacitor parameters must be readjusted to maintain the capacitive surge current suppression effect, thereby changing the slow-start time accordingly. This results in poor flexibility and adaptability of the power-on slow-start circuit.

[0053] In order to improve the flexibility and adaptability of the power-on slow start circuit, an embodiment of the present application provides a power-on slow start circuit for a DC converter. The power-on slow start circuit controls the gate voltage of the MOS tube connected in series in the input loop in real time according to the input current detected in real time, which can almost achieve the effect of constant current slow start of the DC converter, and is not dependent on the capacitance value of the input capacitor. It has the advantages of high flexibility and strong scalability.

[0054] The following is a detailed description of a DC converter power-on slow start circuit provided by an embodiment of the present application in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0055] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0056] See also Figure 1 The embodiment of the present application provides a DC converter power-on slow start circuit, specifically comprising: an NMOS tube S main , NMOS transistor S1, NMOS transistor S2, capacitor C1, capacitor C2, resistor R1, diode D1, first discharge circuit, second discharge circuit, current detection circuit and controller;

[0057] The drain D of the NMOS transistor S1 is connected to the output end of the auxiliary power supply of the DC converter, and is connected to the anode of the diode D1 and the drain D of the NMOS transistor S2 through the resistor R1;

[0058] The gate G of the NMOS transistor S1 is connected to the cathode of the diode D1 and one end of the capacitor C1;

[0059] The source S of the NMOS tube S1 is connected to one end of the capacitor C2 and the NMOS tube S main The gate G;

[0060] NMOS tube S main The source S of , the other end of capacitor C2, the other end of capacitor C1 and the source S of NMOS tube S2 are all connected to the negative input electrode of the DC converter;

[0061] NMOS tube S main The drain D is connected to the input capacitor C of the DC converter in The low voltage end;

[0062] The first discharge circuit is connected in series with the capacitor C1, and is used to discharge the capacitor C1, and the discharge rate of the first discharge circuit to the capacitor C1 is lower than the charging rate of the capacitor C1;

[0063] The second discharge circuit is connected in series with the capacitor C2 and is used to discharge the capacitor C2, and the discharge rate of the capacitor C2 by it is less than the charging rate of the capacitor C2;

[0064] The output terminal of the current detection circuit is connected to the input terminal of the controller; the current detection circuit is used to detect the input current of the DC converter and output it to the controller; the output terminal of the controller is connected to the gate G of the NMOS transistor S2.

[0065] Among them, the capacitor C2 can be an equivalent capacitor, which is the sum of the parasitic capacitance of the NMOS transistor S main and the externally applied capacitor. Figure 1 The NMOS transistor S1, the NMOS transistor S2, the capacitor C1, the capacitor C2, the resistor R1, the diode D1, the first discharge circuit, the second discharge circuit and the controller in the shown power-on soft-start circuit together constitute the drive voltage control circuit of the NMOS transistor S main .

[0066] In a possible implementation, still referring to Figure 1 , the first discharge circuit includes the resistor R2 and the above-mentioned NMOS transistor S1, and the resistor R2 is connected in parallel with the diode D1. The second discharge circuit includes the diode D2, the above-mentioned resistor R2 and the above-mentioned NMOS transistor S1; the anode of the diode D2 is connected to the source S of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1. It can be seen that in Figure 1 the shown scheme, the NMOS transistor S2 independent of the two discharge circuits is reused in the first discharge circuit and the second discharge circuit; the resistor R2 in the first discharge circuit is reused in the second discharge circuit.

[0067] Next, in combination with the working characteristics of the NMOS transistor, the Figure 1 working principle of the shown power-on soft-start circuit is analyzed:

[0068] MOS transistors can be divided into two types, NMOS transistors and PMOS transistors, according to the channel type. The working characteristics of an NMOS transistor are as follows 1)~3):

[0069] 1) The conduction and cut-off of the NMOS transistor are mainly controlled by the gate-source voltage VGS of the NMOS transistor (that is, the voltage difference between the gate G and the source S of the NMOS transistor). When the gate-source voltage VGS of the NMOS transistor < the threshold voltage VGSth of the NMOS transistor, the NMOS transistor is in the cut-off region (that is, the NMOS transistor is in the cut-off state). At this time, there is no conductive channel between the drain D and the source S, and the drain current is close to zero.

[0070] 2) When the gate-source voltage VGS ≥ the threshold voltage VGSth, the NMOS transistor conducts, allowing current to flow from the source S to the drain D; moreover, when the gate-source voltage VGS ≥ the threshold voltage VGSth and the drain-source voltage VDS (i.e., the voltage difference between the drain D and the source S of the NMOS transistor) < VGS - VGSth, the NMOS transistor enters the variable resistance region. In the variable resistance region, the region between the drain D and the source S of the NMOS transistor can be regarded as a variable resistor controlled by the gate-source voltage VGS. The larger the gate-source voltage VGS, the smaller the impedance of the variable resistor (referred to as the on-resistance); conversely, the smaller the gate-source voltage VGS, the larger the impedance of the variable resistor.

[0071] 3) When the drain-source voltage VDS increases to a certain extent such that VDS ≥ VGS - VGSth, the NMOS transistor enters the saturation region from the variable resistance region. In the saturation region, the drain current no longer changes significantly with the change of the drain-source voltage VDS, the drain current of the NMOS transistor is basically stable, and the on-resistance of the NMOS transistor reaches the minimum.

[0072] Still referring to Figure 1 , before the DC converter is powered on, the NMOS transistors S1, S2, and NMOS transistor S main are all in the cut-off state, and the input current I in (i.e., the drain current of the NMOS transistor S main ) is zero, and the voltages across the capacitors C1, C2, and the input capacitor C in are also zero.

[0073] Combined with Figure 2 the main working waveform diagram of the power-on soft-start circuit shown in Figure 1 (not drawn in dr ), after the DC converter is powered on at time t0, the auxiliary power supply ( Figure 1 not drawn in dr ) provides a stable DC voltage V dr and powers the controller; the DC voltage V dr provided by the auxiliary power supply charges the capacitor C1 through the resistor R1 and the diode D1, and the voltage across the capacitor C1 gradually increases. The difference between the voltage across the capacitor C1 and the voltage across the capacitor C2, V C2 , is equal to the gate-source voltage of the NMOS transistor S1. When the gate-source voltage of the NMOS transistor S1 is greater than the threshold voltage of the NMOS transistor S1, the NMOS transistor S1 conducts; moreover, since the drain-source voltage of the NMOS transistor S1 is high enough, the NMOS transistor S1 is in the saturation region after conduction;

[0074] After the NMOS transistor S1 conducts, the DC voltage V dr provided by the auxiliary power supply starts to charge the capacitor C2 through the NMOS transistor S1, and the voltage V C2 across the capacitor C2 begins to gradually increase;

[0075] The voltage V across the capacitor C2C2 Equal to NMOS tube S main The gate-source voltage of NMOS tube S main The gate-source voltage exceeds the NMOS tube S main When the turn-on voltage of NMOS tube S main is turned on, and because the NMOS tube S main The drain-source voltage VDS of NMOS tube is low, so main After being turned on, it enters the variable resistance area; NMOS tube S main After entering the variable resistance area, the input current I in Flowing through the input capacitor C in 、NMOS tube S main The circuit is formed, starting with the input capacitor C in Charging, input capacitor C in The voltage at both ends begins to increase gradually, and the input current I in It also gradually increases;

[0076] At the same time, the current detection circuit will also detect the input current I in The controller inputs the current I in With the set value I in_start For comparison, when I in in_start When the controller controls the NMOS tube S2 to keep the cut-off state, the voltage V across the capacitor C2 C2 Continue to increase, the input current I in Continue to increase until time t1.

[0077] At time t1, the controller detects that I in ≥I in_start , immediately controls NMOS tube S2 to enter the conduction state. At this time, the drain voltage of NMOS tube S2 is 0, so capacitors C1 and C2 are no longer charged. Capacitor C1 slowly discharges through resistor R2 and NMOS tube S2, and capacitor C2 also slowly discharges through diode D2 and resistor R2. The voltage across capacitor C2 is V C2 Gradually decreases, causing the NMOS tube S main The on-resistance gradually increases, and the input current I in It should be noted that the resistance of resistor R2 is much larger than that of resistor R1, so V C2 and I in The falling speed is also slow, until the controller detects that I in in_start , immediately control the NMOS tube S2 to the cut-off state again, V C2 and I in ​​It rises again and the above state is repeated. This cycle repeats itself. When the controller's control cycle is much smaller than the time constant of the resistor R1 and the capacitor C1, the input current I in Will always be at the set value I in_start There is a slight jitter near the capacitor C1 and the capacitor C2. The voltages at both ends of the capacitor C1 and the capacitor C2 also jitter slightly, but the overall trend is linear. in Voltage across both ends V Cin Also due to the input current I in The continuous charging increases linearly, V Cin The rate of rise can be approximately calculated as follows: dV Cin / dt=I in_start / C in .

[0078] Until time t2 when the input capacitor C in The voltage across both ends reaches the input voltage V in When the input capacitor C in The voltage across both ends is stable at the input voltage V in , input current I in Then it gradually decreases to a value less than I in_start The controller controls the NMOS tube S2 to be in the cut-off state, and V C2 When it gradually rises to a certain level, the NMOS tube S main From the variable resistance area into the saturation area, at this time the NMOS tube S main Basically regarded as fully conductive, S main The on-resistance is reduced to the minimum, the conduction loss of the power-on slow start circuit is reduced to the minimum, and the power-on slow start process is completed.

[0079] From the above description, we can see that the power-on slow start time varies with the input capacitor C in The input capacitance C in The larger the capacitance, the longer the power-on slow start time, and the input capacitor C in The smaller the capacitance, the shorter the power-on slow start time; but the input current I in Will not change with the input capacitor C in The power-on slow start circuit can adapt to different input capacitances and has the advantages of high flexibility and strong adaptability.

[0080] exist Figure 1 In the illustrated solution, to achieve a discharge rate of the first discharge circuit on capacitor C1 that is lower than the charge rate of capacitor C1, and a discharge rate of the second discharge circuit on capacitor C2 that is lower than the charge rate of capacitor C2, the resistance of resistor R1 needs to be designed to be significantly lower than the resistance of resistor R2. For example, resistor R1 can be set to 10kΩ and resistor R2 can be set to 100kΩ.

[0081] In a possible implementation, the current detection circuit may use a current Hall sensor or a current sampling resistor to perform current detection.

[0082] Among them, the current Hall sensor has high precision, good linearity and electrical isolation performance. It can measure a wide range of currents and has little impact on the circuit because the measurement is performed in a non-contact manner.

[0083] The current sampling resistor is a simple and low-cost current detection method. It calculates the current by connecting a small resistor in series to the circuit and then measuring the voltage drop across the resistor. This current detection method does not require an additional power supply and is easy to integrate into the circuit.

[0084] Figure 3 Given Figure 1 The power-on slow-start circuit shown in the figure shows a compact PCB layout scheme, allowing the entire circuit to be tightly arranged on the PCB, reducing the board area and increasing the converter power density. For the specific layout scheme, see 1) to 4 below:

[0085] 1) NMOS tube S main MOSFETs in DPAK packages. The DPAK (also known as TO-252 or TO-252AA) package is a common package for medium-power and voltage applications. Its pinout includes source, gate, and drain pins, with the source and drain pins located on opposite sides of the package and the gate pin in the center. The larger package improves heat dissipation, dissipating the heat generated during the MOSFET's slow startup process in a timely manner to ensure component reliability.

[0086] 2) The rated current values ​​of NMOS transistors S1 and S2 are relatively small, so the package size and board area are also relatively small. They do not need to dissipate too much heat, so MOS transistors with smaller package sizes can be used to reduce the board area.

[0087] 3) The current flowing through diodes D1 and D2 will be limited by resistors R1 and R2, so diodes with small package sizes can also be used.

[0088] 4) The current detection circuit uses a current sampling resistor to detect current. The current sampling resistor can be easily integrated into the circuit, reducing the volume and weight of the system.

[0089] It should be noted that Figure 3 This is merely to illustrate that the embodiment of the present application can implement a board layout solution that occupies a smaller board area, and is not the only layout method.

[0090] In one possible implementation, Figure 3 The resistor R2 in the figure is changed to be connected in parallel with the capacitor C1, and the result is as follows Figure 4 The scheme shown (to simplify the drawing, Figure 4 The current detection circuit is not shown in FIG). Specifically, Figure 3 The first discharge circuit in is replaced by a resistor R2, which is connected in parallel with the capacitor C1; at the same time, Figure 3 The second discharge circuit in is replaced by a diode D2 and a resistor R2; the anode of the diode D2 is connected to the source of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1; the resistance of the resistor R1 is much smaller than that of the resistor R2. Figure 4 In the scheme shown, the resistor R2 in the first discharge circuit is reused in the second discharge circuit. Figure 4 In the illustrated solution, the resistor R2 in the first discharge circuit is reused in the second discharge circuit.

[0091] In one possible implementation, we can also let Figure 3 The capacitors C1 and C2 in the circuit are discharged using different resistors R2 and R3, respectively, to obtain the following: Figure 5 The scheme shown (to simplify the drawing, Figure 5 The current detection circuit is not shown in FIG). Specifically, Figure 3 The first discharge circuit in is replaced by a resistor R2, which is connected in parallel with the capacitor C1; at the same time, Figure 3 The second discharge circuit in is replaced by a resistor R3; the resistor R3 is connected in parallel with the capacitor C2; and the resistance of the resistor R1 is significantly smaller than the resistance of the resistor R2 and the resistor R3.

[0092] In one possible implementation, we can also let Figure 3 The capacitor C2 in the circuit is discharged by a separate resistor R3, and the result is as follows: Figure 6 The scheme shown (to simplify the drawing, Figure 6 The current detection circuit is not shown in FIG). Specifically, Figure 3 The second discharge circuit in the circuit is replaced by a resistor R3; the resistor R3 is connected in parallel with the capacitor C2; the resistance of the resistor R1 is much smaller than the resistance of the resistor R2 and the resistor R3. Figure 6 In the illustrated solution, the NMOS transistor S2 independent of the first discharge circuit is reused in the first discharge circuit.

[0093] In one possible implementation, we can also let Figure 3 Replace the diode D2 in the figure with the resistor R3, and we get Figure 7 The scheme shown (to simplify the drawing, Figure 7 The current detection circuit is not shown in FIG). Specifically, Figure 3The second discharge circuit in is replaced by a resistor R3, a resistor R2 and an NMOS transistor S2; one end of the resistor R3 is connected to the source of the NMOS transistor S1, and the other end of the resistor R3 is connected to the cathode of the diode D1; the resistance of the resistor R1 is much smaller than the resistance of the resistor R2 and the resistor R3. Figure 7 In the illustrated solution, the NMOS transistor S2 independent of the two discharge circuits is reused in the first discharge circuit and the second discharge circuit; the resistor R2 in the first discharge circuit is reused in the second discharge circuit.

[0094] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 The discharge principle of the scheme shown is the same as Figure 1 The schemes shown are the same in that: the first discharge circuit and the second discharge circuit both start to discharge the capacitors C1 and C2 respectively after the NMOS transistor S2 is turned on, which will not be described in detail herein.

[0095] In addition, an embodiment of the present application further provides a DC converter, comprising: any one of the power-on slow start circuits provided above, so as to achieve a capacitive surge current suppression effect that does not change with changes in the capacitance of the input capacitor.

[0096] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present application. Therefore, the embodiments of the present application are not limited to the embodiments shown herein, but are intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DC converter power-on slow start circuit, characterized in that: include: NMOS tube S main , NMOS transistor S1, NMOS transistor S2, capacitor C1, capacitor C2, resistor R1, diode D1, first discharge circuit, second discharge circuit, current detection circuit and controller; The drain of the NMOS transistor S1 is connected to the output end of the auxiliary power supply of the DC converter, and is connected to the anode of the diode D1 and the drain of the NMOS transistor S2 via the resistor R1; The gate of the NMOS transistor S1 is connected to the cathode of the diode D1 and one end of the capacitor C1; The source of the NMOS transistor S1 is connected to one end of the capacitor C2 and the NMOS transistor S main The gate; The NMOS tube S main The source of the capacitor C2, the other end of the capacitor C1 and the source of the NMOS transistor S2 are all connected to the negative input electrode of the DC converter; The NMOS tube S main The drain of the DC converter is connected to the input capacitor C in The low voltage end; The first discharge circuit is connected in series with the capacitor C1 and is used to discharge the capacitor C1, and the discharge rate of the first discharge circuit to the capacitor C1 is lower than the charging rate of the capacitor C1; The second discharge circuit is connected in series with the capacitor C2, and is used to discharge the capacitor C2, and its discharge rate for the capacitor C2 is lower than the charging rate of the capacitor C2; The output end of the current detection circuit is connected to the input end of the controller; the current detection circuit is used to detect the input current of the DC converter and output it to the controller; the output end of the controller is connected to the gate of the NMOS tube S2.

2. The power-on slow start circuit of the DC converter according to claim 1, characterized in that: The first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1; The second discharge circuit includes: a diode D2, the resistor R2 and the NMOS transistor S1; the anode of the diode D2 is connected to the source of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1; The resistance of the resistor R1 is smaller than the resistance of the resistor R2.

3. The power-on slow start circuit of the DC converter according to claim 2, characterized in that: The NMOS tube S main MOS tube using DPAK package.

4. The power-on slow start circuit of the DC converter according to claim 1, characterized in that: The first discharge circuit includes: a resistor R2, the resistor R2 is connected in parallel with the capacitor C1; The second discharge circuit includes: a diode D2 and a resistor R2; the anode of the diode D2 is connected to the source of the NMOS transistor S1, and the cathode of the diode D2 is connected to the cathode of the diode D1; The resistance of the resistor R1 is smaller than the resistance of the resistor R2.

5. The power-on slow start circuit of the DC converter according to claim 1, characterized in that: The first discharge circuit includes: a resistor R2, the resistor R2 is connected in parallel with the capacitor C1; The second discharge circuit includes: a resistor R3; the resistor R3 is connected in parallel with the capacitor C2; The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

6. The power-on slow start circuit of the DC converter according to claim 1, characterized in that: The first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1; The second discharge circuit includes: a resistor R3; the resistor R3 is connected in parallel with the capacitor C2; The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

7. The power-on slow start circuit of the DC converter according to claim 1, characterized in that: The first discharge circuit includes: a resistor R2 and the NMOS transistor S1; the resistor R2 is connected in parallel with the diode D1; The second discharge circuit includes: a resistor R3, a resistor R2 and an NMOS transistor S2; one end of the resistor R3 is connected to the source of the NMOS transistor S1, and the other end of the resistor R3 is connected to the cathode of the diode D1; The resistance of the resistor R1 is smaller than the resistance of the resistor R2 and the resistance of the resistor R3.

8. The power-on slow start circuit of a DC converter according to any one of claims 1 to 7, characterized in that: The current detection circuit includes a current Hall sensor or a current sampling resistor.

9. A DC converter, characterized in that: include: A power-on slow start circuit for a DC converter as claimed in any one of claims 1 to 8.

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