POR circuit compatible with low working voltage

Abstract

The utility model discloses a POR circuit compatible with low working voltage, and the circuit comprises a delay unit which is used for generating a following voltage lagging behind the change of VIO voltage in the power-on process of the VIO voltage. The delay unit comprises a first branch, a second branch and a third branch; the first branch comprises a first PMOS tube, a first NMOS tube and a second resistor which are sequentially connected in series; the second branch comprises a first resistor and a second NMOS tube which are connected in series; and the third branch comprises a second PMOS tube and a capacitor unit which are connected in series. The POR circuit of the MIPI RFFE chip is optimized, compatible work of VIO = 1.8 V and 1.2 V is achieved, effective reset signals can be normally provided under low VIO voltage, and the hard reset function is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front-end chips, and in particular to a POR circuit compatible with low operating voltage. Background Art

[0002] With the rapid development of mobile communication technology, modern mobile products such as mobile phones and mobile computers are becoming thinner and lighter. In addition to RF transceivers, these modern mobile communication devices also widely utilize RF front-end (RFFE) components such as power amplifiers, low-noise amplifiers, filters, switches, power management modules, and antenna tuners. The vast majority of these RF front-end components are controlled and their operating modes configured by a host controller via a digital bus.

[0003] In order to unify industry standards, many standardization organizations have developed communication standards suitable for mobile devices. Among them, the most eye-catching and widely used is the RF front-end control interface developed by the Mobile Industry Processor Interface (MIPI) Alliance. The MIPI RFFE interface is a simple interface for RF systems that can be integrated with a smaller number of logic devices to reduce cost investment. The MIPI RFFE interface uses three signal lines, of which SCLK is the bus clock signal line, SDATA is the bus data signal line, and VIO is the bus voltage reference / power line. This interface can achieve high-speed data transmission and is simple and easy to use. It is currently widely used in RF front-end devices in the mobile industry.

[0004] Figure 1 The internal block diagram of the MIPI control RF front-end chip is shown. The RFFE Digital Core module includes a POR (Power on reset) circuit module. The POR circuit module performs a hard reset operation on the RFFE Digital Core module during the VIO power-on period to prevent the RFFE Digital Core module from outputting erroneous signals after the VIO stabilizes.

[0005] The specific implementation is as follows Figure 2 T VIO-R Time period (corresponding to Figure 3 The POR module needs to output a low level, and the voltage at the inflection point M1 must be higher than 1V. This ensures that the RFFE Digital Core powered by VIO can operate normally, receives a reset signal of 0, which is a valid reset signal, and operates the internal circuits normally.

[0006] A POR circuit in the prior art can refer to the patent document with publication number CN109738830B. Figure 4 As shown in FIG, the POR circuit includes a current generating unit 100, a capacitor unit C1, a comparator 200 and a charge discharge unit 300; the PMOS tubes in the figure are marked with MP1 to MP7; the current generating unit 100 is used to generate an intermediate current I1 related to the size of VIO to charge the capacitor unit C1 after VIO reaches a preset voltage value (the sum of the threshold voltages of MP3 and MP4), so that the following voltage Vdelay at the circuit node B rises with a lag as VIO rises; the comparator 200 is used to compare VIO and Vdelay after VIO reaches another preset voltage (the threshold voltage of MP6), and output a 0 voltage as a valid reset signal when Vdelay is less than VIO, and output the VIO voltage when Vdelay is close to VIO; the charge discharge unit 300 is used to Figure 3 The charge stored in the capacitor unit C1 is discharged during the M5-M0 dotted line segment, so that the POR circuit can work normally when VIO is powered on next time.

[0007] As shown in Table 1, according to the MIPI protocol's VIO voltage level evolution, VIO voltages have evolved from 1.8V to 1.8V and 1.2V compatibility, meeting low-voltage and low-power requirements. Delay unit 100 requires a VIO rated operating voltage higher than the sum of the threshold voltages of MP3 and MP4 for proper operation. However, MP3 and MP4 utilize 1.8V or 2.5V PMOS transistors, each with a threshold voltage greater than 1.2V. Consequently, at VIO = 1.2V, MP4 transistors fail to conduct under certain process conditions. This malfunctions current generation unit 100 and results in a POR circuit anomaly.

[0008] Table 1VIO Supply Pin Requirements(Specification for RFFE,Version 3.0,01-Dec-2019)

[0009]

[0010] Therefore, how to design a POR circuit structure that is compatible with a lower VIO voltage and can generate an intermediate current I1 when VIO = 1.2V and 1.8V to enable the POR circuit to operate normally is an urgent problem to be solved. Summary of the Invention

[0011] In view of this, an object of the present invention is to design a circuit structure of a current generating unit that is compatible with the working states of VIO=1.2V and 1.8V and realizes the normal function of the POR circuit.

[0012] To achieve the above object, the present invention provides a POR circuit compatible with low operating voltage, comprising a delay unit, wherein the delay unit is configured to generate a follower voltage that lags behind the change of the VIO voltage during the power-on process of the VIO voltage;

[0013] The delay unit includes a first branch, a second branch and a third branch; the first to third branches are connected between the VIO terminal and the ground terminal;

[0014] The first branch includes a first PMOS transistor, a first NMOS transistor, and a second resistor connected in series in sequence, wherein the source of the first PMOS transistor is electrically connected to the VIO terminal, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, one end of the second resistor is electrically connected to the first NMOS transistor, and the other end of the second resistor is grounded;

[0015] The second branch includes a first resistor and a second NMOS transistor connected in series; the drain of the second NMOS transistor is electrically connected to the VIO terminal through the first resistor, and the source of the second NMOS transistor is grounded;

[0016] The third branch includes a second PMOS transistor and a capacitor unit connected in series; the source of the second PMOS transistor is electrically connected to the VIO terminal; one end of the capacitor unit is electrically connected to the drain of the second PMOS transistor, and the other end of the capacitor unit is grounded;

[0017] The gate of the first NMOS transistor is electrically connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is electrically connected to the source of the first NMOS transistor; the gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected to the drain of the first PMOS transistor;

[0018] The drain voltage of the second PMOS tube is the follower voltage generated by the delay unit.

[0019] Preferably, the POR circuit further includes a comparator and a charge discharge unit, wherein the comparator is electrically connected to the delay unit, and the comparator is electrically connected to the VIO terminal. The comparator is used to compare the follower voltage and the VIO voltage, and to generate a valid reset signal after the VIO terminal is powered on. The charge discharge unit is used to discharge the charge stored in the capacitor unit during the VIO voltage drop phase.

[0020] Preferably, the POR circuit further includes a fourth branch and a fifth branch, wherein the fourth branch includes a third PMOS transistor, a third NMOS transistor, and a third resistor connected in series in sequence; and the fifth branch includes a fourth PMOS transistor and a fourth NMOS transistor connected in series.

[0021] The source of the third PMOS transistor is electrically connected to the VIO terminal, the drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor, one end of the third resistor is electrically connected to the source of the third NMOS transistor, and the other end of the third resistor is grounded; the gate of the third PMOS transistor and the gate of the third NMOS transistor are electrically connected to the drain of the second PMOS transistor;

[0022] The source of the fourth PMOS tube is electrically connected to the VIO terminal; the source of the fourth NMOS tube is grounded; the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are electrically connected to the output terminal of the POR circuit; the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third PMOS tube.

[0023] Preferably, the POR circuit further includes a fifth PMOS transistor, the fifth PMOS transistor and the second PMOS transistor are connected in parallel, and a gate of the fifth PMOS transistor is electrically connected to the VIO terminal.

[0024] Preferably, the POR circuit is used for a radio frequency front-end chip whose VIO voltage is compatible with 1.8V and 1.2V.

[0025] The beneficial effects of the present invention are:

[0026] The POR circuit of the MIPIRFFE chip has been optimized to achieve compatible operation at VIO = 1.8V and 1.2V. It can normally provide an effective reset signal at a lower VIO voltage to realize the hard reset function. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a schematic diagram of the structure of the RF front-end chip that supports the MIPI protocol;

[0029] Figure 2 Schematic diagram of the transition between the VIO voltage valid state and invalid state;

[0030] Figure 3 Schematic diagram of the relationship between the reset signal reset and the VIO voltage when the VIO voltage state switches;

[0031] Figure 4 A POR circuit diagram in the prior art;

[0032] Figure 5 is a circuit diagram of a delay unit according to an embodiment of the present invention;

[0033] Figure 6 A POR circuit diagram according to an embodiment of the present invention;

[0034] Figure 7 This is a diagram showing the power-on simulation results of an embodiment of the present invention when VIO=1.2V;

[0035] Figure 8 This is a diagram of power-on simulation results of an embodiment of the present invention when VIO=1.8V. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] Figure 5 The circuit diagram of a delay unit according to an embodiment of the present invention is shown. The delay unit includes a first branch, a second branch, and a third branch. The first to third branches are respectively connected between the VIO terminal and the ground terminal. The first branch includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second resistor R2 connected in series. The source of the first PMOS transistor MP1 is electrically connected to the VIO terminal, and the drains of the first PMOS transistor MP1 and the first NMOS transistor MN1 are electrically connected. One end of the second resistor R2 is electrically connected to the source of the first NMOS transistor MN1, and the other end of the second resistor R2 is grounded. The second branch includes the first resistor R1 and the second NMOS transistor MN2 connected in series. The drain of the second NMOS transistor is electrically connected to the VIO terminal through the first resistor R1, and the source of the second NMOS transistor MN2 is grounded. The third branch includes a second PMOS transistor MP2 and a capacitor unit C1. The source of the second PMOS transistor is electrically connected to the VIO terminal, and the two ends of the capacitor unit C1 are electrically connected to the drain of the second PMOS transistor MP2 and the ground terminal, respectively. The gate of the first NMOS transistor MN1 is electrically connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor MN2 is electrically connected to the source of the first NMOS transistor; the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are electrically connected to the drain of the first PMOS transistor. The second PMOS transistor is used to mirror the current of the first PMOS transistor as the intermediate current I1 and charge the capacitor unit C1. That is, the second PMOS transistors MP2 in the first branch, the second branch, and the third branch function as the current generating unit 100, and the drain terminal voltage of the second PMOS transistor MP2 follows the voltage Vdelay.

[0038] Figure 6 The circuit diagram of the POR circuit shown here replaces the prior art delay unit with an embodiment of the present invention. In addition to the delay unit, the POR circuit further includes a fourth branch, a fifth branch, and a charge discharge unit 300. The fourth branch and the fifth branch are respectively connected between the VIO terminal and the ground terminal. The fourth branch includes a comparator 200, which includes a third PMOS transistor MP3, a third NMOS transistor MN3, and a third resistor R3 connected in series. The source of the third PMOS transistor MP3 is electrically connected to the VIO terminal, the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3 are electrically connected, one end of the third resistor R3 is electrically connected to the drain of the third NMOS transistor, the other end of the third resistor R3 is grounded, and the gates of the third PMOS transistor and the third NMOS transistor are electrically connected to the drain of the second PMOS transistor MP2. The comparator receives a follower voltage Vdelay and compares it with VIO. The fifth branch The circuit includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4 connected in series, the source of the fourth PMOS transistor is electrically connected to the VIO terminal, the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are electrically connected to the output terminal of the POR circuit, the drain of the fourth NMOS transistor is grounded, and the gates of the fourth PMOS transistor and the fourth NMOS transistor are electrically connected to the drain of the third PMOS transistor MP3. The fifth branch is used for signal shaping; the charge discharge unit 300 includes a fifth PMOS transistor MP5, the fifth PMOS transistor and the second PMOS transistor MP2 are connected in parallel, and the gate of the fifth PMOS transistor is electrically connected to the VIO terminal.

[0039] During operation, when VIO is 1.2V, the V gs The sum is V gs_MN1 +V gs_MN2 >1.2V, the second NMOS transistor MN2 cannot be turned on and is in the off state; the current of the first branch is (VIO-V gs_MN1 ) / R2, that is, when VIO>V gs_MN1 When the current flows through the first PMOS transistor MP1, the third branch generates an intermediate current I1 through the mirror, which charges the capacitor unit C1 to generate a hysteresis following voltage Vdelay. The simulation results are as follows: Figure 7 shown. Figure 7 The upper, middle, and lower (pink, green, and red) curves respectively show the time-varying relationships between the VIO voltage, the following voltage Vdelay, and the POR circuit's output signal reset during VIO power-up. As can be seen from the figure, due to the hysteresis of the following voltage Vdelay relative to the VIO signal, the POR circuit outputs a valid reset signal (reset = 0) within a short window of time after VIO power-up, implementing a hard reset.

[0040] When VIO is 1.8V, the V gs The sum is V gs_MN1 +V gs_MN2 <1.8V, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on at the same time; at this time, the current flowing through the first PMOS transistor MP1 is V gs_MN2 / R2 determines that the third branch generates an intermediate current I1 through the mirror, charging C1 to generate a hysteresis following voltage Vdelay. The simulation results are as follows Figure 8 As shown in the figure, the upper, middle, and lower (pink, green, and red) curves respectively represent the time-varying relationship between the VIO voltage, the follower voltage Vdelay, and the POR circuit output signal reset during VIO power-up. Compared to the operating condition of VIO = 1.2V, when VIO is higher, the second NMOS transistor MN2 acts as a negative feedback clamping current, thus generating sufficient delay time for judgment.

[0041] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A POR circuit compatible with low operating voltage, characterized in that: A delay unit is included, wherein the delay unit is used to generate a follow-up voltage that lags behind the change of the VIO voltage during the power-on process of the VIO voltage; The delay unit includes a first branch, a second branch and a third branch; the first to third branches are connected between the VIO terminal and the ground terminal; The first branch includes a first PMOS transistor, a first NMOS transistor, and a second resistor connected in series in sequence, wherein the source of the first PMOS transistor is electrically connected to the VIO terminal, the drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor, one end of the second resistor is electrically connected to the first NMOS transistor, and the other end of the second resistor is grounded; The second branch includes a first resistor and a second NMOS transistor connected in series; the drain of the second NMOS transistor is electrically connected to the VIO terminal through the first resistor, and the source of the second NMOS transistor is grounded; The third branch includes a second PMOS transistor and a capacitor unit connected in series; the source of the second PMOS transistor is electrically connected to the VIO terminal; one end of the capacitor unit is electrically connected to the drain of the second PMOS transistor, and the other end of the capacitor unit is grounded; The gate of the first NMOS transistor is electrically connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is electrically connected to the source of the first NMOS transistor; the gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected to the drain of the first PMOS transistor; The drain voltage of the second PMOS tube is the follower voltage generated by the delay unit.

2. The POR circuit according to claim 1, wherein: It also includes a comparator and a charge discharge unit. The comparator is electrically connected to the delay unit, and the comparator is electrically connected to the VIO terminal. The comparator is used to compare the follower voltage and the VIO voltage, and generate a valid reset signal after the VIO terminal is powered on. The charge discharge unit is used to discharge the charge stored in the capacitor unit during the VIO voltage drop stage.

3. The POR circuit according to claim 1, wherein: The circuit further includes a fourth branch and a fifth branch, wherein the fourth branch includes a third PMOS transistor, a third NMOS transistor, and a third resistor connected in series in sequence; and the fifth branch includes a fourth PMOS transistor and a fourth NMOS transistor connected in series; The source of the third PMOS transistor is electrically connected to the VIO terminal, the drain of the third PMOS transistor is electrically connected to the drain of the third NMOS transistor, one end of the third resistor is electrically connected to the source of the third NMOS transistor, and the other end of the third resistor is grounded; the gate of the third PMOS transistor and the gate of the third NMOS transistor are electrically connected to the drain of the second PMOS transistor; The source of the fourth PMOS tube is electrically connected to the VIO terminal; the source of the fourth NMOS tube is grounded; the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are electrically connected to the output terminal of the POR circuit; the gate of the fourth PMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third PMOS tube.

4. The POR circuit according to claim 3, wherein: The device further includes a fifth PMOS transistor, which is connected in parallel with the second PMOS transistor, and a gate of the fifth PMOS transistor is electrically connected to the VIO terminal.

5. The POR circuit according to claim 1, wherein: The POR circuit is used for RF front-end chips whose VIO voltage is compatible with 1.8V and 1.2V.

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