High-speed scanning direction-finding intermediate frequency processor scanning device

Abstract

The utility model provides a scanning device for a high-speed scanning direction-finding intermediate frequency processor, which relates to the technical field of intermediate frequency processors, and comprises a board card as a bottom plate and consists of an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and an ADC (Analog to Digital Converter) framework. The utility model discloses a high-speed scanning direction-finding intermediate frequency processor, and aims to solve the defects of high hardware configuration cost, low scanning direction-finding efficiency and high occupied time cost in a radio direction-finding system.

Description

Technical Field

[0001] The present invention relates to the technical field of intermediate frequency processors, and in particular to a high-speed scanning and direction-finding intermediate frequency processor scanning device. Background Art

[0002] A radio direction-finding system generally consists of a front-end receiving antenna array, a radio frequency receiver, an intermediate frequency (IF) processor, and a back-end display and control terminal computer. The IF processor, which connects the entire system, is one of the core components of the system.

[0003] The mainstream architecture of today's IF processors is FPGA + DSP + A / D, and most implement scanning direction finding using a correlation interferometer system. Currently, the primary scanning direction finding method employed by radio direction finding systems is this: the IF processor controls the front-end antenna array and RF receiver to collect signal data within a single frequency bandwidth. This data is pre-processed by the IF processor before being uploaded to the display and control terminal computer, which then performs a complex correlation interferometer algorithm and displays the direction finding results. The terminal computer then issues a command to switch to the next frequency to collect data, perform calculations, and display the direction finding results.

[0004] The existing method of using a display and control terminal computer to control frequency switching and perform related interferometer direction finding calculations can no longer meet the current demand for high speed and large bandwidth for spectrum radio monitoring and direction finding. It has two major drawbacks:

[0005] First, it relies on the display and control terminal computer to perform complex direction-finding calculations, which places high demands on computer performance and results in extremely high hardware configuration costs.

[0006] Secondly, the efficiency of scanning and direction finding by switching frequencies through the display and control terminal computer is extremely low, and the command exchange between the display and control terminal computer and the intermediate frequency processor will take a lot of time. Utility Model Content

[0007] In view of the above-mentioned deficiencies in the prior art, the present invention provides a high-speed scanning direction finding intermediate frequency processor scanning device which solves the problems of high hardware configuration cost, low scanning direction finding efficiency and high time cost in radio direction finding system.

[0008] In order to achieve the above-mentioned purpose of the utility model, the technical solution adopted by the utility model is: a high-speed scanning direction finding intermediate frequency processor scanning device, which uses a board as a baseboard and is composed of an FPGA, a DSP and an ADC framework.

[0009] The beneficial effects of this utility model include: A high-speed scanning direction-finding IF processor is designed to address the shortcomings of high hardware configuration costs, low scanning efficiency, and high time consumption in radio direction-finding systems. By utilizing a state-of-the-art FPGA and an eight-core DSP with a main frequency of up to 1.2 GHz as core components, scanning efficiency is significantly improved. Frequency switching during scanning direction-finding and implementation of the related interferometer direction-finding algorithm are both implemented on this IF processor, reducing computer performance requirements. Direction-finding results are directly output to the display and control terminal computer software, reducing interaction time between the computer and the IF processor.

[0010] Furthermore, the FPGA is connected to the ADCs of five analog-to-digital conversion chips, and the DSP is connected to the FPGA via SRIO and EMIF buses.

[0011] Furthermore, the FPGA is externally connected to DDR3 and FLASH, and the DSP is externally connected to DDR3 and FLASH, the DDR3 storage unit is 2GB, and the FLASH storage unit is 32MB.

[0012] Furthermore, the DSP is connected to a Gigabit network port for external communication;

[0013] The FPGA is externally connected to RS422, RS232, and SPI low-speed interfaces for external communication.

[0014] Furthermore, the FPGA controls the ADC chip to collect signal data, and the FPGA sends the direction finding result to the DSP via a high-speed SRIO interface.

[0015] Furthermore, it also includes a first high-speed ADC chip, a second high-speed ADC chip, a crystal oscillator, a high-precision clock chip AD9156-3 clock, a third high-speed ADC chip, a fourth high-speed ADC chip, a fifth high-speed ADC chip, an FPGA chip XC7VX690T-2FFG1761, a J303 interface, a first FLASH chip SPIFLASH-32MB, a first memory DDR3X4-4GB, a DSP chip TMS320C6678, a second FLASH chip NOFLASH-32MB, a second memory DDR3X4-4GB, a first network PHY chip 88e6131, a second network PHY chip 88e1512, a J63A debug port and an ASACC interface;

[0016] Among them, the reserved data is connected to one end of the first high-speed ADC chip through channels 7 and 8, and the reserved data is connected to one end of the second high-speed ADC chip through channels 9 and 10. The crystal oscillator is connected to the first port of the high-precision clock chip AD9156-3 clock. The second port of the high-precision clock chip AD9156-3 clock is connected to the other end of the first high-speed ADC chip, the other end of the second high-speed ADC chip, one end of the third high-speed ADC chip, one end of the fourth high-speed ADC chip and one end of the fifth high-speed ADC chip. The third port of the high-precision clock chip AD9156-3 clock is connected to one end of the FPGA chip XC7VX690T-2FFG1761. The other end of the FPGA chip XC7VX690T-2FFG1761 is respectively connected to one end of the J303 interface, one end of the first FLASH chip SPIFLASH-32MB, one end of the first memory DDR3X4-4GB and one end of the DSP chip TMS320C6678. The other end of the P chip TMS320C6678 is respectively connected to one end of the second FLASH chip NOFLASH-32MB, one end of the second network PHY chip 88e1512, one end of the second memory DDR3X4-4GB and one end of the first network PHY chip 88e6131. ​​The other end of the second network PHY chip 88e1512 is connected to the RJ45 interface. The J63A debug port is respectively connected to the other end of the FPGA chip XC7VX690T-2FFG1761 and the other end of the DSP chip TMS320C6678. The other end of the third high-speed ADC chip, the other end of the fourth high-speed ADC chip and the other end of the fifth high-speed ADC chip, the other end of the FPGA chip XC7VX690T-2FFG1761, the other end of the DSP chip TMS320C6678, the other end of the first network PHY chip 88e6131 and the other end of the second network PHY chip 88e1512 are respectively connected to the ASACC interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] This specification will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, like numbers represent like structures, wherein:

[0018] Figure 1 This is an exemplary schematic diagram of the principle of a high-speed scanning direction finding intermediate frequency processor scanning device according to some embodiments of this specification;

[0019] Figure 2 This is an exemplary schematic diagram of a high-speed scanning direction finding intermediate frequency processor scanning device according to some embodiments of this specification. DETAILED DESCRIPTION

[0020] The specific implementation methods of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific implementation methods. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all utility model creations using the concept of the present invention are protected.

[0021] Example

[0022] In some embodiments, as Figure 2 As shown, a high-speed scanning direction finding intermediate frequency processor scanning device uses a board as a baseboard and is composed of an FPGA, DSP, and ADC framework.

[0023] In some embodiments, as Figure 1 As shown, the high-speed scanning direction finding intermediate frequency processor scanning device may include a first high-speed ADC chip, a second high-speed ADC chip, a third high-speed ADC chip, a fourth high-speed ADC chip, a fifth high-speed ADC chip, a crystal oscillator, a high-precision clock chip, an FPGA chip, a DSP chip, a first network PHY chip, a first FLASH chip, a first memory, a second FLASH chip, a second network PHY chip, a second memory, an ASACC interface, a J303 interface, an RJ45 interface and a J63A debug port.

[0024] In some embodiments, the reserved data is connected to one end of the first high-speed ADC chip through channels 7 and 8, the reserved data is connected to one end of the second high-speed ADC chip through channels 9 and 10, the crystal oscillator is connected to the first port of the high-precision clock chip AD9156-3 clock, the second port of the high-precision clock chip AD9156-3 clock is connected to the other end of the first high-speed ADC chip, the other end of the second high-speed ADC chip, one end of the third high-speed ADC chip, one end of the fourth high-speed ADC chip and one end of the fifth high-speed ADC chip, the third port of the high-precision clock chip AD9156-3 clock is connected to one end of the FPGA chip XC7VX690T-2FFG1761, and the other end of the FPGA chip XC7VX690T-2FFG1761 is respectively connected to one end of the J303 interface, one end of the first FLASH chip SPIFLASH-32MB, one end of the first memory DDR3X4-4GB and one end of the DSP chip TMS320C6678. The other end of the DSP chip TMS320C6678 is respectively connected to one end of the second FLASH chip NOFLASH-32MB, one end of the second network PHY chip 88e1512, one end of the second memory DDR3X4-4GB and one end of the first network PHY chip 88e6131. ​​The other end of the second network PHY chip 88e1512 is connected to the RJ45 interface. The J63A debug port is respectively connected to the other end of the FPGA chip XC7VX690T-2FFG1761 and the other end of the DSP chip TMS320C6678. The other end of the third high-speed ADC chip, the other end of the fourth high-speed ADC chip and the other end of the fifth high-speed ADC chip, the other end of the FPGA chip XC7VX690T-2FFG1761, the other end of the DSP chip TMS320C6678, the other end of the first network PHY chip 88e6131 and the other end of the second network PHY chip 88e1512 are respectively connected to the ASACC interface.

[0025] In some embodiments, the high-speed scanning direction finding intermediate frequency processor scanning device may use a 3U standard board with FPGA, DSP, and ADC as the framework, including FPGA and TMS320C6678 core components.

[0026] In some embodiments, the FPGA is connected to the ADCs of five analog-to-digital conversion chips, and the DSP is connected to the FPGA via SRIO and EMIF buses.

[0027] In some embodiments, the FPGA is connected to the ADCs of five analog-to-digital conversion chips, and the DSP is connected to the FPGA via SRIO and EMIF buses.

[0028] In some embodiments, the FPGA has external DDR3 and FLASH, the DSP has external DDR3 and FLASH, the DDR3 storage unit is 2GB, and the FLASH storage unit is 32MB.

[0029] In some embodiments, the DSP is connected to a gigabit network port for external communication, which is used to exchange command data with the display and control terminal computer; the FPGA is connected to an RS422, RS232, or SPI low-speed interface for external communication, which is used to communicate with the front-end receiver.

[0030] In some embodiments, the DSP is connected to a Gigabit Ethernet port for external communication, which can be used to exchange command data with a display and control terminal computer.

[0031] In some embodiments, the FPGA controls the ADC chip to collect signal data, the FPGA sends the direction finding results to the DSP through the high-speed SRIO interface, and the DSP controls the FPGA to perform various functional operations through the EMIF bus.

[0032] In some embodiments, a full-band calibration instruction is sent to the intermediate frequency processor, and the intermediate frequency processor performs full-band calibration after receiving the instruction; after receiving the instruction and parameters, the DSP in the intermediate frequency processor calculates and converts the parameters, and transmits the converted instructions, parameters, and phase difference library to the FPGA; the FPGA of the intermediate frequency processor receives the scanning direction finding instruction and parameters, controls the configuration of the receiver, collects the multi-channel intermediate frequency signals output by the receiver, and performs analog-to-digital conversion; the FPGA obtains the digital signal, performs preprocessing such as frequency conversion, calculates the spectrum of each channel, calculates the direction finding of the related interferometer, and obtains the azimuth and amplitude of the signal; the FPGA autonomously switches the configuration of the receiver to the next frequency point according to the scanning direction finding instruction, performs direction finding calculation as described in S3, and outputs the result to the DSP; the DSP of the intermediate frequency processor receives the direction finding azimuth and amplitude returned by the FPGA.

[0033] In some embodiments, ADC specifications may have the following requirements:

[0034] The chip has no less than 9 channels;

[0035] The recommended ADC model is ADS42LB69;

[0036] Maximum sampling rate: 250Msps;

[0037] Signal intermediate frequency: 153.6MHz / 140MHz;

[0038] Signal bandwidth: 80MHz;

[0039] Resolution: 16 bits;

[0040] Support standard frequency clock input (standard frequency amplitude ≥ 3dBm);

[0041] Analog signal interface: SMP-JHD.

[0042] In some embodiments, the high-speed scanning direction finding intermediate frequency processor can achieve the following indicators:

[0043] Frequency resolution: ≤25KHz;

[0044] Maximum scanning direction finding speed: ≥100GHz / s;

[0045] Instantaneous dynamic range: ≥165dB;

[0046] Measurement dynamic range: ≥1110dB;

[0047] IF suppression: ≥180dB;

[0048] Direction finding accuracy: ≤1.5° (fixed frequency signal), ≤3° (pulse signal);

[0049] Direction finding sensitivity: ≤20dBμV / m;

[0050] Direction finding time: ≤100us;

[0051] Maximum instantaneous receiving bandwidth: 80MHz;

[0052] IF frequency: 153.6MHz.

[0053] This utility model addresses the shortcomings of high hardware configuration costs, low scanning and direction-finding efficiency, and high time consumption in radio direction-finding systems through a high-speed scanning and direction-finding IF processor. Utilizing a state-of-the-art FPGA and an eight-core DSP with a clock speed of up to 1.2GHz as its core components, scanning efficiency is significantly improved. Frequency switching during scanning and direction-finding, as well as the implementation of the relevant interferometer direction-finding algorithm, are all implemented on this IF processor, reducing computer performance requirements. Direction-finding results are directly output to the display and control terminal software, reducing interaction time between the computer and the IF processor.

[0054] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements are intended to fall within the scope of the present invention. The scope of protection claimed in this invention is defined by the appended claims and their equivalents.

Claims

1. A high-speed scanning direction finding intermediate frequency processor scanning device, characterized in that: The board is used as the baseboard, which consists of FPGA, DSP and ADC framework; wherein the FPGA is connected to the ADC of 5 analog-to-digital conversion chips, and the DSP is connected to the FPGA through SRIO and EMIF buses; The FPGA is plugged into DDR3 and FLASH, and the DSP is plugged into DDR3 and FLASH. The DDR3 storage unit is 2GB, and the FLASH storage unit is 32MB. The DSP is connected to a Gigabit Ethernet port for external communication; The FPGA is connected to an external RS422, RS232, or SPI low-speed interface for external communication; The FPGA controls the ADC chip to collect signal data, and the FPGA sends the direction finding results to the DSP via a high-speed SRIO interface; It also includes: a first high-speed ADC chip, a second high-speed ADC chip, a crystal oscillator, a high-precision clock chip AD9156-3, a third high-speed ADC chip, a fourth high-speed ADC chip, a fifth high-speed ADC chip, an FPGA chip XC7VX690T-2FFG1761, a J303 interface, a first FLASH chip SPIFLASH-32MB, a first memory DDR3X4-4GB, a DSP chip TMS320C6678, a second FLASH chip NOFLASH-32MB, a second memory DDR3X4-4GB, a first network PHY chip 88e6131, a second network PHY chip 88e1512, a J63A debug port, and an ASACC interface; Among them, the reserved data is connected to one end of the first high-speed ADC chip through channels 7 and 8, and the reserved data is connected to one end of the second high-speed ADC chip through channels 9 and 10. The crystal oscillator is connected to the first port of the high-precision clock chip AD9156-3 clock. The second port of the high-precision clock chip AD9156-3 clock is connected to the other end of the first high-speed ADC chip, the other end of the second high-speed ADC chip, one end of the third high-speed ADC chip, one end of the fourth high-speed ADC chip and one end of the fifth high-speed ADC chip. The third port of the high-precision clock chip AD9156-3 clock is connected to one end of the FPGA chip XC7VX690T-2FFG1761. The other end of the FPGA chip XC7VX690T-2FFG1761 is respectively connected to one end of the J303 interface, one end of the first FLASH chip SPIFLASH-32MB, one end of the first memory DDR3X4-4GB and one end of the DSP chip TMS320C6678. The other end of the P chip TMS320C6678 is respectively connected to one end of the second FLASH chip NOFLASH-32MB, one end of the second network PHY chip 88e1512, one end of the second memory DDR3X4-4GB and one end of the first network PHY chip 88e6131. ​​The other end of the second network PHY chip 88e1512 is connected to the RJ45 interface. The J63A debug port is respectively connected to the other end of the FPGA chip XC7VX690T-2FFG1761 and the other end of the DSP chip TMS320C6678. The other end of the third high-speed ADC chip, the other end of the fourth high-speed ADC chip and the other end of the fifth high-speed ADC chip, the other end of the FPGA chip XC7VX690T-2FFG1761, the other end of the DSP chip TMS320C6678, the other end of the first network PHY chip 88e6131 and the other end of the second network PHY chip 88e1512 are respectively connected to the ASACC interface.

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