Multi-channel broadband receiver

Abstract

The invention discloses a multichannel broadband receiver, and belongs to the technical field of microwave radio frequency and electronic control, the multichannel broadband receiver comprises a multichannel down-conversion assembly, a local oscillator power component, a power interface control panel and a VPX connector, the down-conversion assembly adopts a cavity-divided integrated structure, multiple identical radio frequency links are arranged in the same cavity in parallel, and the VPX connector is connected with the local oscillator power component. Down conversion from a 2-18GHz radio frequency signal to a 1.3-2.3 GHz intermediate frequency signal is realized through two-stage frequency mixing; the power supply interface control board takes an FPGA as a core, integrates the functions of multi-path power supply conversion, driving isolation, state monitoring and the like, and realizes channel gain power failure storage and calling, BIT self-inspection, nanosecond rapid turn-off and multi-parameter real-time monitoring through software and hardware cooperation. Through collaborative innovation of the structure, circuit and control, high integration, high channel consistency, high isolation and high intelligence of the multi-channel receiver are realized, and the multi-channel receiver is suitable for the fields of high-performance radars, electronic countermeasures and the like.

Description

Technical Field

[0001] This invention relates to the field of microwave radio frequency and electronic control technology, and in particular to a multi-channel broadband receiver. Background Technology

[0002] Multichannel broadband receivers are core components in modern radar, electronic reconnaissance, and communication systems, and their performance directly affects the system's detection range, resolution, and anti-jamming capabilities. Traditional broadband receivers mostly employ single-channel or few-channel designs, making it difficult to meet the requirements of modern systems for multi-target detection, high precision, and high consistency.

[0003] In existing technologies, multi-channel receivers often face the following problems: 1. Conflict between integration and isolation: Traditional solutions simply stack multiple single-channel modules, resulting in bulky and heavy equipment, severe electromagnetic crosstalk between channels, and difficulty in ensuring isolation (usually below 50dB), which affects the performance of multi-target detection. 2. Performance consistency issues: Due to differences in component tolerances, wiring variations, and uneven heat distribution, the gain and phase consistency between multiple channels are poor (amplitude consistency is often better than ±2dB, and phase consistency is better than ±100°), making it difficult to meet the requirements of applications such as accurate direction finding and DBF. 3. Insufficient intelligent control: Existing VPX power supplies and control boards are mostly feature-packed, lacking system-level intelligent collaboration. The control logic is rigid, heavily reliant on the host computer for micro-management, and cannot achieve advanced functions such as gain memory, fast protection, and automatic diagnosis. The system response is slow and reliability is low. 4. Poor environmental adaptability: Under harsh environments such as high temperature, vibration, and shock, the performance of traditional designs deteriorates significantly, the heat dissipation path is not optimal, and there is a lack of effective condition monitoring and protection mechanisms.

[0004] Therefore, there is an urgent need in this field for a multi-channel broadband receiver solution that integrates high-density integration, high performance indicators, highly intelligent control, and high environmental adaptability. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems existing in the prior art and to provide a multi-channel broadband receiver.

[0006] The objective of this invention is achieved through the following technical solution: A multi-channel broadband receiver, comprising: A multi-channel downconversion assembly is used to convert multiple input radio frequency signals to intermediate frequency. It includes a cavity and multiple frequency conversion channels with identical structures disposed in the cavity. The multiple frequency conversion channels are arranged in parallel in the cavity, and each frequency conversion channel is physically separated by an independent metal partition wall to form a cavity structure. The local oscillator power distribution component is used to provide the local oscillator signal to the down-conversion component; The power interface control board includes a system interface unit and an FPGA system unit. An SPI communication unit, a power module, and a level conversion unit are connected between the system interface unit and the FPGA system unit. A status monitoring module is connected to the FPGA system unit, including a voltage and current detection unit, a temperature detection unit, a bit status detection unit, and a frequency synthesizer lockout indication detection unit. The FPGA system includes a main control chip and peripheral circuits, including a clock circuit, a configuration circuit, and a reset circuit. The FPGA system unit is connected to the voltage and current detection unit via an MCU. The main control chip is also connected to the multi-channel down-converter component via a drive isolation unit. The power interface control board is connected to the local oscillator power distribution component. The VPX connector is connected to the multi-channel downconverter assembly, the local oscillator power distribution assembly, and the power interface control board, respectively.

[0007] In some embodiments, the radio frequency link of the frequency conversion channel includes, in sequence, a limiting protection unit, a pre-selection switching filter bank, a low-noise amplification unit, a two-stage mixer, a digitally controlled attenuation unit, an intermediate frequency (IF) switching filter bank, and an IF coupler; wherein, the pre-selection switching filter bank includes filters covering different radio frequency bands and a first single-pole multi-throw (SPMD) switch, the first SPMD switch being connected to the filters covering different radio frequency bands respectively; the IF filter bank includes filters covering different IF frequency bands and a second SPMD switch, the second SPMD switch being connected to the filters covering different IF frequency bands respectively.

[0008] In some embodiments, the limiting protection unit includes a limiter and an amplifying pass-through chip connected in sequence. The input terminal of the limiter receives an radio frequency signal, and the output terminal of the amplifying pass-through chip is connected to the input terminal of the preselected switching filter group. The two-stage mixing unit includes a first mixer, a filtering amplification unit, and a second mixer connected in sequence. The local oscillator power distribution component includes a variable local oscillator signal input unit connected to the first mixer and a fixed local oscillator signal input unit connected to the second mixer. The low-noise amplification unit includes a first low-noise amplifier, a first low-pass filter, an equalizer, and a first attenuator connected in sequence; the filtering amplification unit includes a first band-pass filter, a second low-noise amplifier, a second band-pass filter, and a second attenuator connected in sequence; the digitally controlled attenuation unit includes a third band-pass filter, a third attenuator, a third low-noise amplifier, a fourth attenuator, a temperature compensator, a fifth attenuator, and a fourth low-noise amplifier connected in sequence; the variable local oscillator signal input unit includes a frequency multiplier, a fourth band-pass filter, a fifth low-noise amplifier, and a second low-pass filter connected in sequence.

[0009] In some embodiments, the frequency conversion channel further includes a BIT self-test unit, which includes a detector.

[0010] In some embodiments, a software control system running on a power interface control board is also included. The software control system includes a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown design: The FPGA asynchronously monitors and processes the full shutdown signal. Upon receiving the shutdown signal, it cuts off the RF channel within less than 50ns.

[0011] In some embodiments, the main control chip is model XC6SLX25-2CSG324I, the clock circuit includes a clock chip, model BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; and the reset circuit includes a pull-up resistor.

[0012] In some embodiments, the drive isolation unit includes a drive isolation chip, wherein the drive isolation chip is of model number SN74LVCH16T245DGGR.

[0013] In some embodiments, the voltage and current detection unit includes a voltage and current detection chip, the model of which is ISL28022; the temperature detection unit includes a temperature sensor, the model of which is DS18B20; the level conversion unit includes a level conversion chip, the model of which is 74VHC245MTC; the BIT status detection unit includes an amplifier and a comparator connected in sequence, the model of which is AD8313 and the model of which is TL331IDBVR; the power supply module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

[0014] In some embodiments, during the collaborative status monitoring, the MCU reads register address 0x02 of the ISL28022 chip to obtain the voltage value and reads register address 0x01 to obtain the current value.

[0015] In some embodiments, the software control system is also used to implement self-test diagnosis: after receiving a self-test command, the FPGA controls the radio frequency module to inject a self-test signal, and synchronously analyzes the BIT status signal of all channels, automatically determines the faulty channel, and packages and reports the results.

[0016] It should be further noted that the technical features corresponding to the above options can be combined or substituted to form new technical solutions if there is no conflict.

[0017] Compared with the prior art, the beneficial effects of the present invention are: 1. System-level integration and performance leap: By integrating the cavity-type downconverter component, intelligent VPX control board and local oscillator power distribution component into a single design, comprehensive optimization from RF link and power management to digital control is achieved. The system has high integration, small size and light weight (≤2kg), while key RF indicators (such as isolation ≥55dB, amplitude consistency ≤±1.5dB) are significantly better than traditional designs.

[0018] 2. Intelligent Closed-Loop Control and Management: A complete control closed loop of "state perception - intelligent decision-making - rapid execution - parameter memory" is constructed. The system has advanced functions such as gain power-down preservation, self-test diagnosis, and rapid shutdown (<100ns), realizing a qualitative change from "passive execution" to "active management", and greatly improving the system's automation level, reliability, and maintainability.

[0019] 3. Excellent multi-channel consistency: The downconverter components adopt the same link layout and cavity isolation structure, combined with high-precision digital control attenuation and temperature compensation, to ensure excellent amplitude consistency (≤±1.5dB) and phase stability (differential stability better than ±2°) among the 10 channels, laying a solid foundation for high-performance array processing.

[0020] 4. Strong environmental adaptability and reliability: The VPX control board integrates comprehensive status monitoring (voltage, current, temperature, BIT) and a high-efficiency hybrid power architecture. Combined with the optimized heat dissipation and reinforced structure of the downconverter components, the system can operate stably in harsh environments (such as -50℃ to +85℃).

[0021] 5. High efficiency of deep hardware and software integration: Fully leveraging the parallel processing capabilities of FPGA, it achieves parallel execution of multiple tasks (status monitoring, instruction parsing, and rapid shutdown), resulting in fast system response and high resource utilization. The same hardware platform can be adapted to various functional requirements through software definition, offering strong versatility and convenient expansion. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a multi-channel broadband receiver according to the present invention; Figure 2 This is a schematic diagram of the structure of a downconversion component for a multi-channel broadband receiver according to the present invention; Figure 3 This is a schematic diagram of the signal processing flow of the frequency conversion channel of the present invention; Figure 4 This is a schematic diagram of the frequency conversion channel of the present invention; Figure 5 This is a schematic diagram of the preselection switching filter bank of the present invention; Figure 6 This is a schematic diagram of the intermediate frequency switching filter bank of the present invention; Figure 7 This is a schematic diagram of the mixing process of the two-stage mixing unit of the present invention; Figure 8 This is a schematic diagram of the structure of a VPX power interface control board according to the present invention; Figure 9 This is a schematic diagram of the FPGA system unit of the present invention; Figure 10 This is a schematic diagram of the LDO voltage regulator circuit of the present invention; Figure 11 This is a schematic diagram of the FPGA system clock of the present invention; Figure 12 This is a schematic diagram of the Spartan-6 FPGA SPI configuration circuit of the present invention; Figure 13 This is a schematic diagram of the reset circuit of the present invention; Figure 14 This is a schematic diagram of the driving isolation unit of the present invention; Figure 15 This is a schematic diagram of the voltage and current detection circuit of the present invention; Figure 16 This is a schematic diagram of the temperature detection circuit of the present invention; Figure 17 This is a schematic diagram of the level conversion circuit of the present invention; Figure 18 This is a schematic diagram of the BIT status detection circuit of the present invention; Figure 19 This is a topology diagram of the power module of the present invention; Figure 20 This is a schematic diagram of the surge protection and EMI filtering circuit of the present invention; Figure 21 This is a schematic diagram of the conversion circuits at each stage of the present invention; Figure 22 This is a functional diagram of the software control system of the present invention; Figure 23 This is a schematic diagram of the SPI write timing of the present invention; Figure 24 This is a schematic diagram of the SPI read timing of the present invention; Figure 25 This is a schematic diagram of the external appearance of the multi-channel broadband receiver of the present invention.

[0023] In the diagram: 1-cavity; 2-frequency conversion channel. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0026] In view of the technical problems pointed out in the background art, the present invention provides the following embodiments: In one exemplary embodiment, a multi-channel broadband receiver is provided, such as Figure 1-2 As shown, it includes: A multi-channel downconversion assembly is used to convert multiple input radio frequency signals to intermediate frequency. It includes a cavity 1 and multiple frequency conversion channels 2 with identical structures disposed in the cavity. The multiple frequency conversion channels 2 are arranged in parallel in the cavity 1, and each frequency conversion channel 2 is physically separated by an independent metal partition wall to form a cavity structure. The local oscillator power distribution component is used to provide the local oscillator signal to the down-conversion component; The power interface control board is used to complete the data exchange between the RF module and the system, and realize functions such as RF module interface control, status detection feedback and query, hardware status storage and recording, online program debugging and updating; The VPX connector is connected to the multi-channel downconverter assembly, the local oscillator power distribution assembly, and the power interface control board, respectively.

[0027] The RF link is designed using bare chips, with each channel designed using a separate cavity to improve isolation between channels and reduce the size of the internal circuit cavity. This reduces RF crosstalk and allows for the removal of excess cavity space, thus achieving weight reduction. The cavity is made of rust-resistant aluminum 6063 (LD31).

[0028] Specifically, the signal processing flow of frequency converter channel 2 is as follows: Figure 3 As shown, the 2GHz–18GHz radio frequency signal is processed through limiting, amplification pass-through selection, filtering, amplification, frequency conversion, digitally controlled attenuation, and bandwidth selection to output an intermediate frequency signal of 1.3GHz–2.3GHz. Taking a 10-channel example, the 10-channel frequency conversion component mainly realizes the down-conversion of 10 channels of 2–18GHz radio frequency signals to output three selectable intermediate frequency signals with bandwidths of 1800MHz±500MHz, 1800MHz±200MHz, and 1800MHz±25MHz.

[0029] Preferably, the limiting protection unit includes a limiter and an amplifying pass-through chip connected in sequence. The input terminal of the limiter receives an RF signal, and the output terminal of the amplifying pass-through chip is connected to the input terminal of the preselected switching filter group. The two-stage mixing unit includes a first mixer (MWM007), a filtering amplification unit, and a second mixer (MWM2000A) connected in sequence. The local oscillator power divider includes a variable local oscillator signal input unit connected to the first mixer and a fixed local oscillator signal input unit connected to the second mixer.

[0030] The low-noise amplification unit includes a first low-noise amplifier (MWL0071), a first low-pass filter (TFL18-9B), an equalizer (HGC131-4), and a first attenuator (HGC191-305) connected in sequence. The filtering amplification unit includes a first bandpass filter (HGC177-22B), a second low-noise amplifier (HGC448), a second bandpass filter (HGC177-22B), and a second attenuator (HGC191-305) connected in sequence. The digitally controlled attenuation unit includes a third bandpass filter (DLF1800R1000), a third attenuator (HGC219), a third low-noise amplifier (HGC301-10A), a fourth attenuator (HGC219), a temperature compensator (STCA0604N9W3219), a fifth attenuator, and a fourth low-noise amplifier (TQPL9092) connected in sequence.

[0031] The variable local oscillator signal input unit includes a frequency multiplier, a fourth bandpass filter, a fifth low-noise amplifier, and a second low-pass filter connected in sequence.

[0032] Based on the above structural design, a specific circuit structure for a frequency conversion channel is given, such as... Figure 4 As shown.

[0033] In this embodiment, both the third and fourth attenuators are digitally controlled attenuators.

[0034] In some examples, the frequency converter channel also includes a BIT self-test unit, which includes a detector. When a self-test signal is input, it automatically collects and detects the signals of each channel according to the self-test command and outputs an LVTTL level. The signals of 10 channels (≥-15dBm) are continuously output as high, and the signals of 10 channels (≤-18dBm) are continuously output as low. At the same time, the status of 10 channels is reported through SPI.

[0035] In some examples, the first single-pole multi-throw switch is an SPI switching switch.

[0036] Furthermore, the structure of the preselected switching filter bank is as follows: Figure 5 As shown, the downconversion is achieved by dividing the 2~18GHz RF signal input into 7 frequency bands through the selection of a pre-selected switching filter bank. The pre-selected switching filter bank adopts SPI switching control, and the filter bank frequency band overlap is ≥1000MHz.

[0037] Furthermore, the local oscillator power divider primarily functions to input the amplified local oscillator signal, after frequency multiplication, into the frequency converter with equal amplitude and phase, providing the local oscillator signal for the frequency converter's frequency conversion. The mixing relationship of the two-stage mixing unit is as follows: Figure 7As shown. A variable local oscillator signal of 12~20GHz is amplified by frequency multiplication and mixed with the RF input signal to generate a narrowband signal of 21.5~22.5GHz. The signal is then filtered by a two-stage bandpass filter to suppress the local oscillator signal and other intermodulation signals. A fixed local oscillator signal of 11.9GHz is amplified by frequency multiplication and mixed with the RF input signal to generate a narrowband signal of 1.3~2.3GHz. The signal is filtered by a first-stage chip filter to remove high-frequency signals and by a second-stage LTCC bandpass filter to remove low-frequency signals, thus meeting the module's intermediate frequency output requirements.

[0038] The intermediate frequency (IF) link is designed with a switching filter bank (3-bandwidth filters), which can achieve bandwidth selection of 1800MHz±500MHz, 1800MHz±200MHz, and 1800MHz±25MHz. The structure of the IF switching filter bank is as follows: Figure 6 As shown. The intermediate frequency switching filter bank adopts a joint control method, and the requirements for the filters in each frequency band are as follows: 1.1800±500MHz: ≥40dBc@DC~1100MHz&2500~6000MHz; 2.1800±200MHz: ≥40dBc@DC~1300MHz&2300~6000MHz; 3.1800±25MHz: ≥40dBc@DC~1600MHz&2000~6000MHz; The switch filter bank can achieve the function of full shutdown. The switch model is HMC7992.

[0039] Furthermore, the numerically controlled attenuation unit is designed with two stages of numerically controlled attenuation, with a step size of 0.5dB, used for gain calibration and system operation respectively. Simultaneously, a temperature compensator compensates for performance drift caused by temperature variations, ensuring performance stability across the entire temperature range.

[0040] For example, such as Figure 8 As shown, the control board includes a system interface unit and an FPGA system unit. An SPI communication unit, a power supply module, and a level conversion unit are respectively connected between the system interface unit and the FPGA system unit. A status monitoring module is connected to the FPGA system unit, and the status monitoring module includes a voltage and current detection unit, a temperature detection unit, a bit status detection unit, and a frequency synthesizer lockout indication detection unit. Figure 9 As shown, the FPGA system includes a main control chip and peripheral circuits. The peripheral circuits include a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external downconversion component through a drive isolation unit. The FPGA system unit is connected to the voltage and current detection unit through an MCU. The software control system includes a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown design: The FPGA asynchronously monitors and processes the full shutdown signal, and cuts off the RF channel within a threshold time after receiving the shutdown signal.

[0041] In this embodiment, the main control chip is model XC6SLX25-2CSG324I. The chip requires a core voltage of 1.2V and a port voltage of 3.3V to operate. The operating voltage of the FPGA main control chip and the FLASH configuration chip can be generated by using a +5V input voltage regulated by an LDO and then further regulated by an LT1963AMPS8 regulator. The LDO regulator circuit design is as follows... Figure 10 As shown.

[0042] The clock circuit includes a clock chip, model BT0503BH3I106BN40, which introduces a 40MHz clock to the global clock pin of the FPGA. The FPGA system clock schematic is shown below. Figure 11 As shown.

[0043] The configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; the FPGA chip XC6SLX25-2CSG324I is connected to the FLASH chip M25P16-VMN6 via Master Serial / SPI mode. The Spartan-6 FPGA SPI configuration circuit is as follows: Figure 12 As shown.

[0044] The reset circuit includes a pull-up resistor. The FPGA system reset uses a 4.7K pull-up resistor connected to the FPGA's PROGRAM_B_2 pin, such as... Figure 13 As shown.

[0045] The driver isolation unit primarily serves to isolate and enhance the driving capability between the FPGA chip and the RF module interface. The switching control signals and attenuation control signals required by the RF module are generated by the FPGA and sent to the RF module after passing through this unit to complete the corresponding control functions. The driver isolation unit includes a driver isolation chip, specifically the SN74LVCH16T245DGGR. The schematic design of the driver isolation unit is shown below. Figure 14 As shown.

[0046] In this embodiment, the voltage and current detection unit is implemented through an MCU coprocessor unit. This MCU coprocessor unit acts as a "coprocessor" for the FPGA, focusing on analog data acquisition, freeing up FPGA resources. It packages and sends the acquired data to the FPGA via a UART serial port (115200 baud rate). Specifically, the voltage and current detection unit includes a voltage and current detection chip, model ISL28022, which uses I2C for data communication with the MCU. The voltage and current acquisition circuit is as follows... Figure 15 As shown.

[0047] The temperature detection unit includes a temperature sensor, model DS18B20. The temperature resolution is selectable from 9 to 12 bits; at the highest 12-bit accuracy, the temperature conversion speed is less than 400ms, and the measurement range is -55℃ to +125℃. Data exchange is performed via a single bus. The temperature detection circuit is as follows: Figure 16 As shown.

[0048] The level conversion unit includes a level conversion chip, specifically a 74VHC245MTC. The single-ended SPI is converted to LVTTL level by the 74VHC245MTC before being connected to the FPGA. The typical transmission delay of the 74VHC245MTC is 4ns. The level conversion circuit for the single-ended SPI is as follows: Figure 17 As shown.

[0049] The BIT status detection unit includes an amplifier and a comparator connected in sequence. The amplifier is an AD8313, and the comparator is a TL331IDBVR. The BIT self-test function is implemented by detecting the output signal. The detection point is placed at the last stage of the RF link, enabling detection of the entire RF link. The detected level of the output signal is compared and then fed into the FPGA. The system is fed back via serial port after detecting all bits in the channel. The BIT status detection circuit is as follows: Figure 18 As shown.

[0050] Furthermore, such as Figure 19As shown, the power supply module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence. The +12V supplied by the system is converted to +5.5V by the first-stage DC / DC converter, then to a negative voltage by the second-stage DC / DC converter, and finally converted to the operating voltage required by each functional circuit by the LDO linear regulator, thus powering each functional circuit unit. The surge protection and EMI filtering circuits are as follows... Figure 20 As shown in the diagram above, the power supplies for the electrical modules are all designed with enable functionality. When the power enable is floating, the module's internal pull-up switch keeps the power supply module on; when the power enable is low, the module's EN switch is pulled low, and the module's power supply is off. The conversion circuits at each stage are as follows: Figure 21 As shown in the diagram. +5V powers the frequency conversion channel and the local oscillator amplifier; -5V powers devices requiring negative voltage (such as microwave switches, temperature compensators, digitally controlled attenuators, and switching filter banks); and +3.3V powers the digital processing unit (such as detection circuits and FPGAs).

[0051] Furthermore, the module's power input does not employ large-capacity capacitor filtering to ensure that the inrush current does not exceed twice the module's rated current. During any instantaneous inrush current event, the input current can recover to the specified steady-state limit within 10ms. The module's 12V power input ground is isolated from the module's internal ground and is not connected to the module's casing. A TVS diode is designed at the voltage input terminal to effectively prevent inrush current.

[0052] Furthermore, software control systems such as Figure 22 As shown, the FPGA software consists of a clock reset subfunction, an SPI communication subfunction, a serial communication subfunction, a temperature acquisition subfunction, and an RF switch control subfunction. The SPI communication uses a four-wire 32-bit serial data transmission, with bit 31 output first and bit 0 output last. SPI_CS is the SPI serial port chip select control bit, SPI_CLK is the communication synchronization clock bit, SPI_MOSI is the master data output module data input, and SPI_MISO is the master data input module data output (Note: the slave starts outputting data on the rising edge of SPI_CLK, and the master samples data on the falling edge of SPI_CLK). The SPI write timing is as follows... Figure 23 As shown. The SPI read timing is as follows. Figure 24 As shown. SPI communication functions include SPI data parsing and data latching. The temperature sensor uses a single bus for communication, periodically acquiring temperature information. The FPGA serial communication primarily communicates with the MCU, receiving voltage and current information acquired by the MCU, with a baud rate of 115200.

[0053] The MCU exchanges data with the voltage and current sensing chip ISL28022 via I2C. Based on the register addresses of the ISL28022 chip, voltage and current values ​​are read periodically. The register address corresponding to the voltage value is 0x02, and the register address corresponding to the current value is 0x01. The MCU's serial communication primarily transmits the acquired voltage and current information to the FPGA at a baud rate of 115200, using timed transmission.

[0054] Furthermore, the BIT self-test function is implemented by detecting the output signal, with the detection point placed at the last stage of the RF link, enabling detection of the entire RF link. The detected level of the output signal is compared and then fed into the FPGA. The system is then fed back via serial port after detecting all bits in the channel.

[0055] Furthermore, the control status query uses SPI timing to read the data corresponding to the SPI register address and send it back to the system. Specifically, the FPGA detects the LVTTL level of each channel status indicator, where logic 0 indicates a channel status fault and logic 1 indicates a normal channel status. The result of ANDing each channel status indicator represents the BIT status indicator. The FPGA also periodically detects the LVTTL level of each PLL lock indicator, where logic 0 indicates a PLL unlock and logic 1 indicates a PLL lock.

[0056] Furthermore, when the FPGA receives the channel attenuation value, it controls the intermediate frequency attenuation while saving the attenuation value, for example, by saving it to the AT24C128 memory. When powered on, it reads the data in the AT24C128 memory to initialize the intermediate frequency attenuation; thus realizing the requirements of power-off saving and retrieval of intermediate frequency attenuation.

[0057] Furthermore, the software control system is also used to implement self-testing and diagnosis: after receiving a self-testing command, the FPGA controls the radio frequency module to inject a self-testing signal, and synchronously analyzes the BIT status signals of all channels, automatically determines the faulty channel, and packages and reports the results.

[0058] Furthermore, the LVTTL level of the fully off discrete line is first connected to the FPGA via a level conversion unit to control the RF switch. The LVTTL level conversion unit takes approximately 4ns. After being connected to the FPGA, it first performs a two-step process before controlling the RF switch according to the control logic. The FPGA processing time is approximately 50ns.

[0059] In this embodiment, the module hardware interface consists of a VPX connector and a JTAG program debugging port. The VPX connector is a hybrid connector of VPX-61T8aDD8BADD8-A, and it comprises one basic module, one single-ended module, one differential module, and four RF modules. The node functions and quantities of each module are shown in Table 1. Table 1 VPX Node Function Table The JTAG port uses the AVIC Optoelectronics model J30JS-15ZKP low-frequency connector, and the connector housing is made of stainless steel passivation.

[0060] Furthermore, the receiver adopts a modular, standardized, and serialized design approach to ensure product testability, manufacturability, and maintainability. While meeting design requirements, weight reduction and vibration damping designs are incorporated as much as possible. The module consists of a frequency converter assembly, a local oscillator assembly, and a VPX power control board, and its external structure is as follows... Figure 25 As shown.

[0061] Furthermore, by attaching the high-power components of the receiver to cavity 1, the heat conduction path is shortened, which is beneficial for heat dissipation of high-power components and achieves a rapid heat dissipation effect. In practice, the heat dissipation design can be realized by constructing a model of a multi-channel broadband receiver in SW software and performing finite element thermal simulation analysis.

[0062] Furthermore, the receiver's channel switching is achieved through the switching of the intermediate frequency (IF) switching filter bank. The shutdown control is a single LVTTL level control signal; a high-level signal fully opens the channel, and a low-level signal fully closes it. By cascading two stages of switches, the required switching isolation of ≥70dBc can be achieved. The series connection time between the two stages is ≤40ns. Considering the digital processing delay and the 40ns channel delay, the final switching time is ≤80ns.

[0063] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A multi-channel broadband receiver, characterized in that, include: A multi-channel downconversion assembly is used to convert multiple input radio frequency signals to intermediate frequency. It includes a cavity and multiple frequency conversion channels with identical structures disposed in the cavity. The multiple frequency conversion channels are arranged in parallel in the cavity, and each frequency conversion channel is physically separated by an independent metal partition wall to form a cavity structure. The local oscillator power distribution component is used to provide the local oscillator signal to the down-conversion component; The power interface control board includes a system interface unit and an FPGA system unit. An SPI communication unit, a power module, and a level conversion unit are connected between the system interface unit and the FPGA system unit. A status monitoring module is connected to the FPGA system unit, including a voltage and current detection unit, a temperature detection unit, a bit status detection unit, and a frequency synthesizer lockout indication detection unit. The FPGA system includes a main control chip and peripheral circuits, including a clock circuit, a configuration circuit, and a reset circuit. The FPGA system unit is connected to the voltage and current detection unit via an MCU. The main control chip is also connected to the multi-channel down-converter component via a drive isolation unit. The power interface control board is connected to the local oscillator power distribution component. The VPX connector is connected to the multi-channel downconverter assembly, the local oscillator power distribution assembly, and the power interface control board, respectively.

2. The multi-channel broadband receiver according to claim 1, characterized in that, The radio frequency link of the frequency conversion channel includes, in sequence, a limiting protection unit, a pre-selection switch filter group, a low-noise amplification unit, a two-stage mixer, a digitally controlled attenuation unit, an intermediate frequency switch filter group, and an intermediate frequency coupler; wherein, the pre-selection switch filter group includes filters covering different radio frequency bands and a first single-pole multi-throw switch, the first single-pole multi-throw switch being connected to the filters covering different radio frequency bands respectively; the intermediate frequency filter group includes filters covering different intermediate frequency bands and a second single-pole multi-throw switch, the second single-pole multi-throw switch being connected to the filters covering different intermediate frequency bands respectively.

3. A multi-channel broadband receiver according to claim 1, characterized in that, The limiting protection unit includes a limiter and an amplifying pass-through chip connected in sequence. The input terminal of the limiter receives an RF signal, and the output terminal of the amplifying pass-through chip is connected to the input terminal of the preselected switch filter group. The two-stage mixing unit includes a first mixer, a filtering amplification unit, and a second mixer connected in sequence. The local oscillator power divider includes a variable local oscillator signal input unit connected to the first mixer and a fixed local oscillator signal input unit connected to the second mixer. The low-noise amplification unit includes a first low-noise amplifier, a first low-pass filter, an equalizer, and a first attenuator connected in sequence; the filtering amplification unit includes a first band-pass filter, a second low-noise amplifier, a second band-pass filter, and a second attenuator connected in sequence; the digitally controlled attenuation unit includes a third band-pass filter, a third attenuator, a third low-noise amplifier, a fourth attenuator, a temperature compensator, a fifth attenuator, and a fourth low-noise amplifier connected in sequence; the variable local oscillator signal input unit includes a frequency multiplier, a fourth band-pass filter, a fifth low-noise amplifier, and a second low-pass filter connected in sequence.

4. A multi-channel broadband receiver according to claim 1, characterized in that, The frequency conversion channel also includes a BIT self-test unit, which includes a detector.

5. A multi-channel broadband receiver according to claim 1, characterized in that, It also includes a software control system running on the power interface control board, the software control system comprising a program stored in a storage medium, which, when executed, performs the following: Collaborative status monitoring: The MCU periodically reads voltage and current data and sends it to the FPGA system unit via UART; simultaneously, the FPGA system unit periodically reads temperature data; the FPGA system unit also monitors the BIT status signal from the RF module in real time. Intelligent instruction processing: The FPGA system unit receives and parses the host computer instructions through the SPI communication unit, and autonomously generates the corresponding control sequence according to the instruction type. It then controls the gain, filter bandwidth, and channel switching of the RF module through the drive isolation unit. Control status query: The FPGA system unit detects the lock indication level of each phase-locked loop in the radio frequency module through the frequency synthesizer lock indication detection unit; Channel gain power-down saving and retrieval: The FPGA saves the gain of the RF channel after power-down according to the control command; and automatically reads the value when the system is powered on to initialize the RF module; Full shutdown design: The FPGA asynchronously monitors and processes the full shutdown signal. Upon receiving the shutdown signal, it cuts off the RF channel within less than 50ns.

6. A multi-channel broadband receiver according to claim 1, characterized in that, The main control chip is model XC6SLX25-2CSG324I; the clock circuit includes a clock chip, model BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; and the reset circuit includes pull-up resistors.

7. A multi-channel broadband receiver according to claim 1, characterized in that, The drive isolation unit includes a drive isolation chip, the model of which is SN74LVCH16T245DGGR.

8. A multi-channel broadband receiver according to claim 1, characterized in that, The voltage and current detection unit includes a voltage and current detection chip, model ISL28022; the temperature detection unit includes a temperature sensor, model DS18B20; the level conversion unit includes a level conversion chip, model 74VHC245MTC; the BIT status detection unit includes an amplifier and a comparator connected in sequence, model AD8313 for the amplifier and model TL331IDBVR for the comparator; the power module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

9. A multi-channel broadband receiver according to claim 5, characterized in that, In the collaborative status monitoring, the MCU reads register address 0x02 of the ISL28022 chip to obtain the voltage value and reads register address 0x01 to obtain the current value.

10. A multi-channel broadband receiver according to claim 5, characterized in that, The software control system is also used to realize self-test diagnosis: after receiving the self-test command, the FPGA controls the radio frequency module to inject the self-test signal, and synchronously analyzes the BIT status signal of all channels, automatically determines the faulty channel, and packages and reports the results.

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