Aging test board compatible with multiple interfaces

Abstract

The utility model discloses an aging test board compatible with multiple interfaces. The aging test board compatible with multiple interfaces comprises a test device and a plurality of test interface units arranged on the test device at intervals. The test interface unit comprises a circuit board, a 7 + 15P male head connector, a 7 + 15P female seat connector, an M.2 female seat connector, an mSATA female seat connector, a first SATA channel switching chip, a second SATA channel switching chip and a DC3.3 V circuit chip. According to the utility model, the 7 + 15P female seat connector, the M.2 female seat connector and the mSATA female seat connector are integrated on the circuit board, a multi-interface compatible connection mode is realized, channel switching is carried out through the first SATA channel switching chip and the second SATA channel switching chip, one of multiple interfaces can be selected during testing, and the testing efficiency is improved. Therefore, aging tests can be carried out on solid state disks of different specifications, and the method has good applicability.

Description

Technical Field

[0001] The utility model relates to the technical field of testing equipment, in particular to an aging test board compatible with multiple interfaces. Background Art

[0002] The BIT (Burn in Test) test is a burn-in test for solid-state drives (SSDs). The SSD is connected to test equipment and continuously writes and reads data for an extended period of time to test its stability and application compatibility. SATA (Serial ATA) is a computer bus primarily used for data transmission between SSDs and devices. It gets its name from its serial data transmission method and offers the advantages of a simple structure and hot-swappable support.

[0003] SATA protocol solid-state drives have many physical interfaces, such as 7+15P interface, Mini PCIe (mSATA) interface, M.2 interface, Mini SATA interface, 7P interface, etc. Among them, 7+15P interface, Mini PCIe (mSATA) interface and M.2 interface are mainstream interfaces. During production testing, they are incompatible due to different physical interfaces.

[0004] Therefore, there is an urgent need for an aging test board that is compatible with multiple interfaces. Utility Model Content

[0005] In view of the above problems, the present invention is proposed to provide a multi-interface compatible aging test board that overcomes the above problems or at least partially solves the above problems.

[0006] The utility model provides a multi-interface compatible aging test board, which comprises a test device and a plurality of test interface units spaced apart on the test device;

[0007] The test interface unit includes a circuit board, a 7+15P male connector, a 7+15P female connector, an M.2 female connector, an mSATA female connector, a first SATA channel switching chip, a second SATA channel switching chip, and a DC3.3V circuit chip, wherein the 7+15P male connector is installed at the lower end of the circuit board, and the 7+15P female connector, the M.2 female connector, the mSATA female connector, the first SATA channel switching chip, the second SATA channel switching chip, and the DC3.3V circuit chip are installed at the upper end of the circuit board;

[0008] The 7+15P male connector is electrically connected to the test equipment, the first SATA channel switch chip is electrically connected to the 7+15P male connector, the 7+15P female connector and the second SATA channel switch chip respectively; the M.2 female connector is electrically connected to the second SATA channel switch chip and the DC3.3V circuit chip respectively; the mSATA female connector is electrically connected to the second SATA channel switch chip and the DC3.3V circuit chip respectively; the 7+15P male connector, the 7+15P female connector, the first SATA channel switch chip and the DC3.3V circuit chip are all connected to a DC5V power supply.

[0009] Optionally, the test interface unit is screwed onto the test device by fastening screws.

[0010] Optionally, the product model of the first SATA channel switching chip is ASW3410, the first SATA channel switching chip includes 19 groups of pins, and the 7+15P male connector includes 22 groups of pins; pin 17 of the first SATA channel switching chip is connected to a DC5V power supply, pin 2 of the first SATA channel switching chip is connected to pin 2 of the 7+15P male connector, pin 1 of the first SATA channel switching chip is connected to pin 3 of the 7+15P male connector, pin 4 of the first SATA channel switching chip is connected to pin 5 of the 7+15P male connector, and pin 5 of the first SATA channel switching chip is connected to pin 6 of the 7+15P male connector; pins 14-16 of the 7+15P male connector are connected to a DC5V power supply.

[0011] Optionally, the 7+15P female connector includes 22 groups of pins, pin 13 of the first SATA channel switching chip is connected to pin 2 of the 7+15P female connector, pin 14 of the first SATA channel switching chip is connected to pin 3 of the 7+15P female connector, pin 9 of the first SATA channel switching chip is connected to pin 5 of the 7+15P female connector, pin 8 of the first SATA channel switching chip is connected to pin 6 of the 7+15P female connector, and pin 6 of the first SATA channel switching chip is connected to pin 16 of the 7+15P female connector; pins 14-15 of the 7+15P female connector are connected to a DC5V power supply.

[0012] Optionally, the product model of the second SATA channel switching chip is ASW3410, and the second SATA channel switching chip includes 19 groups of pins, wherein pin 4 of the second SATA channel switching chip is connected to pin 11 of the first SATA channel switching chip, pin 5 of the second SATA channel switching chip is connected to pin 10 of the first SATA channel switching chip, pin 1 of the second SATA channel switching chip is connected to pin 16 of the first SATA channel switching chip, and pin 2 of the second SATA channel switching chip is connected to pin 15 of the first SATA channel switching chip.

[0013] Optionally, the M.2 female connector includes 77 groups of pins, pin 10 of the second SATA channel switching chip is connected to pin 41 of the M.2 female connector, pin 11 of the second SATA channel switching chip is connected to pin 43 of the M.2 female connector, pin 47 of the second SATA channel switching chip is connected to pin 16 of the M.2 female connector, and pin 49 of the second SATA channel switching chip is connected to pin 15 of the M.2 female connector; pin 2, pin 4, pin 70, pin 72 and pin 74 of the M.2 female connector are respectively connected to the DC3.3V circuit chip.

[0014] Optionally, the mSATA female connector includes 52 groups of pins, pin 8 of the second SATA channel switching chip is connected to pin 23 of the mSATA female connector, pin 9 of the second SATA channel switching chip is connected to pin 25 of the mSATA female connector, pin 14 of the second SATA channel switching chip is connected to pin 31 of the mSATA female connector, and pin 13 of the second SATA channel switching chip is connected to pin 33 of the mSATA female connector; pin 6 of the second SATA channel switching chip is connected to pin 52 of the mSATA female connector; pin 2, pin 24, pin 39, and pin 41 of the mSATA female connector are respectively connected to the DC3.3V circuit chip.

[0015] Optionally, the product model of the DC3.3V circuit chip is MT3035, and the DC3.3V circuit chip includes 10 groups of pins, wherein pins 8-10 of the DC3.3V circuit chip are connected to a DC5V power supply, and pins 1-3 of the DC3.3V circuit chip are respectively connected to the M.2 female connector and the mSATA female connector to provide stepped-down DC3.3V.

[0016] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0017] The multi-interface compatible aging test board described in the embodiment of the present utility model realizes a multi-interface compatible connection mode by integrating a 7+15P female connector, an M.2 female connector, and an mSATA female connector on the circuit board. At the same time, channel switching is performed through the first SATA channel switching chip and the second SATA channel switching chip. During the test, multiple interfaces can be selected, so that aging tests can be performed on solid-state drives of different specifications, and the board has better applicability.

[0018] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a side view of the multi-interface compatible aging test board of the present invention;

[0021] Figure 2 This is a top view of the multi-interface compatible aging test board of the present invention;

[0022] Figure 3 This is a schematic diagram of the circuit principle of the multi-interface compatible aging test board of the utility model;

[0023] Figure 4 This is the circuit reference diagram of the 7+15P male connector;

[0024] Figure 5 This is a circuit reference diagram of the first SATA channel switching chip;

[0025] Figure 6 This is the circuit reference diagram of the 7+15P female connector;

[0026] Figure 7 This is a circuit reference diagram of the second SATA channel switching chip;

[0027] Figure 8 This is a circuit reference diagram for the M.2 female connector;

[0028] Figure 9 This is a circuit reference diagram of the mSATA female connector;

[0029] Figure 10 This is a circuit reference diagram for the DC3.3V circuit chip.

[0030] Description of reference numerals:

[0031] 10. Test equipment; 20. Test interface unit; 21. Circuit board; 22. Fastening screws; J1, 7+15P male connector; J2, 7+15P female connector; J3, M.2 female connector; J4, mSATA female connector; U1, first SATA channel switching chip; U2, second SATA channel switching chip; U3, DC3.3V circuit chip. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings.

[0033] In order to enable those skilled in the art to better understand the present invention, the following will be combined with the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. The accompanying drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0034] Unless otherwise specified, various raw materials, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0035] Figure 1 This is a structural diagram of a multi-interface compatible aging test board provided by an embodiment of the present utility model. Figure 2 This is a top view of the multi-interface compatible aging test board of the present invention. Figure 3 This is a schematic diagram of the circuit principle of the multi-interface compatible aging test board of the utility model, see Figure 1-3As shown, the multi-interface compatible aging test board includes a test device 10 and a plurality of test interface units 20 spaced apart on the test device 10; the test interface unit 20 includes a circuit board 21, a 7+15P male connector J1, a 7+15P female connector J2, an M.2 female connector J3, an mSATA female connector J4, a first SATA channel switching chip U1, a second SATA channel switching chip U2, and a DC3.3V circuit chip U3, wherein the 7+15P male connector J1 is mounted at the lower end of the circuit board 21, The 7+15P female connector J2, M.2 female connector J3, mSATA female connector J4, first SATA channel switch chip U1, second SATA channel switch chip U2 and DC3.3V circuit chip U3 are installed on the upper end of the circuit board 21; the 7+15P male connector J1 is electrically connected to the test equipment 10, and the first SATA channel switch chip U1 is electrically connected to the 7+15P male connector J1, 7+15P female connector J2 and second SATA channel switch chip U2 respectively; the M.2 The female connector J3 is electrically connected to the second SATA channel switch chip U2 and the DC3.3V circuit chip U3 respectively; the mSATA female connector J4 is electrically connected to the second SATA channel switch chip U2 and the DC3.3V circuit chip U3 respectively; the 7+15P male connector J1, the 7+15P female connector J2, the first SATA channel switch chip U1 and the DC3.3V circuit chip U3 are all connected to the DC5V power supply; the circuit board 21 is used to provide physical support and provide power for the active devices installed thereon. Power supply signal transmission channel; the 7+15P male connector J1, 7+15P female connector J2, M.2 female connector J3 and mSATA female connector J4 respectively provide interface functions; the first SATA channel switching chip U1 and the second SATA channel switching chip U2 respectively provide channel switching functions; the DC3.3V circuit chip U3 is used to provide a step-down function, for example, stepping down the DC5V power supply to DC3.3V, and supplying the stepped-down power supply DC3.3V to the M.2 female connector J3 and the mSATA female connector J4.

[0036] In an embodiment of the present utility model, the test interface unit 20 is screwed onto the test device 10 by a fastening screw 22; the test interface unit 20 can be connected to solid-state hard drives of various interface specifications, and the test device 10 is a conventional test device-end integrated cabinet, which is used to perform aging tests on solid-state hard drives of various interface specifications loaded on the test interface unit 20 and collect test data.

[0037] Figure 4This is the circuit reference diagram of the 7+15P male connector J1. Figure 5 This is a circuit reference diagram of the first SATA channel switching chip U1. Figure 6 This is the circuit reference diagram of the 7+15P female connector J2, see Figure 4-6 As shown, the 7+15P male connector J1 and the 7+15P female connector J2 are conventional 7P+15P SATA modules, the 7+15P male connector J1 includes 22 groups of pins, and the 7+15P female connector J2 includes 22 groups of pins; the product model of the first SATA channel switch chip U1 is ASW3410, the first SATA channel switch chip U1 includes 19 groups of pins, pin 17 of the first SATA channel switch chip U1 is connected to a DC5V power supply, pin 2 of the first SATA channel switch chip U1 is connected to pin 2 of the 7+15P male connector J1, pin 1 of the first SATA channel switch chip U1 is connected to pin 3 of the 7+15P male connector J1, pin 4 of the first SATA channel switch chip U1 is connected to pin 5 of the 7+15P male connector J1, and pin 5 of the first SATA channel switch chip U1 is connected to the 7+ Pin 6 of the 15P male connector J1; pins 14-16 of the 7+15P male connector J1 are connected to a DC5V power supply; pin 13 of the first SATA channel switching chip U1 is connected to pin 2 of the 7+15P female connector J2, pin 14 of the first SATA channel switching chip U1 is connected to pin 3 of the 7+15P female connector J2, pin 9 of the first SATA channel switching chip U1 is connected to pin 5 of the 7+15P female connector J2, pin 8 of the first SATA channel switching chip U1 is connected to pin 6 of the 7+15P female connector J2, and pin 6 of the first SATA channel switching chip U1 is connected to pin 16 of the 7+15P female connector J2; pins 14-15 of the 7+15P female connector J2 are connected to a DC5V power supply.

[0038] Specifically, the 7+15P male connector J1 is located in the center of the bottom of the circuit board 21, passes through the data cable hole of the test equipment 10, and is used to connect the test equipment 10. The 7+15P male connector J1 controls the switching channel through the first SATA channel switching chip U1, where SEL (pin 6 of the first SATA channel switching chip U1) is pulled low, channel 1 is connected to the second SATA channel switching chip U2. When the 7+15P female connector J2 is connected to the solid-state hard drive, the SEL of pin 6 of the first SATA channel switching chip U1 is pulled high, channel 1 is disconnected, switched to channel 2, and connected to the 7+15P female connector J2. The DC5V of the 7+15P male connector J1 is directly connected to the 7+15P female connector J2, LED1 is on, and the 7+15P female connector J2 and its solid-state hard drive are connected for testing.

[0039] Figure 7 This is a circuit reference diagram of the second SATA channel switching chip U2. Figure 8 This is the circuit reference diagram of the M.2 female connector J3. Figure 9 This is the circuit reference diagram of the mSATA female connector J4, combined with Figure 7-9 As shown, the product model of the second SATA channel switching chip U2 is ASW3410, and the second SATA channel switching chip U2 includes 19 groups of pins, among which pin 4 of the second SATA channel switching chip U2 is connected to pin 11 of the first SATA channel switching chip U1, pin 5 of the second SATA channel switching chip U2 is connected to pin 10 of the first SATA channel switching chip U1, pin 1 of the second SATA channel switching chip U2 is connected to pin 16 of the first SATA channel switching chip U1, and pin 2 of the second SATA channel switching chip U2 is connected to pin 15 of the first SATA channel switching chip U1.

[0040] The M.2 female connector J3 is a conventional M.2 interface connector. The M.2 female connector J3 includes 77 groups of pins. Pin 10 of the second SATA channel switching chip U2 is connected to pin 41 of the M.2 female connector J3, pin 11 of the second SATA channel switching chip U2 is connected to pin 43 of the M.2 female connector J3, pin 47 of the second SATA channel switching chip U2 is connected to pin 16 of the M.2 female connector J3, and pin 49 of the second SATA channel switching chip U2 is connected to pin 15 of the M.2 female connector J3; pin 2, pin 4, pin 70, pin 72 and pin 74 of the M.2 female connector J3 are respectively connected to the DC3.3V circuit chip U3.

[0041] The mSATA female connector J4 is a conventional mSATA interface connector. The mSATA female connector J4 includes 52 groups of pins. Pin 8 of the second SATA channel switching chip U2 is connected to pin 23 of the mSATA female connector J4, pin 9 of the second SATA channel switching chip U2 is connected to pin 25 of the mSATA female connector J4, pin 14 of the second SATA channel switching chip U2 is connected to pin 31 of the mSATA female connector J4, and pin 13 of the second SATA channel switching chip U2 is connected to pin 33 of the mSATA female connector J4; pin 6 of the second SATA channel switching chip U2 is connected to pin 52 of the mSATA female connector J4; pin 2, pin 24, pin 39, and pin 41 of the mSATA female connector J4 are respectively connected to the DC3.3V circuit chip U3.

[0042] Specifically, the M.2 female connector J3, the mSATA female connector J4, and the 7+15P female connector J2 are distributed together on the front of the circuit board 21 to provide corresponding interface functions. When the 7+15P female connector J2 is not connected to a solid-state drive, the SEL (pin 6) of the first SATA channel switching chip U1 is pulled low, and channel 1 is connected to the second SATA channel switching chip U2. When the SEL (pin 6) of the second SATA channel switching chip U2 is pulled low, channel 1 is connected to the M.2 female connector J3, and LED2 is on. When the mSATA female connector J4 is connected to a solid-state drive, the SEL (pin 6) of the second SATA channel switching chip U2 is pulled high, channel 1 is connected to the mSATA female connector J4, and LED3 is on.

[0043] Figure 10 This is a circuit reference diagram of the DC3.3V circuit chip U3. The product model of the DC3.3V circuit chip U3 is MT3035. The DC3.3V circuit chip U3 includes 10 groups of pins, wherein pins 8-10 of the DC3.3V circuit chip U3 are connected to a DC5V power supply, and pins 1-3 of the DC3.3V circuit chip U3 are respectively connected to the M.2 female connector J3 and the mSATA female connector J4 to provide stepped-down DC3.3V.

[0044] It should be noted that, in the embodiment of the present invention, the 7+15P male connector J1, the 7+15P female connector J2, the M.2 female connector J3, the mSATA female connector J4, the first SATA channel switch chip U1, the second SATA channel switch chip U2 and the DC3.3V circuit chip U3 also include auxiliary components, such as filter capacitors (C1, etc.), resistors (R23, etc.), diodes (LED1, etc.), etc., combined with Figure 4-10 As shown, it can be selected according to actual needs, and the present invention has no restrictions on this.

[0045] The multi-interface compatible aging test board described in the embodiment of the present invention realizes a multi-interface compatible connection mode by integrating a 7+15P female connector J2, an M.2 female connector J3, and an mSATA female connector J4 on the circuit board 21. At the same time, channel switching is performed through the first SATA channel switching chip U1 and the second SATA channel switching chip U2. During the test, multiple interfaces can be selected, so that aging tests can be performed on solid-state drives of different specifications, and the board has better applicability.

[0046] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0047] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various invention aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims, the invention aspects lie in less than all of the features of the individual embodiments previously disclosed. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0048] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A multi-interface compatible aging test board, characterized in that: The multi-interface compatible aging test board comprises: a test device and a plurality of test interface units spaced apart on the test device; The test interface unit includes a circuit board, a 7+15P male connector, a 7+15P female connector, an M.2 female connector, an mSATA female connector, a first SATA channel switching chip, a second SATA channel switching chip, and a DC3.3V circuit chip, wherein the 7+15P male connector is installed at the lower end of the circuit board, and the 7+15P female connector, the M.2 female connector, the mSATA female connector, the first SATA channel switching chip, the second SATA channel switching chip, and the DC3.3V circuit chip are installed at the upper end of the circuit board; The 7+15P male connector is electrically connected to the test equipment, the first SATA channel switch chip is electrically connected to the 7+15P male connector, the 7+15P female connector and the second SATA channel switch chip respectively; the M.2 female connector is electrically connected to the second SATA channel switch chip and the DC3.3V circuit chip respectively; the mSATA female connector is electrically connected to the second SATA channel switch chip and the DC3.3V circuit chip respectively; the 7+15P male connector, the 7+15P female connector, the first SATA channel switch chip and the DC3.3V circuit chip are all connected to a DC5V power supply.

2. The multi-interface compatible aging test board according to claim 1, characterized in that: The test interface unit is screwed onto the test device by fastening screws.

3. The multi-interface compatible aging test board according to claim 1, characterized in that: The product model of the first SATA channel switching chip is ASW3410. The first SATA channel switching chip includes 19 groups of pins, and the 7+15P male connector includes 22 groups of pins. Pin 17 of the first SATA channel switching chip is connected to a DC5V power supply, pin 2 of the first SATA channel switching chip is connected to pin 2 of the 7+15P male connector, pin 1 of the first SATA channel switching chip is connected to pin 3 of the 7+15P male connector, pin 4 of the first SATA channel switching chip is connected to pin 5 of the 7+15P male connector, and pin 5 of the first SATA channel switching chip is connected to pin 6 of the 7+15P male connector. Pins 14-16 of the 7+15P male connector are connected to a DC5V power supply.

4. The multi-interface compatible aging test board according to claim 3, characterized in that: The 7+15P female connector includes 22 groups of pins, pin 13 of the first SATA channel switching chip is connected to pin 2 of the 7+15P female connector, pin 14 of the first SATA channel switching chip is connected to pin 3 of the 7+15P female connector, pin 9 of the first SATA channel switching chip is connected to pin 5 of the 7+15P female connector, pin 8 of the first SATA channel switching chip is connected to pin 6 of the 7+15P female connector, and pin 6 of the first SATA channel switching chip is connected to pin 16 of the 7+15P female connector; pins 14-15 of the 7+15P female connector are connected to a DC5V power supply.

5. The multi-interface compatible aging test board according to claim 4, characterized in that: The product model of the second SATA channel switching chip is ASW3410. The second SATA channel switching chip includes 19 groups of pins, among which pin 4 of the second SATA channel switching chip is connected to pin 11 of the first SATA channel switching chip, pin 5 of the second SATA channel switching chip is connected to pin 10 of the first SATA channel switching chip, pin 1 of the second SATA channel switching chip is connected to pin 16 of the first SATA channel switching chip, and pin 2 of the second SATA channel switching chip is connected to pin 15 of the first SATA channel switching chip.

6. The multi-interface compatible aging test board according to claim 5, characterized in that: The M.2 female connector includes 77 groups of pins, pin 10 of the second SATA channel switching chip is connected to pin 41 of the M.2 female connector, pin 11 of the second SATA channel switching chip is connected to pin 43 of the M.2 female connector, pin 47 of the second SATA channel switching chip is connected to pin 16 of the M.2 female connector, and pin 49 of the second SATA channel switching chip is connected to pin 15 of the M.2 female connector; pin 2, pin 4, pin 70, pin 72 and pin 74 of the M.2 female connector are respectively connected to the DC3.3V circuit chip.

7. The multi-interface compatible aging test board according to claim 6, characterized in that: The mSATA female connector includes 52 groups of pins, pin 8 of the second SATA channel switching chip is connected to pin 23 of the mSATA female connector, pin 9 of the second SATA channel switching chip is connected to pin 25 of the mSATA female connector, pin 14 of the second SATA channel switching chip is connected to pin 31 of the mSATA female connector, and pin 13 of the second SATA channel switching chip is connected to pin 33 of the mSATA female connector; pin 6 of the second SATA channel switching chip is connected to pin 52 of the mSATA female connector; pin 2, pin 24, pin 39, and pin 41 of the mSATA female connector are respectively connected to the DC3.3V circuit chip.

8. The multi-interface compatible aging test board according to claim 7, characterized in that: The product model of the DC3.3V circuit chip is MT3035. The DC3.3V circuit chip includes 10 groups of pins, wherein pins 8-10 of the DC3.3V circuit chip are connected to the DC5V power supply, and pins 1-3 of the DC3.3V circuit chip are respectively connected to the M.2 female connector and the mSATA female connector to provide stepped-down DC3.3V.

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