High-voltage half-bridge driving circuit and control chip thereof
By integrating the filtering function inside the control chip of the high-voltage half-bridge driving circuit, the external capacitor is cancelled, and the problems of large capacitor volume and long reaction delay are solved, and efficient overcurrent protection and accurate current detection are achieved.
Patent Information
- Application Number
- CN202422471129.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-08-29
- Estimated Expiration
- 2034-10-12
AI Technical Summary
In the existing high-voltage half-bridge driver chips, larger capacitors are used for current detection signal filtering, resulting in large volume and long reaction delay, reducing the overcurrent protection accuracy and effect.
The filtering function is integrated inside the control chip, the external capacitor is cancelled, and the selective shielding of current glitches is realized through the internal circuit to avoid accidentally triggering overcurrent protection.
It reduces the system size and cost, improves the reliability and accuracy of overcurrent protection, eliminates the delay of external filter circuits, and prevents overshoot of overcurrent protection.
Smart Images
Figure CN223285742U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronics, and specifically but not limited to a high-voltage half-bridge drive circuit and a control chip thereof. Background Art
[0002] In the field of high-voltage half-bridge drive, the current mainstream power driver chips have a current detection function, which is used for current control and / or overcurrent protection. Figure 1 A current detection circuit for a high-voltage half-bridge circuit is shown. The current detection circuit includes a detection resistor Rs and an RC filter circuit. The output end (source) of the lower tube QL in the half-bridge circuit is connected in series with the detection resistor Rs for sampling the current flowing through the lower tube QL. The detection resistor Rs is connected to the RC filter circuit to filter the current sampling signal to filter out the glitches in the signal, thereby avoiding the signal glitches from falsely triggering the overcurrent protection, wherein the RC filter circuit includes a capacitor C and a resistor R. The filtered current detection signal is sent to the inside of the chip for operations such as overcurrent protection. Especially in the field of three-phase high-voltage half-bridge driver chips, it is more necessary to filter the current detection signal to prevent the glitches generated in situations such as phase switching from falsely triggering the overcurrent protection.
[0003] To effectively prevent overcurrent nuisance triggering caused by current spikes, a larger capacitor C is required, coupled between current sense pin 1 and reference ground 2, to filter out large current spikes. However, larger capacitors are bulky and can cause a significant delay in the detection signal's response to current changes. This delays the overcurrent protection from shutting down, causing current overshoot and significantly reducing the accuracy and effectiveness of the protection.
[0004] In view of this, it is necessary to provide a new structure and control method to solve at least part of the above problems. Utility Model Content
[0005] In order to at least address one or more problems in the background technology, the present invention proposes a high-voltage half-bridge drive circuit and a corresponding control chip.
[0006] The high-voltage half-bridge drive circuit includes: at least one half-bridge circuit, each half-bridge circuit includes an upper tube and a lower tube, wherein the first end of the upper tube is coupled to the line voltage end, and the second end of the upper tube is coupled to the first end of the lower tube; a control chip, having a current detection pin, a reference ground pin and multiple drive pins, and the multiple drive pins are respectively coupled to the control end of the upper tube and the control end of the lower tube; and a detection resistor, wherein the first end of the detection resistor is coupled to the second end of the lower tube and the current detection pin, and the second end of the detection resistor is coupled to the reference ground pin; wherein no capacitor is set between the current detection pin and the reference ground pin outside the control chip.
[0007] Optionally, the control chip is manufactured on a semiconductor substrate to form a semiconductor wafer, and the ports of the semiconductor wafer include a current detection pin, a reference ground pin and a plurality of driving pins.
[0008] Optionally, the control chip includes a semiconductor chip, a lead frame and packaging material, wherein the semiconductor chip is placed on the lead frame, the port of the semiconductor chip is coupled to the lead frame through a conductive material, the packaging material encapsulates the semiconductor chip and part of the lead frame, and another part of the lead frame is exposed outside the packaging material to form pins, and the pins include a current detection pin, a reference ground pin and multiple drive pins.
[0009] Optionally, the at least one half-bridge circuit includes three half-bridge circuits, configured to form a three-phase half-bridge drive circuit.
[0010] Optionally, the control chip includes: an overcurrent comparison circuit, wherein a first input terminal of the overcurrent comparison circuit is coupled to a current detection pin, a second input terminal of the overcurrent comparison circuit is coupled to an overcurrent threshold signal, and an output terminal of the overcurrent comparison circuit provides an overcurrent comparison signal; a signal shaping circuit, wherein an input terminal of the signal shaping circuit is coupled to the current detection pin, and an output terminal of the signal shaping circuit provides a shaped processing signal; and a timing filter circuit, coupled to an output terminal of the overcurrent comparison circuit and an output terminal of the signal shaping circuit, and an output terminal of the timing filter circuit provides an overcurrent protection signal. This circuit is used to achieve a filtering effect of a large capacitor, selectively shield higher current glitches, and avoid false triggering of overcurrent protection.
[0011] Optionally, the signal shaping circuit includes a Schmitt trigger, an input end of the Schmitt trigger is coupled to the current detection pin, and an output end of the Schmitt trigger is coupled to the timing filter circuit.
[0012] Optionally, the timing filter circuit includes a first timing filter circuit, a second timing filter circuit and a logic circuit, the input end of the first timing filter circuit and the input end of the second timing filter circuit are coupled to the output end of the overcurrent comparison circuit, the output end of the second timing filter circuit is coupled to the first input end of the logic circuit, the output end of the signal shaping circuit is coupled to the second input end of the logic circuit, the output end of the logic circuit is coupled to the reset end of the first timing filter circuit, and the output end of the first timing filter circuit is coupled to the output end of the timing filter circuit.
[0013] Optionally, the first timing filter circuit includes a first switch, a first resistor, a second resistor, a second switch, a third resistor, a first capacitor and a first Schmitt trigger, wherein the first switch, the first resistor, the second resistor and the second switch are coupled in series between the voltage source and the reference ground pin, the control ends of the first switch and the second switch are coupled to the output end of the overcurrent comparison circuit, the coupling point of the first resistor and the second resistor is coupled to the first end of the third resistor, the second end of the third resistor is coupled to the first end of the first capacitor and the input end of the first Schmitt trigger and constitutes the reset end of the first timing filter circuit, the second end of the first capacitor is coupled to the reference ground pin, and the output end of the first Schmitt trigger constitutes the output end of the first timing filter circuit.
[0014] Optionally, the second timing filter circuit includes a third switch, a fourth resistor, a fifth resistor, a fourth switch, a sixth resistor, a second capacitor and a second Schmitt trigger, wherein the third switch, the fourth resistor, the fifth resistor and the fourth switch are coupled in series between the voltage source and the reference ground, the control ends of the third switch and the fourth switch are coupled to the output end of the overcurrent comparison circuit, the coupling point of the fourth resistor and the fifth resistor is coupled to the first end of the sixth resistor, the second end of the sixth resistor is coupled to the first end of the second capacitor and the input end of the second Schmitt trigger, the second end of the second capacitor is coupled to the reference ground pin, and the output end of the second Schmitt trigger constitutes the output end of the second timing filter circuit.
[0015] Optionally, the logic circuit includes: a first logic switch, a control end of the first logic switch coupled to the output end of the signal shaping circuit, and a first end of the first logic switch coupled to the reset end of the first timing filter circuit; and a second logic switch, a control end of the second logic switch coupled to the output end of the second timing filter circuit, a first end of the second logic switch coupled to the second end of the first logic switch, and a second end of the second logic switch coupled to the reference ground.
[0016] Optionally, the signal shaping circuit includes a comparator or an inverter.
[0017] The high-voltage half-bridge drive circuit and control chip proposed in the utility model integrate the filtering function into the control chip, realizing a structure without external capacitors in the high-voltage half-bridge overcurrent protection function, reducing the system volume and cost, eliminating the delay of the external filtering circuit, and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings are used to provide a further understanding of the present invention and, together with the description, to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:
[0019] Figure 1 A conventional current detection circuit for a high-voltage half-bridge circuit is shown;
[0020] Figure 2A high-voltage half-bridge drive circuit according to an embodiment of the present invention is shown;
[0021] Figure 3 A high-voltage half-bridge drive circuit according to a specific embodiment of the present utility model is shown;
[0022] Figure 4 A high-voltage half-bridge drive circuit according to an embodiment of the present invention is shown;
[0023] Figure 5 The overcurrent protection circuit in the control chip according to one embodiment of the present utility model is shown;
[0024] Figure 6 The figure shows an overcurrent protection circuit in a control chip according to a specific embodiment of the present utility model. DETAILED DESCRIPTION
[0025] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.
[0026] The description in this section focuses on a few typical embodiments only. The present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, replacement of certain technical features in different embodiments, and replacement of certain technical features in the embodiments with the same or similar prior art methods are also within the scope of the present invention.
[0027] "Coupled" or "connected" in this specification encompasses both direct and indirect connections. An indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance, or a connection through an intermediate circuit or component as described in the embodiments of this specification. An indirect connection may also include a connection through other active or passive devices that achieve the same or similar functions, such as a connection through circuits or components such as switches, signal amplifiers, and follower circuits. "Multiple" or "many" refers to two or more.
[0028] Figure 2A high-voltage half-bridge driver circuit 200 according to an embodiment of the present invention is shown. The high-voltage half-bridge driver circuit 200 includes a half-bridge circuit 21, a control chip 20, and a sense resistor Rs. The half-bridge circuit 21 includes a high-side transistor QH and a low-side transistor QL. The first terminal of the high-side transistor QH is coupled to the voltage terminal BUS, and the second terminal of the high-side transistor QH is coupled to the first terminal of the low-side transistor QL. The control chip 20 has a current sense pin I TRIP, a reference ground pin VSS, and multiple drive pins HO1 and LO1. The multiple drive pins HO1 and HO2 are coupled to the control terminals of the high-side transistor QH and the low-side transistor QL, respectively. The high-side and low-side transistors in the half-bridge circuit 21 can be metal oxide semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), or insulated gate bipolar transistors (IGBTs). In the illustrated embodiment, the drain of the high-side transistor QH is coupled to the voltage terminal BUS, the source of the high-side transistor QH is coupled to the drain of the low-side transistor QL, and the source of the low-side transistor QL is coupled to the sense resistor Rs. The control chip 20 also has other pins, which are not described in detail here. Preferably, the high-voltage half-bridge drive circuit includes a three-phase half-bridge circuit, including three half-bridge circuits, and each half-bridge circuit includes an upper tube and a lower tube. The first end of the detection resistor Rs is coupled to the current detection pin I TRIP and the second end of the lower tube QL, and the second end of the detection resistor Rs is coupled to the reference ground pin VSS. In the illustrated embodiment, a resistor is provided between the current detection pin I TRIP and the source of the lower tube QL. In other embodiments, the external resistor can be omitted. Unlike the prior art, in the high-voltage half-bridge drive circuit 200 of the embodiment of the utility model, outside the control chip 20, no capacitor is required between the current detection pin I TRIP and the reference ground pin VSS to enable normal operation of the overcurrent protection and filtering functions.
[0029] Figure 3 A high-voltage half-bridge drive circuit 300 according to a specific embodiment of the present invention is shown. In this embodiment, the high-voltage half-bridge drive circuit 300 is applied to a three-phase high-voltage half-bridge drive. The high-voltage half-bridge drive circuit 300 includes three half-bridge circuits 31, each of which includes an upper transistor and a lower transistor. The first terminals of the three upper transistors are coupled to a voltage terminal, and the second terminals of the three lower transistors are coupled to a sense resistor Rs. The control chip 30 has 28 pins. In addition to the current sense pin I TRIP and the reference ground pin VSS, it also includes three groups of drive pins: HO1, LO1, HO2, LO2, HO3, and LO3, as well as other power supply pins VCC, signal control pins, and signal feedback pins. Each group of drive pins includes two drive pins, each for driving the upper transistor and lower transistor in a half-bridge circuit. In this three-phase half-bridge drive circuit, a capacitor is not required between the current sense pin I TRIP and the reference ground pin VCC for normal operation. Therefore, no capacitor is provided between the current sense pin I TRIP and the reference ground pin VCC.
[0030] In the illustrated embodiment, the control chip 30 is in the form of an electronic package. No capacitor is provided between the current sense pin I TRIP and the reference ground pin VCC outside the electronic package. In one embodiment, the control chip 30 comprises a semiconductor chip, a lead frame, and packaging material. The semiconductor chip is placed on the lead frame, and the ports of the semiconductor chip are coupled to the lead frame via conductive material, such as metal leads or conductive adhesive, so that the ports of the semiconductor chip can be electrically coupled to the exterior of the electronic package through the lead frame to form pins. The packaging material encapsulates the semiconductor chip and a portion of the lead frame, while another portion of the lead frame is exposed outside the packaging material to form pins, including the illustrated current sense pin I TRIP, the reference ground pin VSS, and the drive pins HO1, LO1, and HO2.
[0031] In another embodiment, the control chip is fabricated on a semiconductor substrate to form a semiconductor chip, and the ports of the semiconductor chip serve as current detection pins, reference ground pins, and multiple drive pins. No capacitor is set between the current detection pin and the reference ground pin outside the package, or between the current detection pin and the reference ground pin of the semiconductor chip inside the package, and the overcurrent protection function can operate normally.
[0032] Figure 4A high-voltage half-bridge driver circuit 400 according to an embodiment of the present invention is shown, which shows a partial circuit topology of the integrated circuit within the control chip 40, which is used to filter current glitches within the control chip 40, thereby eliminating the need for an external capacitor between the current detection pin I TRIP and the reference ground pin VSS. Preferably, the high-voltage half-bridge driver circuit 400 is used to drive a motor. The high-voltage half-bridge driver circuit 400 includes a control chip 40 and a high-voltage half-bridge circuit 401. The control chip 40 is used to output control signals LO, HO, etc. at the drive pins to drive the high-voltage half-bridge circuit 401 and control the on and off states of the power switches in the half-bridge circuit 401. The half-bridge circuit 401 includes an upper tube QH and a lower tube QL, which are controlled by control signals HO and LO, respectively. In one embodiment, the half-bridge circuit is a three-phase half-bridge circuit, including three half-bridge circuits, and the six power switches in the three half-bridge circuits are controlled by six control signals output by the control chip 40. The power switches in the half-bridge circuit 401 can be metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), or insulated gate bipolar transistors (IGBTs). The control chip 40 has a current sensing pin I TRIP and a reference ground pin VSS. The output of the lower transistor (shown as the source of the power switch QL) is coupled to the first end of the sense resistor Rs and the current sensing pin I TRIP of the control chip 40. The second end of the sense resistor Rs is coupled to the reference ground pin VSS of the control chip 40. The control chip 40 obtains a current sensing signal Vs representing the current flowing through the lower transistor QL via the current sensing pin I TRIP. The reference ground pin VSS is connected to the system reference ground. In the three-phase half-bridge circuit embodiment, the outputs of the three lower transistors in the three half-bridge circuits are all coupled to the first end of the sense resistor Rs and the current sensing pin I TRIP. The second end of the sense resistor Rs is coupled to the reference ground pin VSS of the control chip 40. In this way, no external capacitor needs to be provided between the current detection pin I TRIP and the reference ground pin VSS of the control circuit, and the filtering function is completely realized by the internal circuit of the control chip 40 .
[0033] In one embodiment, the control chip 40 is fabricated on a semiconductor substrate. The current sense pin I TRIP and the reference ground pin VSS are external ports of the semiconductor die, connected to the current sense pin and the reference ground pin outside the electronic package via electrical conductors. In another embodiment, the control chip 40 is fabricated within an electronic package, forming a packaged chip. The current sense pin I TRIP and the reference ground pin VSS are external pins of the packaged chip. No capacitors are required to achieve filtering, either between the current sense pin I TRIP outside the packaged chip and the reference ground pin VSS of the control circuit, or between the current sense pin I TRIP and the reference ground pin VSS of the semiconductor die within the packaged chip.
[0034] Specifically, the control chip 40 includes an overcurrent comparison circuit 41, a signal shaping circuit 42, and a timing filter circuit 43, which provide overcurrent protection for the control chip 40. The input of the overcurrent comparison circuit 41 is coupled to the current sensing pin I TRIP for receiving the current sensing signal Vs. The overcurrent comparison circuit 41 compares the current sensing signal Vs with the overcurrent threshold Vref and provides an overcurrent comparison signal S1. The input of the signal shaping circuit 42 is coupled to the current sensing pin I TRIP for receiving the current sensing signal Vs. The signal shaping circuit 42 shapes the current sensing signal Vs and outputs at least one shaped signal Vz. In one embodiment, the signal shaping circuit 42 includes one or more Schmitt triggers, which output one or more corresponding valid signals when the current sensing signal Vs exceeds one or more thresholds. In one embodiment, the signal shaping circuit 42 includes one or more comparators connected in series or parallel. In another embodiment, the signal shaping circuit 42 includes one or more inverters connected in series or parallel. The signal shaping circuit 42 can shape the current sensing signal Vs into a substantially square wave signal based on the amplitude of the current sensing signal Vs. The timing filter circuit 43 processes the overcurrent comparison signal S1 and the shaped signal Vz, selectively shielding the overcurrent comparison signal S1 based on the shaped signal Vz. It then selectively filters glitches in the current detection signal based on other conditions of the current detection signal Vs that differ from those of the overcurrent comparison circuit 41, thereby implementing and optimizing the filtering function and outputting the overcurrent protection signal OCP. In one embodiment, the shaped signal Vz is used to control the enabling and resetting of the timing filter circuit 43. When the shaped signal Vz is active, the timing filter circuit 43 is reset and the timing is restarted to avoid immediate overcurrent protection. This prevents short-term high-level glitches, such as phase switching or input signal glitches, from falsely triggering the overcurrent protection, achieving a large-capacitor filtering effect. In this embodiment of the utility model, an RC filtering circuit is not required external to the current detection pin I TRIP, eliminating external capacitance, resulting in a more streamlined circuit module and lower system cost. Furthermore, detection is more timely and accurate, reducing signal detection delay and preventing overshoot.
[0035] Figure 5The overcurrent protection circuit in a control chip 500 according to an embodiment of the present invention is shown. The signal shaping circuit includes a Schmitt trigger 51 and a one-shot circuit 52. The input of the Schmitt trigger 51 receives the current detection signal Vs, the output of the Schmitt trigger 51 is coupled to the input of the one-shot circuit 52, and the output of the one-shot circuit 52 provides a shaped processing signal Oneshot. When the current detection signal Vs is greater than the flip threshold of the Schmitt trigger 51, the one-shot circuit 52 outputs a high-level pulse. The one-shot circuit 52 can be edge-triggered, outputting a pulse signal on the rising or falling edge of the output signal of the Schmitt trigger 51, which is used to reset the first timing filter circuit 53, causing the timing filter circuit to reset. In the illustrated embodiment, the Schmitt trigger 51 is an inverting trigger, so an inverting circuit is added after the Schmitt trigger 51. However, it should be understood that the Schmitt trigger 51 and the inverting circuit as a whole can be regarded as a Schmitt trigger.
[0036] In another embodiment, the signal shaping circuit may include multiple inverters or multiple comparators instead of a Schmitt trigger, and is used to shape the current detection signal into a required waveform according to the signal amplitude for controlling the timing filter circuit.
[0037] The timing filter circuit includes a first timing filter circuit 53, a second timing filter circuit 54, and a logic circuit 55. The inputs of the first timing filter circuit 53 and the second timing filter circuit 54 are coupled to the output of the overcurrent comparison circuit 21 for receiving the overcurrent comparison signal S1. The output of the second timing filter circuit 54 and the output of the one-shot circuit 52 are coupled to two inputs of the logic circuit 55. The output of the logic circuit 55 is coupled to the reset terminal CLR of the first timing filter circuit 53. The first timing filter circuit 53 has a first timing time T1. Only when the overcurrent comparison signal S1 remains high for longer than the first timing time T1 does the first timing filter circuit 53 output a valid (e.g., high) overcurrent protection signal OCP. However, whether the overcurrent protection signal OCP remains high is further affected by the signal at the CLR reset terminal. The second timing filter circuit 54 has a second timing time T2. When the overcurrent comparison signal S1 remains high for longer than the second timing time T2, the second timing filter circuit 54 outputs a high signal. The first timing time T1 is greater than the second timing time T2. In the illustrated embodiment, logic circuit 55 includes a NAND gate. When either second timing filter circuit 54 or one-shot circuit 52 outputs a low-level signal, NAND gate 55 outputs a high-level signal, preventing the reset of first timing filter circuit 53 from being triggered. NAND gate 55 logically includes an AND gate and a NOT gate. Alternatively, logic circuit 55 may include only an AND gate, with its two inputs coupled to the output of the second timing filter circuit and the output of the signal shaping circuit, respectively, without a NOT gate, depending on the logic control method. In one embodiment, its working state is as follows: in the first case, when the duration of the signal glitch outside the current detection pin I TRIP is very short, less than the first timing time T1, and the amplitude of the signal glitch is lower than the flip threshold of the Schmitt trigger 51, the Schmitt trigger 51 does not flip, the one-shot circuit 52 outputs a low level, the NAND gate 55 outputs a high level, the clear reset CLR of the first timing filter circuit 53 is not triggered, and the signal glitch of the I TRIP pin is filtered out by the first timing filter circuit 53, the overcurrent protection signal OCP is low, and the overcurrent protection is not triggered. In the second case, when the signal glitch outside the current detection pin I TRIP lasts for a long time and the glitch voltage amplitude is higher than the overcurrent threshold and lower than the flip threshold of the Schmitt trigger 51, the Schmitt trigger 51 does not flip, the one-shot circuit 52 outputs a low level, the NAND gate 55 outputs a high level, and the clear reset CLR of the first timing filter circuit 53 is not triggered. At the same time, when the effective state of the overcurrent comparison signal lasts for T1, the output of the first timing filter circuit 53 is a high level, thereby triggering the OCP overcurrent protection.In the third scenario, the glitch duration of the current detection signal Vs outside the current detection pin I TRIP is very short and the signal glitch amplitude is very high. The glitch duration is less than the second timing time T2, and the glitch amplitude is greater than the flip-flop threshold of the Schmitt trigger. The second timing filter circuit 54 outputs a low level, and the NAND gate 55 outputs a high level. The first timing filter circuit 53 is not reset. Moreover, the effective overcurrent comparison signal triggered by the signal glitch is less than the time T1 and is filtered out by the first timing filter circuit 53. The overcurrent protection signal OCP is low, and the overcurrent protection is not triggered. In the fourth scenario, the glitch amplitude of the current detection signal Vs is greater than the flip-flop threshold of the Schmitt trigger, and the Vs glitch duration is greater than the second timing time T2. At this time, the second timing filter circuit 54 and the one-shot circuit 52 both output a high level, the NAND gate 55 outputs a low level, the first timing filter circuit 53 is reset, and the signal OCP is low. If the glitch amplitude of the current detection signal Vs no longer exceeds the Schmitt threshold, the first timing filter circuit 53 resets the timing, and the system re-enters the first or second scenario, depending on the duration of the I TRIP pin signal Vs glitch exceeding the overcurrent threshold Vref. In the fifth scenario, the glitch duration of the current detection signal Vs external to the I TRIP pin is very long (exceeding the first timing time T1) and the amplitude remains above the Schmitt trigger's flip-flop threshold. NAND gate 55 continuously outputs reset pulses. At this point, the first timing filter circuit 53 remains in a reset state, waiting for the I TRIP pin glitch amplitude to return to normal. The fourth and fifth scenarios can be considered as situations where the system's OCP filter time adaptively lengthens due to the extremely long external glitch amplitude and duration, eliminating the need for an external RC filter circuit on the I TRIP pin to increase the auxiliary filtering time. Through the embodiments of the present invention, the external filtering circuit of the current detection pin I TRIP can be removed, and filtering is achieved without the need for an external capacitor. Normal overcurrent protection triggering and abnormal states can be automatically identified, thereby improving reliability, saving costs, reducing the delay caused by the external filtering circuit, avoiding overshoot in the overcurrent protection, and improving the current detection accuracy of the system.
[0038] In another embodiment, the signal shaping circuit outputs multiple shaping processing signals, the timing filtering circuit may have more than two sub-timing filtering circuits, and the multiple shaping processing signals respectively control the sub-timing filtering circuits, which are used to selectively filter the overcurrent comparison signal according to different situations, thereby achieving effective filtering in more situations.
[0039] Figure 6The overcurrent protection circuit in a control chip 600 according to a specific embodiment of the present invention is shown. The signal shaping circuit includes a Schmitt trigger 61 and a one-shot circuit 62. The input of the Schmitt trigger 61 receives the current detection signal Vs, and the output of the Schmitt trigger 61 is coupled to the one-shot circuit 62. The output of the one-shot circuit 62 provides a shaped signal, Oneshot. In other embodiments, the one-shot circuit 62 may be omitted depending on the characteristics of the signal output by the Schmitt trigger. The timing filter circuit includes a first timing filter circuit 63, a second timing filter circuit 64, and a logic circuit. The first timing filter circuit 63 includes a first switch M1, a second switch M2, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a Schmitt trigger A1. The first switch M1, the first resistor R1, the second resistor R2, and the second switch M2 are coupled in series between a voltage source VD and a reference ground pin VSS. The control terminals of the first switch M1 and the second switch M2 are coupled to the output of the overcurrent comparison circuit 21 and are controlled by the overcurrent comparison signal S1. Within the resistor network, the junction of resistors R1 and R2 is coupled to the first end of resistor R3. The second end of resistor R3 is coupled to the first end of capacitor C1 and the input end of Schmitt trigger A1, serving as the reset end CLR of first timing filter circuit 63. The second end of capacitor C1 is coupled to reference ground VSS. The thresholds of resistors R1, R2, R3, capacitor C1, and Schmitt trigger A1 determine the first timing time T1 of first timing filter circuit 63, which is used to detect whether the duration of the active state of overcurrent comparison signal S1 exceeds the first timing time T1. When overcurrent comparison signal S1 is active, first switch M1 is turned on and second switch M2 is turned off, allowing current to flow from voltage source VD to first capacitor C1. When the active state of overcurrent comparison signal S1 exceeds the first timing time T1, the voltage across capacitor C1 reaches the threshold of Schmitt trigger A1, causing Schmitt trigger A1 to output a valid signal, which is low, as shown. When the overcurrent comparison signal S1 is in an invalid state, the first switch M1 is turned off and the second switch M2 is turned on, pulling the voltage on the first capacitor C1 down to zero. The second timing filter circuit 64 can be similar to the first timing filter circuit 63 and include a third switch M3, a fourth switch M2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second capacitor C2, and a second Schmitt trigger A2. The thresholds of resistors R4, R5, R6, the second capacitor C2, and the second Schmitt trigger A2 determine the length of the second timing time T2. When the duration of the valid state of the overcurrent comparison signal S1 exceeds the second timing time T2, the second Schmitt trigger A2 outputs a valid signal, as shown in the figure as a high level. Of course, the first timing filter circuit 63 and the second timing filter circuit 64 can have other forms, which are used to time the continuous valid state of the overcurrent comparison signal S1 and output a valid signal when the valid state exceeds the corresponding timing time.The first timing filter circuit 63 and the second timing filter circuit 64 may also have different circuit structures. The logic circuit includes a first logic switch L1 and a second logic switch L2 for implementation. Figure 5 The logic circuit 55 shown in FIG. The control terminal of the first logic switch L1 is coupled to the output terminal of the signal shaping circuit for receiving the shaped processing signal Oneshot. The first terminal of the first logic switch L1 is coupled to the reset terminal of the first timing filter circuit 63, i.e., the input terminal of the first Schmitt trigger A1. The control terminal of the second logic switch L2 is coupled to the output terminal of the second timing filter circuit 64. The first terminal of the second logic switch L2 is coupled to the second terminal of the first logic switch L1, and the second terminal of the second logic switch L2 is coupled to the reference ground VSS. When the glitch amplitude of the current detection signal Vs exceeds the threshold of the Schmitt trigger 61, the shaped processing signal Oneshot outputs a high level, turning on the first logic switch L1. When the current detection signal Vs exceeds the overcurrent threshold Vref for a second timing time T2, the second timing filter circuit 64 outputs a high level, turning on the second logic switch L2. When the amplitude of a glitch in the current detection signal Vs exceeds the threshold of the Schmitt trigger 61 and the duration of the glitch exceeds the second timing time T2, both the first logic switch L1 and the second logic switch L2 are turned on, the reset clear terminal CLR of the first timing filter circuit 63 is pulled down to the reference ground VSS level, the first Schmitt trigger A1 outputs an invalid signal, such as a high level, the voltage on the first capacitor C1 is pulled down to zero, and the first timing filter circuit 63 resets the timing. At this point, the previously valid overcurrent comparison signal S1 is shielded, the glitch signal in the current detection signal Vs is selectively filtered based on the reset terminal CLR signal, and the valid state of the overcurrent comparison signal S1 is reset by the first timing filter circuit 63. To ensure circuit logic stability, the logic circuit may further include a NOT gate L3 and a NOR gate L4. The input of NOT gate L3 is coupled to the output of the second timing filter circuit 64. The first terminal of NOR gate L4 is coupled to the output of the first timing filter circuit 63. The second terminal of NOR gate L4 is coupled to the output of NOR gate L3. The output of NOR gate L4 provides an overcurrent protection signal OCP, which ensures that a valid overcurrent protection signal OCP is output when the duration of overcurrent comparison signal S1 exceeds the second timing time T2, thereby reducing false triggering. Depending on the different settings for the active state levels of first Schmitt trigger A1 and second Schmitt trigger A2, the NOT gate can be placed in different locations. For example, when the active state of first Schmitt trigger A1 is high, the NOT gate can be placed between the output of first Schmitt trigger A1 and NOR gate L4. When the active state of second Schmitt trigger A2 is low, a NOT gate can be placed between the output of second Schmitt trigger A2 and second logic switch L2, or the second logic switch L2 can be changed from enhancement mode to depletion mode.
[0040] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input terminal" and "inverting input terminal" in the logic controls involved in the specification or drawings can be interchanged or changed with each other, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic controls.
[0041] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-mentioned embodiments. The relevant descriptions of the effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the relevant descriptions of the effects or advantages are not used to limit the scope of the utility model. Variations and changes to the embodiments disclosed here are possible, and the replacement of the embodiments and various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that, without departing from the spirit or essential characteristics of the present invention, the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts. Without departing from the scope and spirit of the present invention, other variations and changes can be made to the embodiments disclosed here.
Claims
1. A high voltage half-bridge drive circuit, characterized in that: include: At least one half-bridge circuit, each half-bridge circuit comprising an upper tube and a lower tube, wherein a first end of the upper tube is coupled to a line voltage terminal, and a second end of the upper tube is coupled to a first end of the lower tube; A control chip having a current detection pin, a reference ground pin, and a plurality of drive pins, wherein the plurality of drive pins are respectively coupled to the control end of the upper tube and the control end of the lower tube; as well as A detection resistor, wherein a first end of the detection resistor is coupled to the second end of the lower tube and the current detection pin, and a second end of the detection resistor is coupled to the reference ground pin; Wherein, no capacitor is provided between the current detection pin and the reference ground pin outside the control chip.
2. The driving circuit according to claim 1, wherein: The control chip is manufactured on a semiconductor substrate to form a semiconductor wafer. The ports of the semiconductor wafer include a current detection pin, a reference ground pin and a plurality of driving pins.
3. The driving circuit according to claim 1, wherein: The control chip includes a semiconductor chip, a lead frame and packaging materials, wherein the semiconductor chip is placed on the lead frame, the port of the semiconductor chip is coupled to the lead frame through a conductive material, the packaging material encapsulates the semiconductor chip and part of the lead frame, and the other part of the lead frame is exposed outside the packaging material to form pins, and the pins include a current detection pin, a reference ground pin and multiple drive pins.
4. The driving circuit according to claim 1, wherein: The at least one half-bridge circuit includes three half-bridge circuits.
5. The driving circuit according to claim 1, wherein: The control chip includes: an overcurrent comparison circuit, wherein a first input terminal of the overcurrent comparison circuit is coupled to the current detection pin, a second input terminal of the overcurrent comparison circuit is coupled to the overcurrent threshold signal, and an output terminal of the overcurrent comparison circuit provides an overcurrent comparison signal; a signal shaping circuit, wherein an input terminal of the signal shaping circuit is coupled to the current detection pin, and an output terminal of the signal shaping circuit provides a shaped processing signal; and The timing filter circuit is coupled to the output end of the overcurrent comparison circuit and the output end of the signal shaping circuit, and the output end of the timing filter circuit provides an overcurrent protection signal.
6. The driving circuit according to claim 5, wherein: The signal shaping circuit includes a Schmitt trigger, an input end of the Schmitt trigger is coupled to the current detection pin, and an output end of the Schmitt trigger is coupled to the timing filter circuit.
7. The driving circuit according to claim 5, wherein: The timing filter circuit includes a first timing filter circuit, a second timing filter circuit and a logic circuit. The input end of the first timing filter circuit and the input end of the second timing filter circuit are coupled to the output end of the overcurrent comparison circuit, the output end of the second timing filter circuit is coupled to the first input end of the logic circuit, the output end of the signal shaping circuit is coupled to the second input end of the logic circuit, the output end of the logic circuit is coupled to the reset end of the first timing filter circuit, and the output end of the first timing filter circuit is coupled to the output end of the timing filter circuit.
8. The driving circuit according to claim 7, wherein: The first timing filter circuit includes a first switch, a first resistor, a second resistor, a second switch, a third resistor, a first capacitor and a first Schmitt trigger, wherein the first switch, the first resistor, the second resistor and the second switch are coupled in series between a voltage source and a reference ground pin, the control ends of the first switch and the second switch are coupled to the output end of the overcurrent comparison circuit, the coupling point between the first resistor and the second resistor is coupled to the first end of the third resistor, the second end of the third resistor is coupled to the first end of the first capacitor and the input end of the first Schmitt trigger and constitutes a reset end of the first timing filter circuit, the second end of the first capacitor is coupled to the reference ground pin, and the output end of the first Schmitt trigger constitutes the output end of the first timing filter circuit.
9. The driving circuit according to claim 7, wherein: The logic circuit includes: a first logic switch, wherein a control terminal of the first logic switch is coupled to the output terminal of the signal shaping circuit, and a first terminal of the first logic switch is coupled to the reset terminal of the first timing filter circuit; and The second logic switch has a control end coupled to the output end of the second timing filter circuit, a first end coupled to the second end of the first logic switch, and a second end coupled to the reference ground.
10. The driving circuit according to claim 5, wherein: The signal shaping circuit includes a comparator or an inverter.
11. A control chip according to any one of claims 1 to 10.