Slope generator, analog-to-digital converter and image sensor

Abstract

The utility model discloses a ramp generator, an analog-to-digital converter and an image sensor, and relates to the field of signal processing. The ramp generator comprises a ramp current generating device which comprises a plurality of current generating sub-devices; wherein each current generation sub-device receives clock signals of different phases and is used for outputting current signals; the output ends of the plurality of current generation sub-devices are connected in parallel and are used for superimposing current signals; the multi-phase clock generation device is used for providing multiple groups of clock signals with different phases and the same clock frequency; and the load resistance device is used for converting the superposed current signal into a ramp voltage signal. According to the ramp generator provided by the utility model, the plurality of groups of clock signals with different phases are sent to the plurality of current generation sub-devices for processing, so that compared with an original ramp generator with a single clock signal, the current signals which are connected in parallel are changed for multiple times in the same clock period, and the current signals are converted into current signals; the slope or resolution of the ramp voltage signal is increased.

Description

Technical Field

[0001] The utility model belongs to the field of signal processing, and in particular relates to a ramp generator, an analog-to-digital converter and an image sensor. Background Art

[0002] In existing image sensors, the linear ramp voltage waveform signal (Vramp, hereinafter referred to as the ramp voltage signal) provided by the ramp generator is often used as a global reference signal in the analog-to-digital conversion circuit to convert the analog signal of the pixel into a digital code.

[0003] In order to meet the requirements of different working scenarios, it is often necessary to adjust the slope of the ramp voltage signal. For analog-to-digital conversion type ramp generators, the existing technology often adjusts the slope of the ramp voltage signal by changing the frequency of the clock signal input to the counter. However, due to process and structural limitations, and affected by parasitic effects between devices and traces, the operating frequency of the counter has a high-speed bottleneck, which limits the adjustment range of the slope of the ramp voltage signal. For example, when the delay time of the highest and lowest bits of the counter output exceeds half a clock cycle of the clock signal, synchronous adjustment cannot be performed, resulting in bit errors in the output result of the counter, affecting the normal working state of the ramp generator.

[0004] Therefore, a ramp generator is urgently needed to further expand the adjustment range of the slope of the ramp voltage signal. Utility Model Content

[0005] The utility model provides a ramp generator, an analog-to-digital converter, and an image sensor, which are used to expand the slope adjustment range of a ramp voltage signal.

[0006] In order to achieve the above purpose, the present invention proposes the following technical solutions:

[0007] In a first aspect of the present invention, a ramp generator is provided, comprising:

[0008] A ramp current generating device comprising a plurality of current generating sub-devices; wherein each current generating sub-device receives a clock signal of a different phase and is used to output a current signal; the output ends of the plurality of current generating sub-devices are connected in parallel to superimpose the current signals;

[0009] a multi-phase clock generating device connected to the input end of the ramp current generating device and configured to provide a plurality of clock signals with different phases but the same clock frequency to the plurality of current generating sub-devices;

[0010] The load resistance device is connected to the output ends of the multiple current generating sub-devices connected in parallel, and is used to convert the superimposed current signal into a ramp voltage signal.

[0011] Optionally, the phase difference between two clock signals with adjacent phases is the same.

[0012] Optionally, the number of the current generating sub-devices is the same as the number of the clock signals.

[0013] Optionally, each current generating sub-device includes:

[0014] a ramp counter connected to the output terminal of the multi-phase clock generating device, configured to receive a clock signal and generate a first digital signal based on the triggering of the clock signal;

[0015] a decoder connected to the output end of the ramp counter, configured to receive the first digital signal and perform digital conversion on the first digital signal to transform it into a second digital signal;

[0016] The current unit is connected to the output end of the decoder, and is used to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

[0017] Optionally, if the bit width of the ramp counter is N bits, the first digital signal is an N-bit binary code, and the decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code along the bit sequence from high to low, and the last m bits remain the binary code and are converted into the second digital signal, where m is a preset value; the thermometer code includes a row selection thermometer code and a column selection thermometer code.

[0018] Optionally, the current unit includes a D latch, and the input end of the D latch is connected to an AND or NOR logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as the switch control signal.

[0019] In a second aspect of the present invention, an analog-to-digital converter is provided, comprising: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit comprising: a comparator, a column counter, and the ramp generator described in the first aspect, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; the input terminal of the column counter is connected to the output terminal of the comparator; if the number of multiple groups of clock signals is a, the operating frequency of the column counter is adjusted to a times the original operating frequency.

[0020] In the third aspect of the present invention, an image sensor is provided, comprising: a pixel circuit, a digital logic circuit and the analog-to-digital converter of the second aspect, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

[0021] The beneficial effects of the utility model are as follows:

[0022] The utility model provides a ramp generator, comprising: a ramp current generating device, comprising a plurality of current generating sub-devices; wherein each current generating sub-device receives a clock signal of a different phase and is used to output a current signal; the output ends of the plurality of current generating sub-devices are connected in parallel and are used to superimpose the current signals; a multi-phase clock generating device, connected to the input ends of the ramp current generating device, is used to provide the plurality of current generating sub-devices with a plurality of groups of clock signals with different phases but the same clock frequency; and a load resistor device, connected to the output ends of the plurality of current generating sub-devices connected in parallel and is used to convert the superimposed current signals into a ramp voltage signal.

[0023] Based on the above-mentioned setting, the ramp generator provided by the present invention sends multiple groups of clock signals with different phases to multiple current generating sub-devices for processing, and converts the current signals provided by the current generating sub-devices into ramp voltage signals after parallel connection. Compared with the original ramp generator with a single clock signal, the parallel current signal undergoes multiple changes within the same clock cycle, thereby expanding the slope or resolution of the ramp voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 This is a structural diagram of a ramp generator provided by the utility model;

[0026] Figure 2 This is a structural diagram of a four-phase generating circuit provided by the utility model;

[0027] Figure 3 This is a structural diagram of a current generating sub-device provided by the utility model;

[0028] Figure 4 This is a schematic diagram of a four-phase clock signal provided by the present invention;

[0029] Figure 5 This is a schematic diagram of a decoding and synchronous latch circuit provided by the utility model;

[0030] Figure 6 This is a structural diagram of a current mirror switch provided by the utility model;

[0031] Figure 7This is a schematic diagram of an original ramp voltage signal provided by the utility model;

[0032] Figure 8 This is a schematic diagram of an adjusted ramp voltage signal provided by the present invention;

[0033] Figure 9 This is a schematic diagram of another adjusted ramp voltage signal provided by the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0035] In CMOS image sensors, a linear ramp voltage signal serves as a global reference signal for the analog-to-digital conversion circuit, which is used to convert the analog signal from the photodiode pixel into a digital code.

[0036] Existing technologies often adjust the slope of a ramp voltage signal by varying the frequency of the clock signal input to a counter. However, due to process and structural limitations, as well as parasitic effects between components and traces, the counter's operating frequency faces a high-speed bottleneck, limiting the maximum slope of the ramp voltage signal. The slope of a ramp voltage signal represents the absolute value of the voltage change per unit time.

[0037] In order to solve the above problems, the present invention provides a ramp generator to further expand the adjustment range of the slope of the ramp voltage signal. Figure 1 As shown, the ramp generator provided by the utility model includes:

[0038] The ramp current generating device comprises multiple current generating sub-devices, such as current generating sub-device 1, current generating sub-device 2, and current generating sub-device a. Each current generating sub-device receives a clock signal of a different phase and outputs a current signal. The output terminals of the multiple current generating sub-devices are connected in parallel to superimpose the current signals. "a" represents the number of current generating sub-devices. In the solution provided by the present invention, the number of current generating sub-devices is generally the same as the number of clock signals.

[0039] The multi-phase clock generating device is connected to the input end of the ramp current generating device and is used to provide multiple groups of clock signals with different phases but the same clock frequency to multiple current generating sub-devices.

[0040] The load resistance device is connected to the output ends of the multiple current generating sub-devices connected in parallel, and is used to convert the superimposed current signal into a ramp voltage signal.

[0041] Based on the above configuration, the ramp generator provided by the present invention transmits multiple sets of clock signals with different phases to multiple current generating sub-devices for processing, and then converts the current signals provided by the current generating sub-devices into a ramp voltage signal after parallel connection. Compared to the original ramp generator with a single clock signal, the parallel current signal undergoes multiple changes within the same clock cycle, which can effectively increase the slope or resolution of the ramp voltage signal. The resolution represents the minimum analog signal change that the ADC can recognize, and is usually expressed in bits. For example, an 8-bit ADC can recognize 256 different signal levels, while a 12-bit ADC can recognize 4096 signal levels.

[0042] In some embodiments, the phase differences between the clock signals provided by the multi-phase clock generator are the same, that is, the phase differences between two clock signals with adjacent phases are the same. For example, when the multi-phase clock generator provides four sets of clock signals with different phases, the phases of the four sets of clock signals are 0°, 90°, 180°, and 270°, respectively, relative to the reference clock signal.

[0043] When adjacent phase differences are the same, the triggering delays between adjacent clock signals are guaranteed to be the same, ensuring the same hold time for the current signals generated based on the clock signals. This effectively reduces the linearity of the final ramp voltage signal and minimizes glitches. Linearity represents the deviation between the actual output ramp voltage signal and the ideal ramp voltage signal. The smaller the linearity, the lower the deviation.

[0044] In actual work, a certain error is allowed in the phase difference between two clock signals with adjacent phases. The smaller the error, the lower the linearity of the ramp voltage signal generated by the ramp generator.

[0045] In one implementation, a multi-phase clock generation device can generate clock signals with different phases using a ring oscillator. Specifically, a reference clock signal is inserted into the ring oscillator to generate clock signals with different phases. A PLL is used in the ring oscillator. The clock signals with different phases are then distributed to different current generating sub-devices.

[0046] In one implementation, the multi-phase clock generating device can also provide clock signals of different phases based on a combination of a delay circuit and a plurality of phase interpolators. When the multi-phase clock generating device is a four-phase clock generating circuit that provides four sets of clock signals of different phases, such as Figure 2As shown, it includes a delay circuit and four phase interpolators (PI01, PI02, PI03, and PI04). The delay circuit delays the input reference clock signal by a predetermined delay time tPD and outputs the delayed clock signal. The delay time tPD is 1 / 4 of the reference clock signal cycle. The delay circuit then sends the delayed reference clock signal to the phase interpolators PI01, PI02, PI03, and PI04, respectively.

[0047] Phase interpolators PI01, PI02, PI03, and PI04 all have the same circuit. Each phase interpolator is a circuit with two inputs and one output, and outputs a signal at a time delayed by a predetermined delay time from the midpoint of the phase difference between the two input signals.

[0048] like Figure 2 As shown in FIG, a signal obtained by delaying the reference clock signal by approximately 1 / 4 cycle is input to phase interpolator PI01. Phase interpolator PI01 uses these signals to generate clock signal q0, one of the four-phase clock signals, and outputs the generated clock signal to the outside of the four-phase clock generation circuit. An inverted signal of the reference clock signal and a signal obtained by delaying the reference clock signal by approximately 1 / 4 cycle are input to phase interpolator PI02. Phase interpolator PI02 uses these signals to generate clock signal q1, one of the four-phase clock signals, and outputs the generated clock signal to the outside of the four-phase clock generation circuit. An inverted signal of the reference clock signal and a signal obtained by delaying the reference clock signal by approximately 1 / 4 cycle are input to phase interpolator PI03. Phase interpolator PI03 uses these signals to generate clock signal q2, one of the four-phase clock signals, and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The reference clock signal and the inverted signal obtained by delaying the reference clock signal by approximately 1 / 4 cycle are input to phase interpolator PI04. The phase interpolator PI04 generates a clock signal q3 as one of four-phase clock signals using these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit.

[0049] The phase interpolator generates four-phase clock signals each having a phase shifted by 1 / 4 cycle using a reference clock signal and a signal obtained by delaying the reference clock signal by approximately 1 / 4 cycle, and outputs the four-phase clock signals.

[0050] In addition, you can also change Figure 2 The number or combination of phase interpolators in the phase difference clock generation circuit in the example (four-phase clock generation circuit) can generate an 8-phase clock signal with each phase shifted by 1 / 8 cycle or a 16-phase clock signal with each phase shifted by 1 / 16 cycle.

[0051] Similarly, by changing Figure 2 The number of phase interpolators, their combination and their weighting coefficient W of the phase difference clock generation circuit in the example (four-phase clock generation circuit) can generate a three-phase clock signal with each phase shifted by 1 / 3 of a cycle or a five-phase clock signal with each phase shifted by 1 / 5 of a cycle.

[0052] In some embodiments, the number of current generating sub-devices is the same as the number of clock signals, that is, each current generating sub-device receives clock signals of different phases. For example, when the multi-phase clock generating device provides four sets of clock signals with phases of 0°, 90°, 180°, and 270°, the number of current generating sub-devices is 4, and current generating sub-device 1 receives the clock signal CLK with a phase of 0°. <1> , the current generating sub-device 2 receives the clock signal CLK with a phase of 90° <2> , the current generating sub-device 3 receives the clock signal CLK with a phase of 180° <3> The current generating sub-device 4 receives the clock signal CLK with a phase of 270° <4> .

[0053] In one implementation, Figure 3 As shown, the current generating sub-device includes: a ramp counter connected to the output end of the multi-phase clock generating device 1, for receiving a clock signal and generating a first digital signal based on the triggering of the clock signal.

[0054] The decoder is connected to the output end of the ramp counter and is used for receiving the first digital signal and performing digital system conversion on the first digital signal to transform it into a second digital signal.

[0055] A current unit is connected to the output terminal of the decoder, and is configured to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal. The current signal is generated and output by the current unit.

[0056] The ramp counter can be triggered by a rising edge or a falling edge of a clock signal. It is worth noting that when the ramp counters in different current sub-devices have the same triggering mode, the total number of current sub-devices is the same as the total number of clock signals of different phases.

[0057] When the ramp counter in a current sub-device has both rising-edge and falling-edge triggering modes, the total number of current sub-devices can be twice the total number of clock signals. For example, when there is only one clock signal, the total number of current sub-devices is two, including two ramp counters with rising-edge triggering and two with falling-edge triggering, respectively. This is equivalent to two clock signals with a 180° phase difference being input to the ramp counters with the same triggering mode in the present invention.

[0058] Similarly, when there are two clock signals with a phase difference of 90°, the total number of current sub-devices is 4, including two rising edge triggered and two falling edge triggered ramp counters. At this time, it is equivalent to the four clock signals with a phase difference of 90° in the present invention being input into the ramp counters under the same triggering mode respectively.

[0059] In some embodiments, if the ramp counter has an N-bit bit width, the first digital signal is an N-bit binary code. When the first digital signal is input to a decoder, the decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code in descending bit order, while the remaining m bits remain in binary code and are converted into a second digital signal. Here, m is a preset value; the thermometer code includes a row-selected thermometer code and a column-selected thermometer code.

[0060] For example, if the ramp counter has a 10-bit bit width and m is 6, the first digital signal is a 10-bit binary value. The decoder converts the upper 6 bits of binary code into a 3-bit row select (selrow) thermometer code and a 3-bit column select (selcol) thermometer code, respectively, while the lower 4 bits remain in binary code (sellow). This forms the second digital signal, which is output from the decoder's output terminal. Based on this processing, the second digital signal can effectively reduce the data volume of the digital signal compared to the first digital signal, improving signal transmission efficiency.

[0061] In some embodiments, the current unit includes a D latch, and the input end of the D latch is connected to an AND / NOR logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as a switch control signal.

[0062] In some embodiments, the ramp generator further includes a reference current generating circuit and a PSRR (Power Supply Rejection Ratio) compensation device. The reference current generating circuit provides a bias current for the current source of the ramp generator, and the PSRR compensation device is used to reduce the power supply ripple rejection ratio of the current source.

[0063] The utility model provides a ramp generator based on a four-phase clock signal, comprising a four-phase clock generator, four ramp counters, four decoders, four current units, and a load resistor. Each ramp counter has a bit width of N bits, and the switch control signal of the current unit uses a binary code with the lower m bits and a thermometer code with the upper Nm bits.

[0064] To convert binary code to thermometer code, the high-order bits are converted into row-select (selrow) and column-select (selcol) thermometer codes, while the low-order bits remain in binary code (sellow) for output. Four phase counters decode the codes and control four equal current mirror units, yielding (N+2) bits of data.

[0065] Conventional ramp generators control the switching of all current mirror arrays during each clock cycle, thereby varying the output voltage. However, in the present invention (using a four-phase clock signal as an example), compared to a conventional single-clock ramp generator, the first ramp counter controls the switching of only one-quarter of the current mirror array (i.e., current unit 1) after counting and decoding, while maintaining the unit current mirror (i.e., the amount of current signal adjustment during each triggering) unchanged.

[0066] During each clock cycle, the current mirror array controlled by each ramp counter is converted to a 1x RAMP voltage change through a load resistor. Similarly, after a quarter clock cycle, the current mirror array controlled by the second counter is also converted to a 1x RAMP voltage change through a load resistor. After two more quarter clock cycles, the current mirror arrays controlled by the third and fourth counters (current unit 3 and current unit 4) are also converted to voltage changes. This process completes voltage conversion at different phases within a single clock cycle.

[0067] Compared to a traditional ramp generator, each of the four phases increases the voltage by a factor of two, and after one clock cycle, they collectively contribute a quadruple voltage change, resulting in a ramp voltage signal with a slope that is four times greater. This ensures the RAMP voltage range remains unchanged, but the amount of voltage change data increases, meaning the resolution increases by 2 bits. Similarly, an 8-phase clock can achieve an additional 3 bits of resolution, and so on.

[0068] The four-phase clock generator can obtain four sets of clock signals with different phases through the reference clock, and the difference between each phase is 90 degrees, such as Figure 4 As shown, four sets of clock signals with different phases control four ramp counters and a binary-to-thermometer code device (i.e., decoder), as well as a current source array (i.e., a current generating sub-device connected in parallel). After conversion by the load resistor device 3, the RAMP output voltage is obtained.

[0069] The present invention provides a DAC ramp with a hybrid structure of 4-bit binary and 4-bit thermometer codes. A decoder converts the high-order 4-bit binary code output by a counter into a 3-bit row-select thermometer control code and a 3-bit column-select thermometer control code. The 8-bit ramp generator provided by the present invention is equivalent to a conventional 10-bit ramp generator. Here, x1...x16 represent the number of current mirrors within a current unit, namely, current unit x1 (indicating the presence of one current mirror), current unit x2 (indicating the presence of two current mirrors), current unit x4, current unit x8, and current unit x16 (indicating the presence of 16 current mirrors), with the number of current units x16 being reduced to 1 / 4.

[0070] Each counter corresponds to a set of current mirror arrays (i.e., current units), ramp counters <1> Generated clkarray, sell <1> , tiehi, tielo are connected to the clk, A, B, C ports of the first group of current units x1 respectively; clkarray, sell <2> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x2 modules respectively; clkarray, sell <3> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x4 modules respectively; clkarray, sell <4> , tiehi, tielo are connected to the clk, A, B, C ports of the first group of current unit x8 modules respectively; the first group of current unit x16 modules has a total of 16 current mirror units, which connect clkarray, 4>(sel_col<1:3>,tielo)、< 4>tiehi,sel_row<(1 4,2 4,3 4)> and sel_row<(1 4,2 4,3 4)>,< 4> tielo, tiehi are connected to the clk, A, B, and C ports of Icell<16:1>. Similarly, the second, third, and fourth groups of counters are connected to their corresponding current mirror arrays according to the above method.

[0071] like Figure 5As shown, the current cell module internally performs AND / OR logic on the row and column control codes and recompiles them into the current cell's switch control signals. However, because the delay paths of these control signals cannot remain completely consistent during the encoding and decoding process, the control signals must be passed through a D latch to synchronize signals of different bits on the same rising edge of the clock. This ensures that the control signals sel and selb of different current cells arrive at the current mirror switch at the same time.

[0072] The structure of the current mirror switch is as follows Figure 6 As shown, pbias represents the current tube bias voltage, pcas represents the common-source common-gate tube bias voltage, sel represents the current turn-on signal, and selb represents the current turn-off signal.

[0073] If the clock signal frequency in the original ramp generator has been adjusted to the maximum value f (in Hz), the present invention also provides an adjustment method for the ramp generator provided by the present invention to increase the slope or resolution of the ramp voltage signal. The adjustment method includes the following steps:

[0074] Step 1: Obtain the number a of multiple groups of clock signals.

[0075] Step 2: Adjust the regulation amount of the current signal at each trigger to the original 1 / a, and keep the bit width of the ramp counter unchanged.

[0076] Based on the above processing, by adjusting the adjustment amount of the current signal in the ramp generator to the original 1 / a at each trigger, the range of the original ramp voltage signal does not change, thereby ensuring the applicability of the ramp generator in the utility model and can be directly applied to the usage scenarios of the original ramp generator.

[0077] At the same time, although the bit width of the ramp counter remains unchanged, the total bit width of multiple ramp counters increases due to the adaptability of the number of ramp counters and the number of clock signals, thereby improving the resolution while ensuring that the range of the ramp voltage signal remains unchanged.

[0078] like Figure 7 As shown, the original ramp represents the ramp voltage signal generated by the original ramp generator, x1 represents the slope of the ramp voltage signal is 1, v represents the voltage value, and t represents the time length. Figure 8 As shown, Figure 8 Figure 1 is a schematic diagram of a ramp voltage signal including the original ramp and the current ramp. The current ramp represents the ramp voltage signal obtained using the ramp generator provided by the present invention and the aforementioned adjustment method. The slope and voltage range of this ramp are the same as those of the original ramp, but its resolution is increased by a factor of a.

[0079] In some embodiments, the adjustment method further comprises the following steps:

[0080] Step 3: Determine whether the number a of multiple clock signals is 2 b ; Wherein, b is an integer greater than or equal to 1.

[0081] Step 4: If yes, reduce the bit width of the ramp counter by b bits, and keep the adjustment amount of the current signal unchanged in each triggering.

[0082] Based on the above processing, by reducing the bit width of the ramp counter by b bits, the resolution of the ramp generator provided by the present invention can be effectively guaranteed not to change. At the same time, the adjustment amount of the current signal under each triggering remains unchanged, which can ensure that the voltage range of the ramp voltage signal does not change, thereby ensuring the applicability of the ramp generator in the present invention.

[0083] In addition, in the process of generating a ramp voltage signal, the number of triggers that cause its current signal to change within the same clock cycle is a times that of the original ramp generator. Therefore, on the basis of the unchanged resolution and voltage range of the ramp voltage signal, its slope is further increased to a times the original.

[0084] like Figure 9 As shown, this ramp is a ramp voltage signal generated based on a four-phase clock signal. Compared with the original ramp, its voltage range and resolution remain unchanged, but its slope is increased by four times.

[0085] For step 3, if the number of clock signals a is not 2 b In this case, the bit width of the ramp counter can be reduced by the bit closest to the log2a integer, while maintaining the current signal's adjustment amount for each trigger, thereby increasing the slope of the ramp voltage signal. In practice, this operation will result in a certain error in the bit width or voltage range of the resulting ramp voltage signal. Therefore, the number of clock signal or current generating sub-devices within the ramp generator of the present invention is typically 2, 4, 8, or 16.

[0086] Based on the same improved concept, the present invention also provides an analog-to-digital converter, comprising: at least one column analog-to-digital conversion unit, wherein the column analog-to-digital conversion unit includes: a comparator, a column counter, and a ramp generator of the present invention. The comparator's non-inverting input is connected to the ramp generator's output; the column counter's input is connected to the comparator's output. If the number of clock signals is a, the column counter's operating frequency is adjusted to a times the original operating frequency. Furthermore, due to the increased slope of the ramp voltage signal, the ramp generator's quantization time is shortened, thereby reducing the power consumption of the analog-to-digital converter.

[0087] The present invention provides an analog-to-digital converter for a readout circuit. A ramp generator generates a ramp voltage signal, which is sampled by a capacitor to the non-inverting input of each column comparator. The inverting input of the comparator samples the pixel signal of each column (including signal Vin1, signal Vin2, etc.). The ramp voltage signal traverses the entire quantization voltage range and is compared with the pixel signal. At the same time, a column counter starts counting. When the ramp voltage signal is greater than the pixel signal, the comparator flips and the column counter stops working. The counting result at this time is the digital code value after the pixel signal is quantized. It is worth noting that if the slope of the ramp voltage signal generated by the ramp generator provided by the present invention increases by a times, the operating frequency of the column counter needs to be increased to a times the original operating frequency.

[0088] In actual work, the operating frequency of the column counter can be adjusted by increasing the frequency of the clock signal input to the column counter. Alternatively, the operating frequency of the column counter can also be increased based on a multi-phase clock signal. Taking a four-phase clock signal as an example, the column counter can achieve 4 times the counting frequency at the same resolution. For example, the bit width of the column counter is 10 bits and the operating frequency is 1 GHz. At this time, the time from 1 to 1024 is 1024ns. For a bit width of 8 bits and an operating frequency of 1 GHz, the time to count is only 256ns, which is 1 / 4 of 10 bits. Through four groups of clock signals with different phases, 10 bits of data can be combined. That is, the utility model only needs to achieve 10-bit counting in 1 / 4 of the time, thereby improving the operating frequency and upper limit of the column counter.

[0089] Existing CMOS image sensor circuits include: a pixel array, a readout circuit, a functional logic unit, a control circuit, and a status register. The pixel array performs photoelectric conversion, converting photons into electrons; the readout circuit reads the electrical signals converted by the pixel array; the functional logic unit adjusts the readout circuit's signal readout and transmission methods; the status register temporarily stores the readout circuit's status; and the control circuit uses the readout circuit's status to provide feedback and adjust the pixel array.

[0090] Based on the same improved concept, the present invention also provides an image sensor comprising a pixel circuit, a digital logic circuit, and the present invention's analog-to-digital converter. The pixel circuit is connected to the inverting input of a comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal, and the ramp initial value signal.

[0091] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A ramp generator, characterized in that: include: A ramp current generating device comprising a plurality of current generating sub-devices; wherein each current generating sub-device receives a clock signal of a different phase and is used to output a current signal; the output ends of the plurality of current generating sub-devices are connected in parallel to superimpose the current signals; a multi-phase clock generating device connected to the input end of the ramp current generating device and configured to provide a plurality of clock signals with different phases but the same clock frequency to the plurality of current generating sub-devices; The load resistance device is connected to the output ends of the multiple current generating sub-devices connected in parallel, and is used to convert the superimposed current signal into a ramp voltage signal.

2. The ramp generator according to claim 1, characterized in that The phase difference between two clock signals with adjacent phases is the same.

3. The ramp generator according to claim 1, characterized in that The number of the current generating sub-devices is the same as the number of the clock signals.

4. The ramp generator according to claim 1, characterized in that Each current generating sub-device includes: a ramp counter connected to the output terminal of the multi-phase clock generating device, configured to receive a clock signal and generate a first digital signal based on the triggering of the clock signal; a decoder connected to the output end of the ramp counter, configured to receive the first digital signal and perform digital conversion on the first digital signal to transform it into a second digital signal; The current unit is connected to the output end of the decoder, and is used to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

5. The ramp generator according to claim 4, characterized in that If the bit width of the ramp counter is N bits, the first digital signal is an N-bit binary code. The decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code in a bit order from high to low, and the remaining m bits remain in binary code and are converted into the second digital signal, where m is a preset value. The thermometer code includes a row-selected thermometer code and a column-selected thermometer code.

6. The ramp generator according to claim 5, characterized in that The current unit includes a D latch, and the input end of the D latch is connected to an AND / NOR logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as the switch control signal.

7. An analog-to-digital converter, characterized in that: The analog-to-digital converter includes: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit includes: a comparator, a column counter and a ramp generator according to any one of claims 1 to 6, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; the input terminal of the column counter is connected to the output terminal of the comparator; if the number of multiple groups of clock signals is a, the operating frequency of the column counter is adjusted to a times the original operating frequency.

8. An image sensor, characterized in that: The image sensor includes: a pixel circuit, a digital logic circuit and the analog-to-digital converter as claimed in claim 7, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

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