Host backboard and valve control device

Abstract

The utility model belongs to the technical field of power distribution control, and provides a host backboard and a valve control device.The host backboard comprises a circuit bottom board, and the circuit bottom board is provided with at least two CPU board connectors and a plurality of interface board connectors; wherein different CPU board connectors and the same interface board connector are respectively connected with signal receiving and transmitting lines with the same length. Signal receiving and transmitting lines of different CPU board connectors and the same interface board connector are set to be equal in length, so that communication of different CPU boards and the same interface board can be synchronously received / transmitted, the time sequence is kept consistent, and the requirement of synchronous communication as much as possible is met. In addition, different CPU board connectors and the same interface board connector are provided with signal receiving and transmitting lines, effective communication can still be kept when a single signal receiving and transmitting line fails, and the reliability of the system is improved.

Description

Technical Field

[0001] The present application belongs to the field of power distribution control technology, and in particular relates to a host backplane and a valve control device. Background Art

[0002] The high-voltage direct-mounted energy storage valve control device is an important hub between the DC control protection and energy storage valve submodules. The controller of the valve control device communicates with the interface (i.e., I / O port) board using a low-voltage differential signaling (LVDS) bus. However, the communication between the controller and the interface board cannot meet the requirement of synchronous communication as much as possible. Utility Model Content

[0003] In view of the above problems, the present application provides a host backplane and a valve control device valve control system, aiming to solve the problem that the communication between the controller and the interface board of the valve control device cannot meet the requirement of as synchronous communication as possible.

[0004] In a first aspect, an embodiment of the present application provides a host backplane, comprising a circuit base plate, wherein at least two CPU board connectors and a plurality of interface board connectors are provided on the circuit base plate;

[0005] Wherein, different CPU board connectors and the same interface board connector are respectively connected to signal transceiver lines with the same routing length.

[0006] In the technical solution of the embodiments of the present application, by setting the signal transceiver lines of different CPU board connectors and the same interface board connector to be of equal length, communications between different CPU boards and the same interface board can be received and delivered as synchronously as possible, maintaining consistent timing and meeting the requirement for as synchronous communication as possible, thereby meeting higher-speed communication requirements. Furthermore, since different CPU board connectors and the same interface board connector both have signal transceiver lines, effective communication can be maintained even if a single signal transceiver line fails, thereby improving system reliability.

[0007] In some embodiments, the equal-length signal transceiver lines include equal-length signal transmission lines and equal-length signal reception lines.

[0008] In the technical solution of the embodiment of the present application, the signal transceiver lines of equal length between different CPU board connectors and the same interface board connector are composed of mutually independent signal sending lines and signal receiving lines, which can realize serial communication with low power consumption and low bit error rate.

[0009] In some embodiments, the signal transceiver circuit includes copper cladding arranged on the circuit substrate. In the technical solution of the embodiment of the present application, an implementation of a signal transceiver circuit is provided.

[0010] In some embodiments, the copper cladding includes meandering traces.

[0011] In the technical solution of the embodiment of the present application, the copper cladding of the bent traces is used on the circuit board to arrange signal sending lines and signal receiving lines of equal length, thereby saving space on the circuit board.

[0012] In some embodiments, a gap is provided between the meandering trace and the CPU board connector and the interface board connector, thereby reducing interference between the meandering trace and the CPU board connector and the interface board connector during communication and improving communication reliability.

[0013] In some embodiments, the signal transceiver circuit includes a connecting cable connected to the circuit board.

[0014] In the technical solution of the embodiment of the present application, another implementation method of the signal transceiver circuit is provided.

[0015] In some embodiments, the signal transmission line includes a pair of differential signal transmission lines, and the signal receiving line includes a pair of differential signal receiving lines.

[0016] In the technical solution of the embodiment of the present application, a signal transmission line communication method of a low voltage differential signal is provided.

[0017] In some embodiments, two of the CPU board connectors are included.

[0018] In the technical solution of the embodiment of the present application, a host backplane with dual CPU boards is provided to provide sufficient computing power and reliability.

[0019] In some embodiments, the two CPU board connectors are arranged in a middle area of ​​the circuit base plate.

[0020] In the technical solution of the embodiment of the present application, the signal receiving and transmitting lines from the CPU board connector to the interface board connectors on opposite sides or surrounding areas are arranged to be of equal length.

[0021] In some embodiments, the plurality of interface board connectors are distributed on opposite sides of or around the two CPU board connectors.

[0022] In the technical solution of the embodiment of the present application, the symmetrical structural layout can meet the requirement of the CPU board or the interface board being interchangeable at any time, thereby improving the redundancy of the system and facilitating the arrangement of the signal receiving and transmitting lines of the CPU board connector to the opposite sides or surrounding interface board connectors to be of equal length.

[0023] In some embodiments, a distance between edges of two CPU board connectors is greater than a distance between edges of two adjacent interface board connectors.

[0024] The technical solution in the embodiment of the present application is beneficial to the heat dissipation of the CPU board to which the CPU board connector is plugged.

[0025] In some embodiments, two sets of redundant signal lines are connected between each of the CPU board connectors.

[0026] In the technical solution of the embodiment of the present application, the communication reliability of the CPU boards connected by the CPU board connectors is improved.

[0027] In the second aspect, an embodiment of the present application provides a valve control device, comprising the host backplane as described above, two CPU boards and at least one interface board, the two CPU boards being respectively plugged into the two CPU board connectors of the host backplane, and the interface board being plugged into the interface board connector of the host backplane.

[0028] In the technical solution of the embodiment of the present application, the host backplane of the valve control device sets the signal receiving and transmitting lines of different CPU board connectors and the same interface board connector to be of equal length, so that the communication between different CPU boards and the same interface board can be received / delivered as synchronously as possible, the timing can be kept consistent, and the requirement of synchronous communication can be achieved, thereby improving the reliability of the valve control device.

[0029] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0031] Figure 1 A schematic structural diagram of a host backplane provided in one embodiment of the present application is shown;

[0032] Figure 2 A schematic diagram of the circuit board structure of a host backplane provided in one embodiment of the present application is shown;

[0033] Figure 3 A schematic diagram of the circuit board structure of a host backplane provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0036] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0037] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0039] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0040] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0041] According to some embodiments of the present application, referring to Figure 1 , Figure 1 A schematic diagram of the structure of a host backplane provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0042] The host backplane 10 can be used in a high-voltage, direct-mounted energy storage valve control device (hereinafter referred to as the valve control device), which is a key hub between the DC control protection and energy storage valve submodules. The host backplane 10 includes a circuit baseboard 100, which is equipped with at least two central processing unit (CPU) board connectors 111 and 112 and multiple interface board connectors 121 to 124. Signal transceiver lines 130 with equal routing lengths are connected to the different CPU board connectors 111 and 112 and the same interface board connectors 121 / 122 / 123 / 124.

[0043] The circuit board 100 is generally a conventional printed circuit board (PCB). The CPU board is a control board or communication board for installing the CPU, and the CPU board connector 111 is used to plug in the CPU board. Figure 1 Four interface board connectors are shown, namely interface board connector 121, interface board connector 122, interface board connector 123, and interface board connector 124; interface board connectors 121 to 124 complete the start and stop operation, control and protection functions of the energy storage sub-module energy storage valve through optical fiber communication, providing reliable communication control for the energy storage sub-module.

[0044] In the technical solution of the embodiment of the present application, by setting the signal transceiver lines 130 of different CPU board connectors 111 and 112 and the same interface board connector 121 / 122 / 123 / 124 to be of equal length, communications between different CPU boards and the same interface board can be received / delivered as synchronously as possible, maintaining consistent timing, and achieving the requirement of as synchronous communication as possible, thereby meeting higher-speed communication requirements. Signal transceiver lines 130 can be serial or parallel communication lines.

[0045] In addition, different CPU board connectors 111 and 112 and the same interface board connector 121 / 122 / 123 / 124 all have signal transceiver lines 130, which can maintain effective communication when a single signal transceiver line 130 fails, thereby improving system reliability.

[0046] The signal transceiver circuit 130 includes a signal transmission circuit and a signal reception circuit.

[0047] In some embodiments, the signal transmission line and signal receiving line connected to a CPU board connector and an interface board connector are the same wire. In this case, the signal transmission line and signal receiving line connected to the same interface board connector 121 / 122 / 123 / 124 by different CPU board connectors 111 and 112 are of equal length.

[0048] According to some embodiments of the present application, referring to Figure 2 and Figure 3 , Figure 2 FIG2 shows a schematic structural diagram of a host backplane provided by an embodiment of the present application. Figure 3 A schematic diagram of the structure of a host backplane provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to this embodiment are shown, which are described in detail as follows:

[0049] In some embodiments, the signal transmission line and signal reception line connecting a CPU board connector to an interface board connector are different wires. For example, the equal-length signal transmission and reception lines 130 include equal-length signal transmission lines TX1 to TX4 and equal-length signal reception lines RX1 to RX4. This allows the communication between CPU boards plugged into different CPU board connectors 111 and 112 and the interface board plugged into the same interface board connector 121 / 122 / 123 / 124 to be as synchronized as possible, maintaining consistent timing. In addition, the equal-length signal transmission and reception lines 130 are composed of mutually independent signal transmission lines TX1 to TX4 and signal reception lines RX1 to RX4, which can achieve serial communication with low power consumption and low bit error rate.

[0050] According to some embodiments of this application, please continue to refer to Figure 2 and Figure 3 The signal transceiver circuit 130 includes copper cladding arranged on the circuit substrate 100. The copper cladding is the copper cladding of the PCB board, which can be composed of straight copper cladding and / or curved copper cladding. According to some embodiments of the present application, the copper cladding includes a curved trace.

[0051] like Figure 2As shown, the signal transmitting line TX1 connects the CPU board connector 111 and the interface board connector 121, the signal transmitting line TX2 connects the CPU board connector 112 and the interface board connector 121, and the signal transmitting line TX1 and the signal transmitting line TX2 are of equal length; the signal receiving line RX1 connects the CPU board connector 111 and the interface board connector 121, the signal receiving line RX2 connects the CPU board connector 112 and the interface board connector 121, and the signal transmitting line RX1 and the signal transmitting line RX2 are of equal length.

[0052] The distance between CPU board connector 111 and interface board connector 121 is shorter than the distance between CPU board connector 112 and interface board connector 121. Therefore, to ensure that signal transmission line TX1 and signal transmission line TX2 are of equal length, a meandering trace 131 is provided on signal transmission line TX1. Similarly, a meandering trace 132 is provided on signal reception line RX1, thereby saving space on circuit board 100.

[0053] like Figure 3 As shown, the signal transmitting line TX3 connects the CPU board connector 111 and the interface board connector 122, the signal transmitting line TX4 connects the CPU board connector 112 and the interface board connector 122, and the signal transmitting line TX3 and the signal transmitting line TX4 are of equal length; the signal receiving line RX3 connects the CPU board connector 111 and the interface board connector 122, the signal receiving line RX3 connects the CPU board connector 112 and the interface board connector 122, and the signal transmitting line RX3 and the signal transmitting line RX4 are of equal length.

[0054] The distance between the CPU board connector 111 and the interface board connector 122 is shorter than the distance between the CPU board connector 112 and the interface board connector 122. Therefore, to ensure that the signal transmission line TX3 and the signal transmission line TX4 are of equal length, a meandering trace 133 is provided on the signal transmission line TX3; similarly, a meandering trace 134 is provided on the signal reception line RX3, thereby saving space on the circuit board 100.

[0055] According to some embodiments of the present application, a gap is provided between the zigzag traces and the CPU board connectors 111, 112 and the interface board connectors 121 / 122 / 123 / 124. This improves interference isolation between the zigzag traces and the CPU board connectors 111, 112 and the interface board connectors 121 / 122 / 123 / 124 during communication, reduces mutual interference, and improves communication reliability.

[0056] According to some embodiments of the present application, the signal transceiver circuit 130 includes a connecting cable connected to the circuit board 100. The connecting cable is, for example, made based on a flexible printed circuit (FPC) or other balanced cables.

[0057] According to some embodiments of this application, please continue to refer to Figure 2 and Figure 3 The signal transmission lines TX1 to TX4 of equal length comprise a pair of differential signal transmission lines, and the signal receiving lines RX1 to RX4 comprise a pair of differential signal receiving lines. In the technical solution of the embodiment of the present application, the host backplane 10 provides an LVDS signal transmission line communication method with low power consumption and low bit error rate.

[0058] According to some embodiments of this application, please continue to refer to Figures 1 to 3 The host backplane 10 includes two CPU board connectors 111 and 112. In the technical solution of the embodiment of the present application, a host backplane 10 with two CPU boards is provided to provide sufficient computing power and reliability.

[0059] According to some embodiments of this application, please continue to refer to Figures 1 to 3 The two CPU board connectors 111 and 112 are arranged in the middle area of ​​the circuit base plate 100 ; the plurality of interface board connectors 121 - 124 are distributed on opposite sides or around the two CPU board connectors 111 and 112 .

[0060] In the technical solution of the embodiment of the present application, the signal transceiver lines 130 of the CPU board connectors 111 and 112 to the interface board connectors 121 to 124 on the opposite sides or the surrounding areas are arranged to be of equal length, and the symmetrical structural layout can meet the requirement that the CPU board or the interface board can be interchanged at any time, thereby improving the redundancy of the system.

[0061] According to some embodiments of this application, please continue to refer to Figure 2 and Figure 3 The distance between the edges of the two CPU board connectors 111 and 112 is greater than the distance between the edges of two adjacent interface board connectors, which is beneficial to heat dissipation of the CPU board to which the CPU board connectors 111 and 112 are plugged.

[0062] According to some embodiments of this application, please continue to refer to Figure 1 Two sets of redundant signal lines are connected between each CPU board connector 111, 112.

[0063] In the technical solution of the embodiment of the present application, two sets of redundant signal lines are set between each CPU board connector 111, 112 to improve the communication reliability of the CPU board plugged into each CPU board connector 111, 112.

[0064] It is understandable that the above-mentioned equal length lines should be relatively equal. Through some tests, it is known that the line length error is related to the signal transmission rate, for example:

[0065] When the signal transmission rate is less than 1 Gbps, the line length error between the two lines is allowed to be: ±0.5mm.

[0066] When the signal transmission rate is 1Gbps to 10Gbps, the line length error between the two lines is allowed to be: ±0.25mm.

[0067] When the signal transmission rate is greater than 10Gbps, the line length error between the two lines is allowed to be: ±0.125mm.

[0068] In the second aspect, an embodiment of the present application provides a valve control device, including the host backplane 10 as above, two CPU boards and at least one interface board, the two CPU boards are respectively plugged into the two CPU board connectors 111 and 112 of the host backplane 10, and the interface board is plugged into the interface board connectors 121~124 of the host backplane 10.

[0069] According to some embodiments of the present application, each interface board and each energy storage submodule require two-way communication, so that effective control of the energy storage submodule can still be maintained when a single line of the control system fails.

[0070] In the technical solution of the embodiment of the present application, the host backplane 10 and the valve control device have at least the following functions or effects:

[0071] The same CPU board can be interchanged between the two CPU board connectors 111 , and the data of the two CPU boards can maintain normal communication.

[0072] It can achieve high-speed differential signal communication between each CPU board and each interface board, and each interface board can achieve dual-channel communication redundant control with two CPU boards.

[0073] The same interface board can be inserted into all interface board connectors 121 to 124 and realize dual-path communication redundant control with two CPU boards.

[0074] The signal transmission delay from the same interface board to two CPU boards can be made the same, ensuring timing consistency.

[0075] A set of valve control devices only requires one type of CPU board and one type of interface board to meet the device installation requirements, effectively reducing the number of board types.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A host backplane, characterized in that: The circuit board comprises a circuit base plate, wherein at least two CPU board connectors and a plurality of interface board connectors are provided on the circuit base plate; Wherein, different CPU board connectors and the same interface board connector are respectively connected to signal transceiver lines with the same routing length.

2. The host backplane according to claim 1, wherein: The signal transceiver lines of equal length include signal sending lines of equal length and signal receiving lines of equal length.

3. The host backplane according to claim 1 or 2, wherein: The signal transceiver circuit includes copper cladding arranged on the circuit base plate.

4. The host backplane according to claim 3, wherein: The copper cladding includes a meandering trace.

5. The host backplane according to claim 4, wherein: There is a gap between the meandering line and the CPU board connector and the interface board connector.

6. The host backplane according to claim 1 or 2, characterized in that: The signal transceiver circuit includes a connecting cable connected to the circuit base plate.

7. The host backplane according to claim 2, wherein: The signal transmission circuit includes a pair of differential signal transmission circuits, and the signal receiving circuit includes a pair of differential signal receiving circuits.

8. The host backplane according to claim 1 or 2, wherein: Includes two of the CPU board connectors.

9. The host backplane according to claim 8, wherein: The two CPU board connectors are arranged in the middle area of ​​the circuit base plate.

10. The host backplane according to claim 9, wherein: The plurality of interface board connectors are distributed on opposite sides or around the two CPU board connectors.

11. The host backplane according to claim 10, wherein: The distance between the edges of two CPU board connectors is greater than the distance between the edges of two adjacent interface board connectors.

12. The host backplane according to claim 1, wherein: Two groups of redundant signal lines are connected between the CPU board connectors.

13. A valve control device, characterized in that: It comprises a host backplane as described in any one of claims 1 to 12, two CPU boards and at least one interface board, the two CPU boards are respectively plugged into the two CPU board connectors of the host backplane, and the interface board is plugged into the interface board connector of the host backplane.

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