Photovoltaic cell and photovoltaic module

Abstract

The utility model provides a photovoltaic cell and a photovoltaic assembly, relates to the field of photovoltaic technology, and aims to solve the technical problem that the photovoltaic cell cannot be prevented from being short-circuited while the photoelectric conversion efficiency of the photovoltaic cell is improved. The photovoltaic cell comprises a substrate, an intrinsic silicon-containing layer, a doped silicon-containing layer and a conductive layer, the intrinsic silicon-containing layer, the doped silicon-containing layer and the conductive layer are sequentially stacked on the substrate, the surface, away from the substrate, of the doped silicon-containing layer is provided with a first area and a second area surrounding the first area, and the second area is located at the circumferential edge of the surface of the substrate; the conductive layer comprises a first part stacked on the first region and a second part stacked on the second region; and the thickness of the first part is greater than that of the second part. The photovoltaic cell provided by the utility model can avoid edge short circuit while the photoelectric conversion efficiency is maximized.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaics, in particular to a photovoltaic cell and a photovoltaic module. Background Art

[0002] The statements in this section merely provide background technology related to the present invention and do not necessarily constitute prior art.

[0003] Heterojunction (HJT) cells are made by depositing an intrinsic α-Si:H layer on the front and back sides of an n-type silicon wafer, followed by preparing a p-type α-Si:H layer and an n-type α-Si:H layer, respectively. Low-temperature silver paste is then screen-printed and dried to form the resulting cell. In actual production, a transparent conductive oxide (TCO) film can also be deposited on the silicon wafer surface before low-temperature silver paste printing, which is then cured to form the gate.

[0004] In related technologies, when TCO films are stacked on both the front and back sides of a heterojunction battery using coating technology, it is inevitable that the front and back TCO films will short-circuit at the edges, affecting the photoelectric conversion efficiency of the heterojunction battery. Utility Model Content

[0005] The purpose of the utility model is to provide a photovoltaic cell and a photovoltaic module to solve the technical problem that the photovoltaic cell cannot avoid short circuit while improving the photoelectric conversion efficiency.

[0006] In order to achieve the above purpose, the present invention provides the following technical solutions:

[0007] In a first aspect, the utility model provides a photovoltaic cell comprising a substrate and an intrinsic silicon-containing layer, a doped silicon-containing layer and a conductive layer sequentially stacked on the substrate.

[0008] The doped silicon-containing layer has a first region on a surface facing away from the substrate and a second region surrounding the first region, wherein the second region is located at a peripheral edge portion of the surface of the substrate;

[0009] The conductive layer includes a first portion stacked on the first region and a second portion stacked on the second region;

[0010] The thickness of the first portion is greater than the thickness of the second portion.

[0011] According to at least one embodiment of the present invention, the thickness of the second portion is greater than zero and less than or equal to 10 nm.

[0012] According to at least one embodiment of the present invention, the first portion includes a first conductive portion and a second conductive portion that are stacked, and the thickness of the first conductive portion is consistent with the thickness of the second portion.

[0013] According to at least one embodiment of the present invention, the first conductive portion and the second portion are integrally formed.

[0014] According to at least one embodiment of the present invention, the first conductive portion and the second conductive portion are arranged in a direction away from the substrate; or,

[0015] The first conductive portion and the second conductive portion are arranged along a direction close to the substrate.

[0016] According to at least one embodiment of the present invention, the second conductive portion includes a stacked first conductive sub-portion and a second conductive sub-portion, and the first conductive sub-portion and the second conductive sub-portion are arranged in a direction away from the substrate;

[0017] The light transmittance of the first conductive sub-portion is greater than the light transmittance of the second conductive sub-portion, and the carrier concentration of the second conductive sub-portion is greater than the carrier concentration of the first conductive sub-portion.

[0018] According to at least one embodiment of the present invention, the conductive layer is made of one or more of indium oxide, tin oxide, zinc oxide, cadmium oxide or titanium nitride; and / or,

[0019] The conductive layer is made of a doping element, wherein the doping element comprises one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium or fluorine; and / or,

[0020] The thickness of the conductive layer ranges from 1 nm to 100 nm.

[0021] According to at least one embodiment of the present invention, the thickness of the intrinsic silicon-containing layer ranges from 1 nm to 50 nm; and / or,

[0022] The thickness of the doped silicon-containing layer ranges from 1 nm to 50 nm; and / or,

[0023] The material of the intrinsic silicon-containing layer includes one or more of microcrystalline silicon, nanosilicon, amorphous silicon, silicon oxide or silicon carbide; and / or,

[0024] The material of the doped silicon-containing layer includes one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide, and the doping element includes phosphorus or boron.

[0025] According to at least one embodiment of the present invention, a surface of the substrate adjacent to the intrinsic silicon-containing layer has a textured structure.

[0026] In a second aspect, the present invention provides a photovoltaic assembly comprising a plurality of electrically connected photovoltaic cells, at least one of which is the photovoltaic cell described in the first aspect.

[0027] One or more technical solutions provided in the exemplary embodiments of the present invention can achieve at least one of the following beneficial effects.

[0028] The photovoltaic cell of the exemplary embodiment of the present utility model has an intrinsic silicon-containing layer, a doped silicon-containing layer and a conductive layer stacked on one side of the substrate, wherein the surface of the doped silicon-containing layer facing the conductive layer is composed of a first region located in the central part and a second region located in the circumferential edge part. The first part of the conductive layer covers the first region, and the second part covers the second region. When the thickness of the second part located in the edge part is sufficiently small relative to the thickness of the first part, during the formation of the conductive layer, the conductive layers on both sides of the substrate will not be conductive at the edge. At the same time, since the conductive layer (the first part and the second part) covers the entire surface of the substrate, that is, the edge of the conductive layer can be flush with the edge of the substrate, there is no need to set a distance between the edge of the conductive layer and the edge of the substrate as in the prior art, which can maximize the carrier collection efficiency. Based on this, the photovoltaic cell of the exemplary embodiment of the present utility model can avoid the problem of edge leakage while maximizing the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. These drawings are included to provide a further understanding of the present invention, and are included in and constitute a part of this specification.

[0030] Figure 1 It is a schematic diagram of the structure of a heterojunction photovoltaic cell in the prior art;

[0031] Figure 2 is a schematic structural diagram of a photovoltaic cell according to an embodiment of the present utility model;

[0032] Figure 3 is a schematic structural diagram of a photovoltaic cell according to another embodiment of the present utility model;

[0033] Figure 4 It is a schematic structural diagram of a photovoltaic cell according to another embodiment of the present utility model.

[0034] Figure numerals: 10, substrate; 20, intrinsic silicon-containing layer; 30, doped silicon-containing layer; 40, conductive layer; 41, first part; 42, second part; 411, first conductive part; 412, second conductive part; 412a, first conductive sub-part; 412b, second conductive sub-part; 50, gate. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] Before introducing the embodiments of the present invention, the following definitions are given for the relevant terms involved in the embodiments of the present invention:

[0037] In photovoltaic cells and other optoelectronic devices, fill factor (FF) measures the impact of internal resistance and electron loss on their performance. A characteristic of the current-voltage (IV) curve, fill factor represents the ratio of the maximum output power (ImVm) to the limiting output power (IscVoc), i.e., FF = ImVm / IscVoc.

[0038] The fill factor ranges from 0 to 1, with values ​​closer to 1 indicating better performance. The fill factor is primarily determined by series resistance, shunt resistance, and PN junction characteristics. Increased series resistance, decreased shunt resistance, and the presence of defects and impurities in the PN junction all contribute to a smaller FF. Furthermore, the fill factor increases with the bandgap of the cell material.

[0039] Short Circuit Current Density (Jsc) refers to the current density per unit area generated by a photovoltaic cell in a short-circuit state. In the short-circuit state, the two electrodes of the photovoltaic cell are directly connected together without external load. Its value is expressed as the intercept on the vertical axis of the JV curve diagram, and the unit is mA / cm 2 Jsc is primarily affected by the incident light intensity and the material's absorption bandgap. The smaller the bandgap, the greater the ability to convert photons into electrical energy. Additionally, device thickness, the quality of each film layer, and carrier transport capacity all have an impact on Jsc.

[0040] Open-circuit voltage (Voc) refers to the voltage difference between the two electrodes of a photovoltaic cell when no load is connected. The specific value of open-circuit voltage is represented by the intercept length on the horizontal axis of the JV curve diagram, and its units are generally mV or V.

[0041] The calculation of conversion efficiency ETA (η) is usually used to measure the ability of photovoltaic cells to convert solar energy into electrical energy. Photovoltaic cell conversion efficiency η = (electrical energy generated by the cell / solar radiation energy irradiating the cell) × 100%.

[0042] Figure 1 It is a schematic diagram of the structure of heterojunction photovoltaic cells in the prior art. Figure 1 As shown, in the actual production of heterojunction photovoltaic cells, it is necessary to deposit a TCO film on the surface (front / back) of the substrate 10, and then prepare a metal gate 50 on the TCO film. Due to the limitations of the TCO film preparation process, when the TCO film is stacked on the entire front / back of the substrate 10, it is unavoidable that the two layers of TCO films on the front / back are conductive at the peripheral edges of the substrate 10, that is, short circuit or leakage at the edge. In order to prevent the above situation from occurring, a certain distance needs to be formed between the edge of the TCO film on the front and / or back and the edge of the substrate 10. Since the TCO film is not stacked on the entire surface of the substrate 10, it will affect the current collection ability of the photovoltaic cell, that is, to a certain extent reduce the photoelectric conversion efficiency of the heterojunction photovoltaic cell.

[0043] To address the aforementioned issues, the photovoltaic cell provided by the exemplary embodiments of the present invention achieves a full-surface stacking of the TCO film on the back of the heterojunction photovoltaic cell by thinning the portion near the peripheral edges and thickening the portion in the middle region. During the formation process, the portion of the TCO film near the peripheral edges is too thin to cause conduction between the front and back TCO films. This avoids the edge conduction problem of the TCO film while ensuring that the TCO film is stacked entirely on the substrate 10, maximizing the photoelectric conversion efficiency of the heterojunction photovoltaic cell.

[0044] Figure 2 Schematic diagram of the structure of a photovoltaic cell according to an embodiment of the present invention. Figure 2 As shown, the photovoltaic cell provided by the exemplary embodiment of the present invention includes a substrate 10, and an intrinsic silicon-containing layer 20, a doped silicon-containing layer 30, and a conductive layer 40 stacked sequentially on the substrate 10. The doped silicon-containing layer 30 has a first region and a second region surrounding the first region on a surface facing away from the substrate 10. The second region is located at the circumferential edge of the surface of the substrate 10. The conductive layer 40 includes a first portion 41 stacked on the first region and a second portion 42 stacked on the second region. The thickness of the first portion 41 is greater than that of the second portion 42. The thickness direction refers to the arrangement direction of the intrinsic silicon-containing layer 20, the doped silicon-containing layer 30, and the conductive layer 40.

[0045] In actual applications, the front side of the photovoltaic cell is sequentially stacked with an intrinsic silicon-containing layer 20, a doped silicon-containing layer 30, and a conductive layer 40 stacked entirely on the doped silicon-containing layer 30. The thickness of the conductive layer 40 is relatively uniform. The back side is also sequentially stacked with an intrinsic silicon-containing layer 20, a doped silicon-containing layer 30, and a conductive layer 40 stacked entirely on the doped silicon-containing layer 30. The conductive layer 40 on the back side differs from the conductive layer 40 on the front side in that the conductive layer 40 is formed by a first portion 41 and a second portion 42. The first portion 41 is formed on a first region of the doped silicon-containing layer 30, that is, on the majority of the region located in the center. The second portion 42 is formed on a second region of the doped silicon-containing layer 30, that is, on a small portion of the surface of the doped silicon-containing layer 30 near the circumferential edge. In other words, there is a certain distance between the circumferential edge of the first portion 41 and the circumferential edge of the substrate 10.

[0046] Because the thickness of the second portion 42 is less than that of the first portion 41, for example, when the thickness of the second portion 42 is greater than zero and less than or equal to 10nm, for example, it can be 0.1nm, 0.5nm, 1nm, 3nm, 5nm, 7nm, or 9nm, in actual production, it is difficult for the conductive layer 40 prepared by coating technology to have conductivity at the edge. Furthermore, the conductive layer 40 composed of the first portion 41 and the second portion 42 covers the entire surface of the substrate 10, which can also maximize the photoelectric conversion efficiency of the photovoltaic cell.

[0047] Exemplarily, the conductive layer 40 may be a TCO film, which is a multilayer or stacked layer or mixture structure of one or more doped metal oxides or nitrides. The metal oxide may be indium oxide, tin oxide, zinc oxide, cadmium oxide, or titanium nitride. The metal nitride may be titanium nitride. The doping elements may be indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine, and the like.

[0048] Illustratively, the thickness of the first portion 41 may be 1 nm to 100 nm, for example, 5 nm, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 90 nm.

[0049] In some embodiments, the first portion 41 includes a stacked first conductive portion 411 and a second conductive portion 412, and the thickness of the first conductive portion 411 is consistent with the thickness of the second portion 42. Exemplarily, the first conductive portion 411 and the second portion 42 are integrally formed.

[0050] For example, if Figure 2As shown, the conductive layer 40 has a stacked structure, wherein a first conductive portion 411 and a second conductive portion 412 are arranged in a direction away from the substrate 10. The first conductive portion 411 and the second portion 42 are integrally formed through a deposition process to form a relatively thin layer covering the entire surface of the doped silicon-containing layer 30. The second conductive portion 412 is deposited and covers the first conductive portion 411. The two together form the first portion 41 of the conductive layer 40. That is, the peripheral edge of the second conductive portion 412 is spaced a certain distance from the peripheral edge of the substrate 10, and the layer formed by the first conductive portion 411 and the second portion 42 can be flush with the peripheral edge of the substrate 10. Thus, the stacked first conductive portion 411 and the second conductive portion 412 form the first portion 41. The first portion 41 and the second portion 42 surrounding the first portion 41 together form the conductive layer 40 on the back side of the substrate 10.

[0051] Figure 3 Schematic diagram of the structure of a photovoltaic cell according to another embodiment of the present invention. Figure 3 As shown, the conductive layer 40 on the back of the photovoltaic cell is a laminated structure, with the first portion 41 comprising a first conductive portion 411 and a second conductive portion 412 stacked together. The thickness of the first conductive portion 411 is consistent with the thickness of the second portion 42. The first conductive portion 411 and the second conductive portion 412 are arranged in a direction close to the substrate 10.

[0052] In practical applications, a deposition process is first performed on the first region of the doped silicon-containing layer 30 to form the second conductive portion 412. Subsequently, a deposition process is performed on the entire surface of the doped silicon-containing layer 30, including the first and second regions, to integrally form the first conductive portion 411 and the second portion 42. In other words, the peripheral edges of the second conductive portion 412 are spaced a certain distance from the peripheral edges of the substrate 10. The thinner conductive layer 40 formed by the first conductive portion 411 and the second portion 42 completely wraps around the surface of the second conductive portion 412 that faces away from the doped silicon-containing layer 30 and the peripheral side surfaces. Thus, the stacked first conductive portion 411 and the second conductive portion 412 form the first portion 41. The first portion 41 and the second portion 42 surrounding the first portion 41 together form the conductive layer 40 on the back side of the substrate 10.

[0053] Figure 4 FIG is a schematic diagram of the structure of a photovoltaic cell according to another embodiment of the present invention. Figure 4 As shown, the conductive layer 40 on the back of the photovoltaic cell is a three-layer stacked structure. The first portion 41 includes a stacked first conductive portion 411 and a second conductive portion 412. The thickness of the first conductive portion 411 is consistent with the thickness of the second portion 42. The first conductive portion 411 and the second conductive portion 412 are arranged in a direction away from the substrate 10.

[0054] The second conductive portion 412 includes a stacked first conductive sub-portion 412 a and a second conductive sub-portion 412 b . The first conductive sub-portion 412 a and the second conductive sub-portion 412 b are arranged in a direction away from the substrate 10 .

[0055] In actual application, the first conductive part 411 and the second part 42 are integrally formed by a deposition process to form a thin layer covering the entire surface of the doped silicon-containing layer 30; a layer of the first conductive sub-part 412a is covered on the first conductive part 411 by a deposition process, and then a layer of the second conductive sub-part 412b is covered on the first conductive sub-part 412a by a deposition process; the first conductive sub-part 412a and the second conductive sub-part 412b form the second conductive part 412, and the second conductive part 412 and the first conductive part 411 form the first part 41 of the conductive layer 40, that is, the peripheral edge of the second conductive part 412 (the first conductive sub-part 412a and the second conductive sub-part 412b) has a certain distance from the peripheral edge of the substrate 10, and the layer formed by the first conductive part 411 and the second part 42 can be flush with the peripheral edge of the substrate 10. Thus, the stacked first conductive part 411 and the second conductive part 412 (formed by the stacked first conductive sub-part 412a and the second conductive sub-part 412b) form a first part 41, and the first part 41 and the second part 42 surrounding the first part 41 together form a conductive layer 40 on the back side of the substrate 10.

[0056] Exemplarily, the transmittance of the first conductive sub-portion 412 a is greater than the transmittance of the second conductive sub-portion 412 b , and the carrier concentration of the second conductive sub-portion 412 b is greater than the carrier concentration of the first conductive sub-portion 412 a .

[0057] In actual production, during the formation of the first conductive electronic portion 412a, the amount of oxygen doped can be increased to reduce the light absorption of the film in the near-infrared band, thereby improving the light transmittance; during the formation of the second conductive electronic portion 412b, the amount of hydrogen doped can be increased to give the layer a higher carrier concentration.

[0058] Exemplarily, the deposition process required to form the intrinsic silicon-containing layer 20, the doped silicon-containing layer 30 and the conductive layer 40 can be prepared in sequence by any one of vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD), or a combination of multiple deposition methods.

[0059] In some embodiments, the thickness of the intrinsic silicon-containing layer 20 on the front and back sides of the photovoltaic cell of the exemplary embodiment of the present invention ranges from 1 nm to 50 nm. For example, the intrinsic silicon-containing layer 20 is made of one or more of microcrystalline silicon, nanosilicon, amorphous silicon, silicon oxide, or silicon carbide, and can be a single layer with the same properties, a multilayer with different properties, a stack of several layers, or a mixed silicon-containing thin film layer.

[0060] In some embodiments, the thickness of the doped silicon-containing layer 30 of the photovoltaic cell of the exemplary embodiment of the present invention ranges from 1 nm to 50 nm; exemplarily, the material of the doped silicon-containing layer 30 includes one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide, and can be a single layer with the same performance or a multilayer with different performance or several stacked or mixed silicon-containing thin film layers, and the doping elements include phosphorus or boron.

[0061] For example, the doped silicon-containing layer 30 on the front side of the photovoltaic cell of the exemplary embodiment of the present invention is an n-type doped silicon-containing thin film layer with phosphorus as the doping element, while the doped silicon-containing layer 30 on the back side is a p-type doped silicon-containing thin film layer with boron as the doping element.

[0062] In some embodiments, the material of the conductive layer 40 on the front side of the photovoltaic cell of the exemplary embodiment of the present invention is the same as that of the conductive layer 40 on the back side, which will not be described in detail here, and the thickness is 1 nm to 100 nm.

[0063] In some embodiments, a velvet structure is further formed on the surface of the photovoltaic cell of the exemplary embodiment of the present invention before stacking the intrinsic silicon-containing layer 20. The velvet structure can be formed on one or both of the back and front sides of the substrate 10, so that the conductive layer 40 formed on the back or front side also has a velvet structure to increase the light trapping effect.

[0064] The following examples and comparative examples are given to illustrate the technical effects of the photovoltaic cells of the exemplary embodiments of the present invention.

[0065] Example 1

[0066] like Figure 2 As shown, the substrate 10 is an n-type silicon substrate, wherein the front and back surfaces of the silicon substrate have a suede structure, wherein the front surface is the light-receiving surface of the silicon substrate, and the back surface is the backlight surface of the silicon substrate.

[0067] The front surface of the substrate 10 is provided with an intrinsic silicon-containing layer 20 , an n-type doped silicon-containing layer 30 , a conductive layer 40 and a metal gate 50 in sequence from the inside to the outside. The conductive layer 40 entirely covers the front surface of the substrate 10 .

[0068] The intrinsic silicon-containing layer 20 on the front side is an amorphous silicon thin film with a thickness of 3 nm to 10 nm.

[0069] The front n-type doped silicon-containing layer 30 is a microcrystalline (nano, amorphous silicon) silicon-containing thin film, the doping element is phosphorus, and the thickness thereof is 3 nm to 20 nm.

[0070] The front conductive layer 40 is doped indium oxide metal oxide, and its thickness is 30 nm to 100 nm.

[0071] The metal gate 50 on the front side is a silver electrode.

[0072] The back side of the substrate 10 is provided with an intrinsic silicon-containing layer 20 , a p-type doped silicon-containing layer 30 , a conductive layer 40 and a metal gate 50 in sequence from the inside to the outside.

[0073] The back conductive layer 40 is formed by a first portion 41 and a second portion 42. The first portion 41 is formed on the first region of the n-type doped silicon-containing layer 30, and the second portion 42 is formed on the second region of the doped silicon-containing layer 30. The first portion 41 is provided with a first conductive portion 411 and a second conductive portion 412 from the inside out. The first conductive portion 411 and the second portion 42 are formed as a single layer, the entire surface of which covers the n-type doped silicon-containing layer 30. The second conductive portion 412 is a separate layer, which is stacked on the first conductive portion 411. That is, the peripheral edge of the second conductive portion 412 is a certain distance from the peripheral edge of the substrate 10. The thickness of the first conductive portion 411 and the second portion 42 is greater than zero and less than or equal to 10 nm.

[0074] The intrinsic silicon-containing layer 20 on the back side is an amorphous silicon thin film with a thickness of 5 nm to 15 nm.

[0075] The p-type doped silicon-containing layer 30 on the back side is a microcrystalline (nano, amorphous silicon) thin film, the doping element is boron, and the thickness thereof is 8 nm to 20 nm.

[0076] The conductive layer 40 on the back side is a doped indium oxide (tin oxide) thin film with a thickness of 50 nm to 100 nm.

[0077] The metal gate 50 on the back side is a silver electrode.

[0078] Example 2

[0079] like Figure 3 As shown, the difference between this embodiment and embodiment 1 is only that:

[0080] In the conductive layer 40 on the back side, the second conductive part 412 is stacked on the first area of ​​the n-type doped silicon-containing layer 30, and the first conductive part 411 covers the second conductive part 412. Since the first conductive part 411 and the second part 42 are an integrally formed layer, this layer is completely wrapped around the second conductive part 412 during the deposition process, that is, the surface of the second conductive part 412 facing away from the n-type doped silicon-containing layer 30 and the surrounding side surfaces are covered with the layer formed by the first conductive part 411 and the second part 42.

[0081] Example 3

[0082] like Figure 4 As shown, the difference between this embodiment and embodiment 1 is only that:

[0083] The second conductive part 412 is a stacked structure, including a stacked first conductive sub-part 412a and a second conductive sub-part 412b from the inside to the outside. During the deposition of the second conductive part 412, the first conductive sub-part 412a has a higher oxygen doping amount than the second conductive sub-part 412b, and the first conductive sub-part 412a has better light transmittance; the second conductive sub-part 412b has a higher hydrogen doping amount than the first conductive sub-part 412a, and the second conductive sub-part 412b has a higher carrier concentration.

[0084] Comparative Example 1

[0085] like Figure 1 As shown, the difference between this comparative example and Example 1 is only that:

[0086] The back conductive layer 40 is a single-layer structure, which is stacked on the first region of the doped silicon-containing layer 30 .

[0087] Comparative Example 2

[0088] The difference between this comparative example and Example 1 is only that:

[0089] In the conductive layer 40 on the back surface, the thickness of the first conductive portion 411 and the second portion 42 are both 20 nm.

[0090] Table 1 Electrical performance data of various embodiments and comparative examples

[0091] Jsc(%) Voc(%) FF(%) Eta (%) Example 1 100.29％ 99.96％ 100.13％ 100.38％ Example 2 100.22％ 100.06％ 100.15％ 100.49％ Example 3 100.54％ 100.03％ 100.14％ 100.72％ Comparative Example 2 100.56％ 100％ 99.65％ 100.07％ Comparative Example 1 100％ 100％ 100％ 100％

[0092] Table 2 Leakage current of each embodiment and comparative example

[0093] Example 1 Example 2 Example 3 Comparative Example 1 Comparative Example 2 Current (A) 0.022 0.038 0.031 0.003 0.21

[0094] As shown in Table 1, with Comparative Example 1 as a benchmark, the fill factor of Comparative Example 2 is slightly reduced, and the short-circuit current density, open-circuit voltage, and conversion efficiency are unchanged or improved; in Examples 1-3, except that the open-circuit voltage of Example 1 is slightly reduced relative to Comparative Example 1, all other electrical performance data are improved. As shown in Table 2, the leakage current of Examples 1-3 is improved relative to Comparative Example 1, but is much smaller than the leakage current of Comparative Example 2, and the weak leakage current can be ignored. When the thickness of the thinner conductive layer covering the entire back of the substrate is greater than 10nm, as shown in Comparative Example 2 with a thickness of 20nm, the leakage current is significantly increased, which makes it difficult to meet the anti-leakage requirements of the photovoltaic cell.

[0095] It can be seen from this that the photovoltaic cell provided by the exemplary embodiment of the present invention is configured by arranging the conductive layer on the back side in multiple layers so that the thinner conductive layer covers the entire back side of the substrate, specifically its thickness is less than or equal to 10nm; the relatively thicker part is stacked in a local area of ​​the substrate so that the peripheral edge of the part has a certain distance from the peripheral edge of the substrate, thereby maximizing the conversion efficiency of the photovoltaic cell while avoiding the problem of edge short circuit or leakage of the photovoltaic cell.

[0096] An exemplary embodiment of the present invention further provides a photovoltaic assembly, comprising a plurality of electrically connected photovoltaic cells, at least one of which is the photovoltaic cell described in the above embodiment.

[0097] The technical advantages of photovoltaic modules over existing technologies are consistent with the technical advantages of the photovoltaic cells in the above-mentioned embodiments, and will not be repeated here.

[0098] Those skilled in the art will appreciate that the above embodiments are merely intended to clearly illustrate the present invention and are not intended to limit the scope of the present invention. Other variations or modifications may be made based on the above disclosure, and such variations or modifications are still within the scope of the present invention.

Claims

1. A photovoltaic cell, characterized in that: It comprises a substrate and an intrinsic silicon-containing layer, a doped silicon-containing layer and a conductive layer sequentially stacked on the substrate. The doped silicon-containing layer has a first region on a surface facing away from the substrate and a second region surrounding the first region, wherein the second region is located at a peripheral edge portion of the surface of the substrate; The conductive layer includes a first portion stacked on the first region and a second portion stacked on the second region; The thickness of the first portion is greater than the thickness of the second portion.

2. The photovoltaic cell according to claim 1, characterized in that The thickness of the second portion is greater than zero and less than or equal to 10 nm.

3. The photovoltaic cell according to claim 1, characterized in that The first portion includes a first conductive portion and a second conductive portion that are stacked together, and a thickness of the first conductive portion is consistent with a thickness of the second portion.

4. The photovoltaic cell according to claim 3, characterized in that The first conductive portion and the second portion are integrally formed.

5. The photovoltaic cell according to claim 4, characterized in that The first conductive portion and the second conductive portion are arranged in a direction away from the substrate; or, The first conductive portion and the second conductive portion are arranged along a direction close to the substrate.

6. The photovoltaic cell according to claim 3, characterized in that The second conductive portion includes a first conductive sub-portion and a second conductive sub-portion stacked together, wherein the first conductive sub-portion and the second conductive sub-portion are arranged in a direction away from the substrate; The light transmittance of the first conductive sub-portion is greater than the light transmittance of the second conductive sub-portion, and the carrier concentration of the second conductive sub-portion is greater than the carrier concentration of the first conductive sub-portion.

7. The photovoltaic cell according to any one of claims 1 to 6, characterized in that: The conductive layer is made of one of indium oxide, tin oxide, zinc oxide, cadmium oxide or titanium nitride; and / or, The conductive layer is made of a doping element, wherein the doping element comprises one of indium, tin, calcium, aluminum, cadmium, zinc, cerium or fluorine; and / or, The thickness of the conductive layer ranges from 1 nm to 100 nm.

8. The photovoltaic cell according to any one of claims 1 to 6, characterized in that: The thickness of the intrinsic silicon-containing layer ranges from 1 nm to 50 nm; and / or, The thickness of the doped silicon-containing layer ranges from 1 nm to 50 nm; and / or, The material of the intrinsic silicon-containing layer includes one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or, The material of the doped silicon-containing layer includes one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide.

9. The photovoltaic cell according to any one of claims 1 to 6, characterized in that: A surface of the substrate adjacent to the intrinsic silicon-containing layer has a textured structure.

10. A photovoltaic module, characterized in that: The invention comprises a plurality of electrically connected photovoltaic cells, at least one of the photovoltaic cells is the photovoltaic cell according to any one of claims 1 to 6.

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