TBC battery structure

Abstract

The utility model relates to a TBC battery structure. The TBC battery structure comprises a semiconductor substrate, a P-doped region and an N-doped region, wherein the P-doped region and the N-doped region are arranged on the back face of the semiconductor substrate at intervals. The P-doped region comprises at least one P-region passivation contact unit, the P-region passivation contact unit comprises a P-region tunneling layer and a P-poly layer, the N-doped region comprises at least one N-region passivation contact unit, the N-region passivation contact unit comprises an N-region tunneling layer and an N-poly layer, and the total thickness of all the P-region tunneling layers in the P-doped region is greater than the total thickness of all the N-region tunneling layers in the N-doped region. The total thickness of all P-region tunneling layers in the P-doped region is greater than the total thickness of all N-region tunneling layers in the N-doped region, that is, the total thickness of the N-region tunneling layers is relatively thin, so that the tunneling probability of electrons can be improved to achieve better carrier collection efficiency; and meanwhile, the total thickness of the P-region tunneling layer is relatively large, so that the excellent passivation effect of the tunneling layer can be ensured.

Description

Technical Field

[0001] The present application relates to the technical field of TBC battery structures, and in particular to TBC battery structures. Background Art

[0002] Since full back-contact solar cells have no metal grid lines on the front surface, they are both beautiful and more efficient, making them highly competitive among various new high-efficiency solar cells.

[0003] In related technologies, in order to further improve the efficiency of the battery, back passivation contact technology is applied to Topcon batteries. As a modified version of Topcon batteries, TBC batteries can achieve higher efficiency due to the support of passivation technology.

[0004] However, electrons can tunnel through the carriers, but holes cannot. A thicker tunneling layer will affect the electron tunneling effect and reduce the carrier collection efficiency; a thinner tunneling layer will affect the passivation effect of the tunneling layer. Utility Model Content

[0005] Based on this, it is necessary to provide a TBC battery structure to address the problems that when the tunneling layer is thick, the carrier collection efficiency is low; when the tunneling layer is thin, the passivation effect of the tunneling layer is poor.

[0006] A TBC battery structure, comprising a semiconductor substrate and a P-doped region and an N-doped region spaced apart on the back side of the semiconductor substrate;

[0007] The P-doped region includes at least one P-region passivation contact unit, the P-region passivation contact unit includes a P-region tunneling layer and a P-poly layer, and the P-region tunneling layer in the same P-region passivation contact unit is located on a side of the P-poly layer close to the semiconductor substrate;

[0008] The N-doped region includes at least one N-region passivation contact unit, the N-region passivation contact unit includes an N-region tunneling layer and an N-poly layer, and the N-region tunneling layer in the same N-region passivation contact unit is located on a side of the N-poly layer close to the semiconductor substrate;

[0009] The total thickness of all the P-region tunneling layers in the P-doped region is greater than the total thickness of all the N-region tunneling layers in the N-doped region.

[0010] In one embodiment, the P-doped region includes a P-region electrode and a P-region passivation contact unit, and the P-region electrode is located on a side of the P-poly layer away from the P-region tunneling layer.

[0011] In one embodiment, the P-doped region includes a P-region electrode and two P-region passivation contact units, the two P-region passivation contact units are respectively a first P-region passivation contact unit and a second P-region passivation contact unit, the second P-region passivation contact unit is located on a side of the first P-region passivation contact unit away from the semiconductor substrate, and the P-region electrode is in contact with the P-poly layer of the second P-region passivation contact unit.

[0012] In one embodiment, the thickness of the P-region tunneling layer in the second P-region passivation contact unit is smaller than the thickness of the P-region tunneling layer in the first P-region passivation contact unit.

[0013] In one embodiment, the thickness of the P-region tunneling layer in the second P-region passivation contact unit is in the range of 0.5 nm to 0.9 nm.

[0014] In one embodiment, the N-doped region includes an N-region electrode and an N-region passivation contact unit, and the N-region electrode is located on a side of the N-poly layer away from the N-region tunneling layer.

[0015] In one embodiment, the N-doped region includes an N-region electrode and two N-region passivation contact units, the two N-region passivation contact units are respectively a first N-region passivation contact unit and a second N-region passivation contact unit, the second N-region passivation contact unit is located on a side of the first N-region passivation contact unit away from the semiconductor substrate, and the N-region electrode is in contact with the N-poly layer of the second N-region passivation contact unit.

[0016] In one embodiment, the thickness of the N-region tunneling layer in the second N-region passivation contact unit is smaller than the thickness of the N-region tunneling layer in the first N-region passivation contact unit.

[0017] In one embodiment, the thickness of the N-region tunneling layer in the second N-region passivation contact unit is 0.4 nm-0.7 nm.

[0018] In one embodiment, the total thickness of all the P-region tunneling layers in the P-doped region is 1.1 nm-2.5 nm, and the total thickness of all the N-region tunneling layers in the N-doped region is 1 nm-2 nm.

[0019] In the aforementioned TBC battery structure, the total thickness of all P-region tunneling layers in the P-doped region is greater than the total thickness of all N-region tunneling layers in the N-doped region. This means that the total thickness of the N-region tunneling layers is relatively thin, thereby increasing the probability of electron tunneling and achieving better carrier collection efficiency. At the same time, the total thickness of the P-region tunneling layers is relatively thick, thereby ensuring excellent passivation of the tunneling layers. Furthermore, the P-doped region includes at least one P-region passivation contact unit, which includes a P-region tunneling layer and a P-poly layer. The provision of multiple P-region passivation contact units is beneficial for improving the passivation quality of the P-doped region, thereby improving battery efficiency. The N-doped region includes at least one N-region passivation contact unit, which includes an N-region tunneling layer and an N-poly layer. The provision of multiple N-region passivation contact units is beneficial for improving the passivation quality of the N-doped region, thereby improving battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the TBC battery structure in the first specific embodiment.

[0021] Figure 2 Schematic diagram of the TBC battery structure in the second specific embodiment.

[0022] Figure 3 Schematic diagram of the TBC battery structure in the third specific embodiment.

[0023] Figure 4 Schematic diagram of the TBC battery structure in the fourth specific embodiment.

[0024] Figure numerals: 10, anti-reflection layer; 20, passivation layer; 30, semiconductor substrate; 40, P-doped region; 41, first P-region passivation contact unit; 42, second P-region passivation contact unit; 43, P-region tunneling layer; 44, P-poly; 45, P-region electrode; 50, N-doped region; 51, first N-region passivation contact unit; 52, second N-region passivation contact unit; 53, N-region tunneling layer; 54, N-poly; 55, N-region electrode; 60, groove region. DETAILED DESCRIPTION

[0025] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0026] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0027] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0028] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0029] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0030] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0031] See Figures 1-4 One embodiment of the present application discloses a TBC battery structure, which includes a semiconductor substrate 30 and a P-doped region 40 and an N-doped region 50 spaced apart on the back surface of the semiconductor substrate 30. The P-doped region 40 includes at least one P-region passivation contact unit, each comprising a P-region tunneling layer 43 and a P-poly layer 44. The P-region tunneling layer 43 within the same P-region passivation contact unit is located on the side of the P-poly layer 44 closer to the semiconductor substrate 30. The N-doped region 50 includes at least one N-region passivation contact unit, each comprising an N-region tunneling layer 53 and an N-poly layer 54. The N-region tunneling layer 53 within the same N-region passivation contact unit is located on the side of the N-poly layer 54 closer to the semiconductor substrate 30. The total thickness of all P-region tunneling layers 43 within the P-doped region 40 is greater than the total thickness of all N-region tunneling layers 53 within the N-doped region 50.

[0032] In this embodiment, the total thickness of all P-region tunneling layers 43 in the P-doped region 40 is greater than the total thickness of all N-region tunneling layers 53 in the N-doped region 50, that is, the total thickness of the N-region tunneling layers 53 is relatively thin, thereby increasing the tunneling probability of electrons to achieve better carrier collection efficiency; at the same time, the total thickness of the P-region tunneling layers 43 is relatively thick, thereby ensuring an excellent passivation effect of the tunneling layer.

[0033] In addition, the P-doped region 40 includes at least one P-region passivation contact unit, which includes a P-region tunneling layer 43 and a P-poly layer 44. Providing multiple P-region passivation contact units helps improve the passivation quality of the P-doped region 40, thereby improving battery efficiency. The N-doped region 50 includes at least one N-region passivation contact unit, which includes an N-region tunneling layer 53 and an N-poly layer 54. Providing multiple N-region passivation contact units helps improve the passivation quality of the N-doped region 50, thereby improving battery efficiency.

[0034] In some embodiments, the P-doped region 40 includes a P-region electrode 45 and a P-region passivation contact unit. The P-region electrode 45 is located on a side of the P-poly layer 44 away from the P-region tunneling layer 43 .

[0035] In some embodiments, the P-doped region 40 includes a P-region electrode 45 and two P-region passivation contact units, the two P-region passivation contact units being a first P-region passivation contact unit 41 and a second P-region passivation contact unit 42, the second P-region passivation contact unit 42 being located on a side of the first P-region passivation contact unit 41 away from the semiconductor substrate 30, and the P-region electrode 45 being in contact with the P-poly layer 44 of the second P-region passivation contact unit 42.

[0036] In some embodiments, the N-doped region 50 includes an N-region electrode 55 and an N-region passivation contact unit. The N-region electrode 55 is located on a side of the N-poly layer 54 away from the N-region tunneling layer 53 .

[0037] In some embodiments, the N-doped region 50 includes an N-region electrode 55 and two N-region passivation contact units, the two N-region passivation contact units being a first N-region passivation contact unit 51 and a second N-region passivation contact unit 52. The second N-region passivation contact unit 52 is located on a side of the first N-region passivation contact unit 51 away from the semiconductor substrate 30, and the N-region electrode 55 is in contact with the N-poly layer 54 of the second N-region passivation contact unit 52.

[0038] The above embodiments can be combined, for example:

[0039] Combine Figure 1 In the first specific embodiment, the P-doped region 40 includes only one P-region tunneling layer 43 and one P-poly layer 44, and the N-doped region 50 includes only one N-region tunneling layer 53 and one N-poly layer 54. The thickness of the P-region tunneling layer 43 is greater than that of the N-region tunneling layer 53. That is, on the basis of ensuring the passivation performance of the tunneling layer, the carrier collection efficiency is improved. At the same time, the TBC battery has a simple structure and high production efficiency.

[0040] Combine Figure 2 In the second embodiment, the P-doped region 40 includes only a P-region tunneling layer 43 and a P-poly layer 44, and the N-doped region 50 includes a first N-region passivation contact unit 51 and a second N-region passivation contact unit 52. That is, along the direction away from the semiconductor substrate 30, the structure of the N-doped region 50 on the back side of the semiconductor substrate 30 is sequentially arranged as follows: an N-region tunneling layer 53, an N-poly layer 54, an N-region tunneling layer 53, an N-poly layer 54, and an N-region electrode 55. The sum of the thicknesses of the N-poly layer 54 in the first N-region passivation contact unit 51 and the N-poly layer 54 in the second N-region passivation contact unit 52 is less than the thickness of the P-region tunneling layer 43. That is, based on the first embodiment, the N-doped region 50 passivation contact unit is provided with two layers. These two layers of passivation contact units can improve the passivation quality of the N-doped region 50, thereby improving the battery efficiency.

[0041] Combine Figure 3 In the third embodiment, the P-doped region 40 includes a first P-region passivation contact unit 41 and a second P-region passivation contact unit 42. Specifically, along the direction away from the semiconductor substrate 30, the P-doped region 40 on the back side of the semiconductor substrate 30 comprises a P-region tunneling layer 43, a P-poly layer 44, a P-region tunneling layer 43, a P-poly layer 44, and a P-region electrode 45, arranged in this order. The N-doped region 50 includes only one N-region tunneling layer 53 and one N-poly layer 54. The sum of the thicknesses of the P-poly layer 44 in the first P-region passivation contact unit 41 and the P-poly layer 44 in the second P-region passivation contact unit 42 is greater than the thickness of the N-region tunneling layer 53. In other words, based on the first embodiment, the passivation contact unit of the P-doped region 40 is provided in two layers, improving the passivation quality of the P-doped region 40 and thereby improving the cell efficiency.

[0042] Combine Figure 4 In the fourth specific embodiment, the P-doped region 40 includes a first P-region passivation contact unit 41 and a second P-region passivation contact unit 42, that is, along the direction away from the semiconductor substrate 30, the structure of the P-doped region 40 on the back side of the semiconductor substrate 30 is a P-region tunneling layer 43, a P-poly layer 44, a P-region tunneling layer 43, a P-poly layer 44 and a P-region electrode 45 arranged in sequence. Similarly, the N-doped region 50 includes a first N-region passivation contact unit 51 and a second N-region passivation contact unit 52. Specifically, along a direction away from the semiconductor substrate 30, the N-doped region 50 on the back side of the semiconductor substrate 30 comprises, in sequence, an N-region tunneling layer 53, an N-poly layer 54, an N-region tunneling layer 53, an N-poly layer 54, and an N-region electrode 55. The sum of the thicknesses of the N-poly layer 54 in the first N-region passivation contact unit 51 and the N-poly layer 54 in the second N-region passivation contact unit 52 is less than the sum of the thicknesses of the P-poly layer 44 in the first P-region passivation contact unit 41 and the P-poly layer 44 in the second P-region passivation contact unit 42. In other words, based on the first specific embodiment, the passivation contact units of both the P-doped region 40 and the N-doped region 50 are configured as two layers, thereby improving the passivation quality of both the P-doped region 40 and the N-doped region 50, thereby improving the cell efficiency.

[0043] In other embodiments, the P-doped region 40 may further include three, four, or five equal P-region passivation contact units, and similarly, the N-doped region 50 may further include three, four, or five equal N-region passivation contact units. The specific number of passivation contact units and the combination of the two are not limited herein. For example, the P-doped region 40 includes four P-region passivation contact units, and the N-doped region 50 arranged alternately with the P-doped region 40 includes two N-region passivation contact units.

[0044] Of course, different P-doped regions 40 may include different numbers of P-region passivation contact units, and different N-doped regions 40 may include different numbers of N-region passivation contact units. For example, a P-doped region 40 may include two P-region passivation contact units, an N-doped region 50 located on one side of the P-doped region 40 may include one N-region passivation contact unit, and an N-doped region 50 located on the other side of the P-doped region 40 may include two N-region passivation contact units.

[0045] In some embodiments, the thickness of the P-region tunneling layer 43 in the second P-region passivation contact unit 42 is smaller than the thickness of the P-region tunneling layer 43 in the first P-region passivation contact unit 41 .

[0046] In this embodiment, the thickness of the P-region tunneling layer 43 in the second P-region passivation contact unit 42 is smaller than the thickness of the P-region tunneling layer 43 in the first P-region passivation contact unit 41 , so as to ensure that holes in the P-doped region 40 have gap migration, thereby reducing the impact on the contact resistance.

[0047] Specifically, the thickness of the P-region tunneling layer 43 in the second P-region passivation contact unit 42 is in the range of 0.5 nm to 0.9 nm.

[0048] In some embodiments, the thickness of the N region tunneling layer 53 in the second N region passivation contact unit 52 is smaller than the thickness of the N region tunneling layer 53 in the first N region passivation contact unit 51 .

[0049] In this embodiment, the N-region tunneling layer 53 in the second N-region passivation contact unit 52 is thin, which is beneficial to carrier migration and further helps to ensure good contact resistance.

[0050] Specifically, the thickness of the N-region tunneling layer 53 in the second N-region passivation contact unit 52 is 0.4 nm to 0.7 nm. Specifically, the thickness of the P-region tunneling layer 43 in the second P-region passivation contact unit 42 may not be limited by the thickness of the N-region tunneling layer 53 in the second N-region passivation contact unit 52, as long as the total thickness of all P-region tunneling layers 43 in the P-doped region 40 is greater than the total thickness of all N-region tunneling layers 53 in the N-doped region 50.

[0051] In some embodiments, the total thickness of all P-region tunneling layers 43 in the P-doped region 40 is 1.1 nm-2.5 nm, and the total thickness of all N-region tunneling layers 53 in the N-doped region 50 is 1 nm-2 nm.

[0052] In some embodiments, the TBC cell structure further includes a passivation layer 20 and an anti-reflection layer 10 disposed on the front and back sides of the cell, respectively, wherein the passivation layer 20 is located on the side of the anti-reflection layer 10 close to the semiconductor substrate 30. Furthermore, the passivation layer 20 on the back side of the cell is located on the side of the P-doped region 40 and the N-doped region 50 away from the semiconductor substrate 30.

[0053] In some embodiments, the P-doped regions 40 and the N-doped regions 50 are alternately and spaced apart on the back side of the cell. Specifically, the back side of the semiconductor substrate 30 has the P-doped regions 40, the grooved regions 60, and the N-doped regions 50 arranged in sequence. The grooved regions 60 separate the P-doped regions 40 from the N-doped regions 50. The passivation layer 20 simultaneously covers the P-doped regions 40, the grooved regions 60, and the N-doped regions 50 on the side away from the semiconductor substrate 30.

[0054] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A TBC battery structure, characterized in that: The TBC battery structure includes a semiconductor substrate and a P-doped region and an N-doped region spaced apart on the back side of the semiconductor substrate; The P-doped region includes at least one P-region passivation contact unit, the P-region passivation contact unit includes a P-region tunneling layer and a P-poly layer, and the P-region tunneling layer in the same P-region passivation contact unit is located on a side of the P-poly layer close to the semiconductor substrate; The N-doped region includes at least one N-region passivation contact unit, the N-region passivation contact unit includes an N-region tunneling layer and an N-poly layer, and the N-region tunneling layer in the same N-region passivation contact unit is located on a side of the N-poly layer close to the semiconductor substrate; The total thickness of all the P-region tunneling layers in the P-doped region is greater than the total thickness of all the N-region tunneling layers in the N-doped region.

2. The TBC battery structure according to claim 1, characterized in that: The P-doped region includes a P-region electrode and a P-region passivation contact unit. The P-region electrode is located on a side of the P-poly layer away from the P-region tunneling layer.

3. The TBC battery structure according to claim 1, characterized in that: The P-doped region includes a P-region electrode and two P-region passivation contact units, the two P-region passivation contact units are respectively a first P-region passivation contact unit and a second P-region passivation contact unit, the second P-region passivation contact unit is located on a side of the first P-region passivation contact unit away from the semiconductor substrate, and the P-region electrode is in contact with the P-poly layer of the second P-region passivation contact unit.

4. The TBC battery structure according to claim 3, characterized in that: The thickness of the P-region tunneling layer in the second P-region passivation contact unit is smaller than the thickness of the P-region tunneling layer in the first P-region passivation contact unit.

5. The TBC battery structure according to claim 4, characterized in that: The thickness of the P-region tunneling layer in the second P-region passivation contact unit is in the range of 0.5 nm to 0.9 nm.

6. The TBC battery structure according to any one of claims 1 to 5, characterized in that: The N-doped region includes an N-region electrode and an N-region passivation contact unit. The N-region electrode is located on a side of the N-poly layer away from the N-region tunneling layer.

7. The TBC battery structure according to any one of claims 1 to 5, characterized in that: The N-doped region includes an N-region electrode and two N-region passivation contact units, the two N-region passivation contact units are respectively a first N-region passivation contact unit and a second N-region passivation contact unit, the second N-region passivation contact unit is located on a side of the first N-region passivation contact unit away from the semiconductor substrate, and the N-region electrode is in contact with the N-poly layer of the second N-region passivation contact unit.

8. The TBC battery structure according to claim 7, characterized in that: The thickness of the N-region tunneling layer in the second N-region passivation contact unit is smaller than the thickness of the N-region tunneling layer in the first N-region passivation contact unit.

9. The TBC battery structure according to claim 8, characterized in that: The thickness of the N-region tunneling layer in the second N-region passivation contact unit is 0.4 nm-0.7 nm.

10. The TBC battery structure according to claim 1, characterized in that: The total thickness of all the P-region tunneling layers in the P-doped region is 1.1 nm-2.5 nm, and the total thickness of all the N-region tunneling layers in the N-doped region is 1 nm-2 nm.

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