Bus structure device

Abstract

The utility model provides a bus structure device. The bus structure device comprises a first bus; a first circuit and a first bus unit circuit; a second circuit and a second bus unit circuit. The first circuit is coupled to the first bus via the first bus unit circuit, and the first bus unit circuit transmits a first output signal from the first circuit as a first bus data signal on the first bus. The second circuit is coupled to the first bus via the second bus unit circuit, and the second bus unit circuit performs OR operation on the first bus data signal and a second bus data signal on the first bus to generate a first input signal to the second circuit.

Description

Technical Field

[0001] The present disclosure relates to a bus structure device, and more particularly to a bus structure device having a plurality of OR gates. Background Art

[0002] Some approaches that rely on tri-state buffer bus configurations face challenges related to electrical leakage and speed limitations. Managing the floating state of the bus requires precise control, and as the number of components and bus capacitance increases, multiple drive mechanisms with high current and timing complexity may be required. Utility Model Content

[0003] A bus structure device is disclosed. The device includes a first bus; a first circuit and a first bus unit circuit, wherein the first circuit is coupled to the first bus via the first bus unit circuit and the first bus unit circuit is configured to transmit a first output signal from the first circuit as a first bus data signal on the first bus; and a second circuit and a second bus unit circuit, wherein the second circuit is coupled to the first bus via the second bus unit circuit and the second bus unit circuit is configured to perform an OR operation between the first bus data signal and the second bus data signal on the first bus to generate a first input signal to the second circuit.

[0004] A bus structure device is disclosed. The device includes: a first die including a first circuit and a second circuit; a plurality of first buses; and a plurality of first bus unit circuits. The first circuit and the second circuit are coupled to the first bus via the first bus unit circuits. Each of the first bus unit circuits is configured to perform an OR operation based on an input signal on a corresponding one of the first buses coupled to the first bus unit circuit to generate a corresponding bus data signal to the first circuit and the second circuit.

[0005] A bus structure device is disclosed. The device includes: a first die, including a first circuit and a second circuit; a plurality of first buses; and a plurality of first bus unit circuits. The first circuit and the second circuit are coupled to the first bus via the first bus unit circuit, and each of the first bus unit circuits is used to perform an OR operation based on an input signal on a corresponding one of the first buses coupled to the first bus unit circuit to generate a corresponding bus data signal to the first circuit and the second circuit; a plurality of second bus unit circuits are coupled to a portion of the first bus; and a first connection circuit is coupled to a portion of the first bus via the second bus unit circuit. The device also includes a second die, including: a third circuit; a plurality of second buses are coupled to the third circuit; a plurality of third bus unit circuits are coupled to the second bus; and a second connection circuit is coupled to the second bus via the third bus unit circuit, wherein the first connection circuit and the second connection circuit are coupled to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0008] Figure 2 According to some embodiments of the present disclosure, Figure 1 Schematic diagram of part of the integrated circuit;

[0009] Figure 3 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0010] Figure 4 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0011] Figure 5 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0012] Figure 6 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0013] Figure 7 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0014] Figure 8 According to some embodiments of the present disclosure, Figure 7 A detailed schematic diagram of the integrated circuit;

[0015] Figure 9 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0016] Figure 10A is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0017] Figure 10B is a schematic diagram of a device according to some embodiments of the present disclosure;

[0018] Figure 11 is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0019] Figure 12 is a flow chart of a method according to some embodiments of the present disclosure;

[0020] Figure 13 FIG. 1 is a schematic diagram illustrating a design process according to some embodiments.

[0021]

Explanation of symbols

[0022] 10, 13, 14, 15, 16, 70, 90: integrated circuits

[0023] 100, 100a~100k: bus unit circuit

[0024] 100M: Bus unit circuit group

[0025] 101: Logic Circuits

[0026] 110, 120, 130, 140, 150, 160, 170, 180, 910a~910o, 930a~930p, 940a~940q, 950a~950r, 960a~960s: Circuit

[0027] 1000:Device

[0028] 1001, 1002, 1100: integrated circuits

[0029] 1010, 1020: Connection circuit

[0030] 1300: Design Process

[0031] 1301: System design phase

[0032] 1302:Logic design phase

[0033] 1303:Synthesis stage

[0034] 1304: Pre-layout simulation stage

[0035] 1305: Resettlement and route selection stage

[0036] 1306: Parameter extraction phase

[0037] 1307: Entity verification and issuance phase

[0038] 1308: Layout file generation phase

[0039] 1309: Manufacturing stage

[0040] AddrBUSL, AddrBUSL0, AddrBUSL1, AddrBUSR: bus data signals

[0041] BUSH, BUSV, BUSH1~BUSH6: bus

[0042] BUSD, BUSU, BUSL, BUSR, BUSIN1, BUSOUT1: bus data signals

[0043] BUSMH1~BUSMH5、BUSMV1~BUSMV3、BUSV1~BUSV3:bus

[0044] D1, D2: grains

[0045] OR1~OR7: OR gate

[0046] P111~P116、P121~P126: Pin

[0047] RdBUSL, RdBUSL0, RdBUSL1, RdBUSR, RdBUSR0, RdBUSR1: bus data signals

[0048] S1201, S1202: Operation

[0049] SI1, SI111, SI121, SI122, SI151: input signal

[0050] SO1, SO111, SO112, SO121: output signal

[0051] WrBUSD, WrBUSD0, WrBUSD1, WrBUSL, WrBUSL0, WrBUSL1, WrBUSR, WrBUSR0, WrBUSR1: bus data signals DETAILED DESCRIPTION

[0052] The following disclosure provides different embodiments or examples for implementing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify one embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. can be expected. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, one embodiment of the present disclosure may repeat element symbols and / or letters in each instance. This repetition is for simplicity and clarity purposes and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0053] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "beneath," "above," and "above," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. The terms "mask," "lithography mask," "reticle," and "mask screen" are used to refer to the same item.

[0054] The terms used in the following description and the scope of the new patent application generally have the ordinary meanings clearly established in the art or in the specific context in which each term is used. Those skilled in the art will understand that a component or process may be referred to by different names. The numerous different embodiments detailed in this specification are for illustration only and do not limit the scope and spirit of the disclosure or any exemplary term.

[0055] It should be noted that the terms "first" and "second" are used herein to describe various elements or processes to distinguish between the elements or processes. However, the elements, processes, and their order are not limited by these terms. For example, a first element may be referred to as a second element, and a second element may be similarly referred to as a first element without departing from the scope of an embodiment of the present disclosure.

[0056] In the following discussion and in the scope of the new patent claims, the terms "comprising," "including," "containing," "having," "involving," etc. should be understood as open-ended, that is, to include but not limited to. As used herein, the term "and / or" is not mutually exclusive and includes any of the relevant listed items and all combinations of one or more of the relevant listed items.

[0057] See now Figure 1 . Figure 1 FIG1 is a schematic diagram of an integrated circuit 10 according to some embodiments of the present disclosure. For illustration, integrated circuit 10 includes circuits 110, 120, and 130, bus unit circuit 100, and buses BUSV and BUSH. Circuits 110-130 are each coupled to bus BUSH via one of bus unit circuits 100. In some embodiments, each of circuits 110-130 may be a device / circuit in a network-on-chip (NoC) system, a logic circuit (e.g., a memory circuit, a controller), or any other suitable circuit.

[0058] In some embodiments, the circuits 110-130 are used to communicate with each other on a bus BUSH via the bus unit circuit 100. The bus BUSH is used to transmit at least two signals in a horizontal bidirectional manner, such as n-bit bus data signals BUSR and BUSL, where n is a positive number. Figure 1 As shown illustratively, the bus data signals BUSR and BUSL are transmitted in opposite directions in the horizontal direction.

[0059] The bus BUSV is coupled to the bus BUSH via the bus unit circuit 100 and is used for vertical bidirectional transmission of at least two signals, such as n-bit bus data signals BUSD and BUSU. The bus data signals BUSD and BUSU are transmitted in opposite directions in the vertical direction.

[0060] In some operational embodiments, the circuits 110 - 130 operate according to a master-slave protocol, for example, the circuit 110 operates as a master circuit, and the circuits 120 - 130 respectively operate as two parallel slave circuits. Specifically, for example, the circuit 110 sends a signal to the bus BUSH via the bus unit circuit 100 to control the circuits 120 - 130, and the bus unit circuit 100 transmits one of the signals from the circuit 110 as a bus data signal BUSL to the circuits 120 - 130.

[0061] By configuring the bus BUSV, the circuit 110 is further configured to control other slave circuits (not shown) coupled to the bus BUSV by transmitting signals via the bus unit circuit 100 coupled to the buses BUSV and BUSH.

[0062] Figure 1 The configuration is for illustration purposes only. Various implementations are within the contemplated scope of an embodiment of the present disclosure.

[0063] See now Figure 2 . Figure 2 According to some embodiments of the present disclosure Figure 1 A schematic diagram of a corresponding portion of the integrated circuit 10 .

[0064] like Figure 2As shown illustratively, bus unit circuit 100 includes OR gates OR1 to OR7. OR gate OR1 has two input terminals coupled to two signal lines of bus BUSH. OR gates OR2, OR4, and OR5 are coupled in series to a first signal line of bus BUSH (e.g., for transmitting bus data signal BUSL). OR gates OR3, OR6, and OR7 are coupled in series to a second signal line of bus BUSH (e.g., for transmitting bus data signal BUSR). Furthermore, OR gates OR4 and OR6 are coupled in series to a first signal line of bus BUSV (e.g., for transmitting bus data signal BUSD). OR gates OR5 and OR7 are coupled in series to a second signal line of bus BUSV (e.g., for transmitting bus data signal BUSU).

[0065] In operation, the bus unit circuit 100 is used to perform an OR operation based on the input signal on the corresponding bus in the bus coupled to the bus unit circuit 100 to generate a corresponding bus data signal. For example, the circuit 110 transmits the output signal SO1 to the bus BUSH via the pin of the circuit 110 and the OR gates OR2 and OR3 in the bus unit circuit 100. In some embodiments where the circuit 110 operates as a master circuit, the bus data signal BUSIN1 transmitted to the bus unit circuit 100 is set to have a low logic value (e.g., connected to the ground voltage). The OR gates OR2, OR4, and OR5 coupled in series are used to perform an OR operation, and accordingly, the bus data signal BUSL is determined by the output signal SO1 and is equal to the output signal SO1. Specifically, the OR gate OR2 performs an OR operation between the bus data signal BUSIN1 and the output signal SO1 to output a signal to the OR gate OR4. The OR gate OR4 performs an OR operation between the signal transmitted by the OR gate OR6 and the signal output by the gate OR2 to generate an output signal to the OR gate OR5 and the signal line of the bus BUSV. OR gate OR5 performs an OR operation between the signal output by OR gate OR4 and the signal transmitted on the second signal line of bus BUSV (e.g., bus data signal BUSU) to generate bus data signal BUSL on the first signal line of bus BUSH to the second signal line of bus BUSV.

[0066] Continue to see Figure 2 OR gate OR7 performs an OR operation between the signal transmitted by OR gate OR5 and bus data signal BUSR to generate an output signal to OR gate OR6 and the second signal line of bus BUSV (e.g., bus data signal BUSU). OR gate OR6 performs an OR operation between the output signal of OR gate OR7 and the signal transmitted by the first signal line of bus BUSV (e.g., bus data signal BUSD) to generate a signal to OR gate OR3. OR gate OR3 performs an OR operation between the signal from OR gate OR6 and output signal SO1 to output bus data signal BUSOUT1.

[0067] based on Figure 2 In the embodiment, OR gates OR4-OR7 are included in a logic circuit 101 of the bus unit circuit 100. The logic circuit 101 is coupled to buses BUSH and BUSV and is used to transmit a signal on bus BUSH / BUSV to bus BUSV / BUSH.

[0068] See now Figure 3 . Figure 3 FIG is a schematic diagram of an integrated circuit 13 according to some embodiments of the present disclosure. Figure 1 and Figure 2 An embodiment of Figure 3 Similar elements in the present invention are designated with the same reference numerals for ease of understanding. The specific operations of similar elements have been discussed in detail in the above paragraphs and are omitted here for the sake of brevity.

[0069] like Figure 3 As shown illustratively, circuit 110 is coupled to buses BUSH1-BUSH3 via bus unit circuits 100a-100c, respectively. Circuit 120 is coupled to buses BUSH1-BUSH3 via bus unit circuits 100d-100f, respectively. In some embodiments, bus unit circuits 100a-100f are, for example, coupled to Figure 1 and Figure 2 The bus unit circuit 100 is configured. For example, the bus BUSH1 to BUSH3 are connected to Figure 1 and Figure 2 Configure the BUSH.

[0070] In some embodiments, each of the bus unit circuits 100 a ˜ 100 f is configured to perform an OR operation based on input signals on a corresponding bus among the buses BUSH1 ˜ BUSH3 coupled thereto to generate corresponding bus data signals to the circuits 110 and 120 .

[0071] See now Figure 4 . Figure 4 is a schematic diagram of an integrated circuit 14 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 14 is relative to, for example, Figure 3 The integrated circuit 13 is configured.

[0072] For example, each of bus lines BUSH1 through BUSH3 includes two signal lines. Bus BUSH1 is used for horizontal bidirectional transmission of at least two signals, such as n-bit bus data signals WrBUSL through WrBUSR. Bus BUSH2 is used for horizontal bidirectional transmission of at least two signals, such as n-bit bus data signals AddrBUSL through AddrBUSR. Bus BUSH3 is used for horizontal bidirectional transmission of at least two signals, such as n-bit bus data signals RdBUSL through RdBUSR.

[0073] In some embodiments, a transaction on a bus typically consists of a start event, a destination slave address in an address bus data signal (e.g., corresponding to AddrBUSL-AddrBUSR), and read / write data in a read / write bus data signal (e.g., RdBUSL-RdBUSR / WrBUSL-WrBUSR), for a circuit on the bus to access other circuits coupled to the bus. In some embodiments, a transaction is typically terminated by a stop event or another start event.

[0074] Circuit 110 is coupled to bus unit circuit 100a via pins P111 and P112, and is further coupled to bus BUSH1, wherein the output of OR gate OR1 of bus unit circuit 100a is coupled to pin 111, and the inputs of OR gates OR2 and OR3 of bus unit circuit 100a are coupled to pin 112. Circuit 110 is coupled to bus unit circuit 100b via pins P113 and P114, and is further coupled to bus BUSH2, wherein the output of OR gate OR1 of bus unit circuit 100b is coupled to pin 113, and the inputs of OR gates OR2 and OR3 of bus unit circuit 100b are coupled to pin 114. Circuit 110 is coupled to bus unit circuit 100c via pins P115 and P116 and further coupled to bus BUSH3, wherein the output of OR gate OR1 of bus unit circuit 100c is coupled to pin 115 and the inputs of OR gates OR2 and OR3 of bus unit circuit 100c are coupled to pin 116.

[0075] Similarly, circuit 120 is coupled to bus unit circuit 100d via pins P121 and P122, and further coupled to bus BUSH1, wherein the output of OR gate OR1 of bus unit circuit 100d is coupled to pin 121, and the inputs of OR gates OR2 and OR3 of bus unit circuit 100d are coupled to pin 122. Circuit 120 is coupled to bus unit circuit 100e via pins P123 and P124, and further coupled to bus BUSH2, wherein the output of OR gate OR1 of bus unit circuit 100e is coupled to pin 123, and the inputs of OR gates OR2 and OR3 of bus unit circuit 100e are coupled to pin 124. Circuit 120 is coupled to bus unit circuit 100f via pins P125 and P126 and further coupled to bus BUSH3, wherein the output of OR gate OR1 of bus unit circuit 100f is coupled to pin 125 and the inputs of OR gates OR2 and OR3 of bus unit circuit 100f are coupled to pin 126.

[0076] exist Figure 4In the embodiment of the present invention, according to the first master-slave protocol, the circuits 110 and 120 operate as a master circuit and a slave circuit, respectively. In some embodiments, the circuit 110 sends a signal to the circuit 120 via the buses BUSH1 and BUSH2 to control the circuit 120, and receives a feedback signal from the circuit 120 via the bus BUSH3. Therefore, in order to make the signal on the first signal line of the buses BUSH1 and BUSH2 (corresponding to the signal line for sending the signal to the right) determined by the signal from the circuit 110 and equal to the signal, the bus data signals WrBUSL0 and AddrBUSL0 transmitted to the bus unit circuits 100a and 100b are relative to, for example, Figure 2 Similarly, in order for the signal on the second signal line of the bus BUSH3 (corresponding to the signal line for transmitting the signal to the left) to be determined by the signal output by the circuit 120 and to be equal to the signal, the bus data signal RdBUSR transmitted to the bus unit circuit 100f is set to a low logic value (for example, connected to the ground voltage).

[0077] In operation, circuit 110 operates as a master circuit, first transmitting output signals SO111 and SO112 to OR gates OR2 and OR3 in bus unit circuits 100a and 100b, while the output terminal of OR gate OR1 in bus unit circuits 100a and 100b is connected to "0", and circuit 110 does not receive signals from buses BUSH1 and BUSH2. OR gates OR2 and OR3 are called "operation OR gates" and are represented by solid lines. In addition, OR gates OR4 to OR7 in bus unit circuits 100a and 100b are called "transmission OR gates" and are represented by dotted lines. Specifically, since there is no vertical bus communication, the first input terminals of OR gates OR4 to OR7 coupled to the vertical bus in bus unit circuits 100a and 100b are connected to ground. Therefore, the output signals of OR gates OR4 to OR7 follow the signals received from the second input terminals of OR gates OR4 to OR7. For example, the OR gates OR4 and OR5 transmit and output the signal from the OR gate OR2 , and the OR gates OR6 and OR7 transmit and output the signal received by the OR gate OR7 .

[0078] Continuing with the above embodiment, the bus unit circuits 100a and 110b further transmit the output signals SO111 and SO112 from the circuit 110 as bus data signals WrBUSL1 and AddrBUSL1 on the buses BUSH1 and BUSH2 to the bus unit circuits 100d and 100e, respectively, and further transmit them to the circuit 120.

[0079] Specifically, for example, the OR gate OR2 of the bus unit circuit 100a performs an OR operation between the output signal SO111 and the bus data signal WrBUSL0 having a low logic value to output the bus data signal WrBUSL1 via the OR gates OR4 and OR5 of the bus unit circuit 100a. The bus data signal WrBUSL1 follows and is equal to the output signal SO111. Then, the OR gate OR1 of the bus unit circuit 100d performs an OR operation between the bus data signal WrBUSL1 and the bus data signal WrBUSR1 on the bus BUSH1 to generate the input signal SI121 to the circuit 120 at pin P121, and generates the bus data signal WrBUSR1 having a low logic value. In some embodiments, the OR gates OR2-OR7 of the bus unit circuit 100d operate as transfer OR gates, and the output signals of the OR gates OR2-OR7 follow the signals received from the input terminals of the OR gates OR2-OR7, while the other input terminals of the OR gates OR2-OR7 are connected to ground. For example, pin P122 is connected to ground and is not vertically transferred through OR gates OR4 to OR7. Therefore, the bus data signal WrBUSL1 is equal to WrBUSL, and the data signal WrBUSLR1 is equal to WrBUSLR.

[0080] Similarly, OR gate OR2 of bus unit circuit 100b performs an OR operation between output signal SO112 and bus data signal AddrBUSL0 having a low logic value to output bus data signal AddrBUSL1 via OR gates OR4 and OR5 of bus unit circuit 100b. Bus data signal AddrBUSL1 follows and is equal to output signal SO112. Then, OR gate OR1 of bus unit circuit 100e performs an OR operation between bus data signal AddrBUSL1 and bus data signal AddrBUSR1 on bus BUSH2 to generate input signal SI122 to circuit 120 at pin P123, and generates bus data signal AddrBUSR1 having a low logic value. In some embodiments, OR gates OR2-OR7 of bus unit circuit 100e operate as transfer OR gates, while pin P124 is connected to ground and is not vertically transferred via OR gates OR4-OR7 of bus unit circuit 100e. Therefore, the bus data signal AddrBUSL1 is equal to AddrBUSL, and the bus data signal AddrBUSLR1 is equal to AddrBUSLR.

[0081] Circuit 120 operates as a slave circuit to transmit the output signal (e.g., SO121) to the OR gates OR2 and OR3 in the bus unit circuit 100f, and circuit 120 selectively receives a signal from the OR gate OR1 in the bus unit circuit 100f coupled to pin P125 according to the operation configuration of circuit 120. In some embodiments, circuit 120 does not receive a signal from bus BUSH3, in some configurations, for example, by connecting pin P125 to "0". The OR gates OR2 and OR3 in the bus unit circuit 100f are referred to as "operation OR gates". In addition, the OR gates OR4 to OR7 in the bus unit circuit 100f are referred to as transmission OR gates. Specifically, since there is no vertical bus communication, the first input terminals of the OR gates OR4 to OR7 coupled to the vertical bus in the bus unit circuit 100f are connected to ground. The configuration of the OR gates OR4 to OR7 in the bus unit circuit 100f is similar to that of the OR gates OR4 to OR7 in the bus unit circuits 100a and 100b. Therefore, repeated description is omitted herein.

[0082] Continuing with the above embodiment, the bus unit circuit 100 f further transmits the output signal SO121 from the circuit 120 as the bus data signal RdBUSR1 on the bus BUSH3 to the bus unit circuit 100 c , and further transmits it to the circuit 110 .

[0083] Specifically, for example, OR gate OR3 of bus unit circuit 100f performs an OR operation between output signal SO121 and bus data signal RdBUSR having a low logic value to output bus data signal RdBUSR1 transmitted to the left. Bus data signal RdBUSR1 follows and is equal to output signal SO121. Then, OR gate OR1 of bus unit circuit 100c performs an OR operation between bus data signal RdBUSR1 and bus data signal RdBUSL0 on bus BUSH3 to generate input signal SI111 to circuit 110 at pin P115, where bus data signal RdBUSL0 has a low logic value. In some embodiments, OR gates OR2-OR7 of bus unit circuit 100c operate as transmission OR gates, with the output signals of OR gates OR2-OR7 following the signals received from the input terminals of OR gates OR2-OR7, while the other input terminals of OR gates OR2-OR7 are connected to ground. For example, pin P116 is connected to ground and is not vertically transmitted through OR gates OR4-OR7. Therefore, bus data signal RdBUSL0 is equal to RdBUSL1. In some embodiments, circuit 110 selectively receives signals from OR gates OR1 in bus unit circuits 100a, 100b coupled to pins P111 and P113, respectively, depending on the operational configuration of circuit 110. In some embodiments, circuit 110 does not receive signals from bus lines BUSH2 and BUSH1, for example, by connecting pins P111 and P113 to "0" in some configurations.

[0084] See now Figure 5 . Figure 5 is a schematic diagram of an integrated circuit 15 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 15 is relative to, for example, Figure 3 and Figure 4 The integrated circuit 14 is configured.

[0085] and Figure 4 Compared with the integrated circuit 14, the circuit 110 operates as a slave circuit and the circuit 120 operates as a master circuit. Figure 5 The configuration of the master circuit and the slave circuit in Figure 4 Therefore, repeated description is omitted in this article.

[0086] See now Figure 6 . Figure 6 FIG. 1 is a schematic diagram of an integrated circuit 16 according to some embodiments of the present disclosure. The integrated circuit 16 is shown relative to, for example, Figures 3 to 5 The integrated circuits 13 to 15 are configured.

[0087] For illustration, the integrated circuit 16 further includes circuits 140, 150 and bus unit circuits 100g-100l. In some embodiments, the bus unit circuits 100g-100l are relative to, for example, Figures 1 to 5 The bus unit circuits 100, 100a to 100f are configured. Figures 1 to 5 For ease of understanding, Figure 6 For simplicity, only the operating OR gates are shown in bold, and the transfer OR gates are omitted.

[0088] The circuit 140 is coupled to the buses BUSH1 to BUSH3 via the bus unit circuits 100g to 100i. The circuit 150 is coupled to the buses BUSH1 to BUSH3 via the bus unit circuits 100j to 100l. Figure 6 shown.

[0089] In some embodiments, under the master-slave protocol, circuits 110 and 140 operate as master circuits (eg, labeled master0 and master1 ), while circuits 120 and 150 operate as slave circuits (eg, labeled slave0 and slave1 ).

[0090] In some embodiments, when circuit 110 operates as a master circuit to control circuits 120 and 150, bus unit circuit 100g outputs a bus data signal WrBUSL0 having a low logic value of 0 on bus BUSH1 to bus unit circuit 100a. Bus unit circuit 100h is configured similarly to bus unit circuit 100g. Bus unit circuits 100j to 100l are configured similarly to bus unit circuits 100d to 100f. For example, bus unit circuit 100j performs an OR operation between bus data signal WrBUSL1 and bus data signal WrBUSR1 on bus BUSH1 to generate input signal SI151 to circuit 150. Therefore, see Figure 4 and Figure 6 , the output signal SO111 is transmitted to the circuit 150 as the input signal SI151.

[0091] Figure 6 The configuration is for illustration purposes only. Various implementations are within the contemplated scope of an embodiment of the present disclosure. For example, in some embodiments, the master-slave protocol of circuits 110, 120, 140, and 150 is configured according to actual application.

[0092] See now Figure 6 and Figure 7 ,in Figure 7 is a schematic diagram of an integrated circuit 70 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 70 is relative to, for example, Figures 1 to 6The integrated circuits 10, 13 to 16 are configured.

[0093] like Figure 7 As shown, circuits 140 and 150 are coupled to the bus unit circuits 100g to 1001. Figure 7 Buses BUSH4 to BUSH6 in the . Figure 4 Bus BUS4 is used to transmit bus data signals related to write signals (e.g., WrBUSL, WrBUSR) relative to bus BUSH1. Bus BUS5 is used to transmit bus data signals related to address signals (e.g., AddrBUSL, AddrBUSR) relative to bus BUSH2. Bus BUS6 is used to transmit bus data signals related to read signals (e.g., RdBUSL, RdBUSR) relative to bus BUSH3.

[0094] Compared to the horizontal bus communication with integrated circuit 16, integrated circuit 70 communicates via the Figure 1 The horizontal bus BUSH1 to BUSH6 of the BUSH configuration and the relative Figure 1 The vertical buses BUSV1 - BUSV3 of the bus BUSV configuration perform horizontal and vertical bus communications between the circuits 110 , 120 and 140 , 150 .

[0095] For example, the bus unit circuits 100a-100c and 100g-100i are coupled to the bus lines BUSH and BUSV. Figure 1 In some embodiments, bus unit circuits 100a and 100g are coupled to each other via bus BUSV1, so that bus data signals on bus BUSH1 are transmitted to / from bus BUSH4. Similarly, bus unit circuits 100b and 100h are coupled to each other via bus BUSV2, so that bus data signals on bus BUSH2 are transmitted to / from bus BUSH5. Bus unit circuits 100c and 100i are coupled to each other via bus BUSV3, so that bus data signals on bus BUSH3 are transmitted to / from bus BUSH6.

[0096] See now Figure 8 . Figure 8 In the embodiment of this disclosure, Figure 7 Detailed schematic diagram of integrated circuit 70.

[0097] In some embodiments of the master-slave protocol, circuits 110 and 140 operate as master circuits, and circuits 120 and 150 operate as slave circuits. When circuit 110 is used to control circuits 120 and 150, OR gates OR4, OR5, and OR6 in bus unit circuits 100a and 100b are referred to as operational OR gates, which transmit the corresponding signal from OR gate OR2 to the right via buses BUSH1 and BUSH2 to bus unit circuits 100d and 100e, and then transmit it downward via buses BUSV1 and BUSV2 to bus unit circuits 100g and 100h. OR gates OR4 and OR5 in bus unit circuits 100g and 100h further transmit the signal to the right via buses BUSH4 and BUSH5 to bus unit circuits 100j and 100k.

[0098] The circuit 120 feeds back a signal to the circuit 110 via the bus unit circuit 100f, the bus BUSH3 and the bus unit circuit 100c, such as Figure 8 The circuit 150 feeds back a signal to the circuit 110 in the left and upward directions via the bus unit circuit 1001, the bus unit circuit 100i, the bus BUSH6, the bus BUSV3 and the bus unit circuit 100c.

[0099] See now Figure 9 . Figure 9 is a schematic diagram of an integrated circuit 90 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 90 is relative to, for example, Figures 1 to 8 The integrated circuits 10, 13 to 16 and 70 are configured.

[0100] Integrated circuit 90 includes bus unit circuit group 100M, buses BUSMV1~BUSMV3, BUSMH1~BUSMH5, and circuits 910a~910o, 920, 930a~930p, 940a~940q, 950a~950r, 960a~960s, where "o", "p", "q", "r", and "s" are positive integers.

[0101] In some embodiments, each of the buses BUSMH1-BUSMH5 includes Figure 1 Multiple buses BUSH in, and each of the buses BUSMV1~BUSMV3 includes Figure 1The bus unit circuit group 100M includes multiple bus unit circuits 100. Each of the circuits 910a-910o, 920, 930a-930p, 940a-940q, 950a-950r, and 960a-960s is coupled to a corresponding one of the buses BUSMH1-BUSMH5 via a bus unit circuit group 100M. In some embodiments, a master-slave protocol is employed, and the circuits 910a-910o, 920, 930a-930p, 940a-940q, 950a-950r, and 960a-960s are configured to perform bus communication via the buses BUSMV1-BUSMV3 and BUSMH1-BUSMH5.

[0102] Furthermore, bus unit circuit group 100M is further configured to transmit signals on buses BUSMH1-BUSMH5 to buses BUSMV1-BUSMV3 for vertical bus communication. For example, bus BUSMV1 is coupled to buses BUSMH1 and BUSMH2 via two bus unit circuit groups 100M. Bus BUSMV2 is coupled to buses BUSMH2 and BUSMH3 via two other bus unit circuit groups 100M. Bus BUSMV3 is coupled to buses BUSMH2-BUSMH5 via three bus unit circuit groups 100M.

[0103] Figure 9 The configuration is for illustration purposes only. Various implementations are within the contemplation of an embodiment of the present disclosure. For example, in some embodiments, the number of circuits, bus unit circuit groups 100M, and buses BUS is not limited.

[0104] See now Figure 10A . Figure 10A FIG. 1 is a schematic diagram of an integrated circuit 1001 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 1001 is configured to be operable with respect to, for example, Figure 7 The integrated circuit 70 is configured.

[0105] and Figure 7 In contrast, integrated circuit 1001 does not include circuit 150 but further includes connection circuit 1010 coupled to buses BUSH4-BUSH6 via bus unit circuits 100j-1001. In some embodiments, connection circuit 1010 includes structures for transmitting received signals to other devices, such as metal lines and vias.

[0106] See now Figure 10B . Figure 10B is a schematic diagram of a device 1000 according to some embodiments of the present disclosure.

[0107] For illustration, the apparatus 1000 includes an integrated circuit 1001 and an integrated circuit 1002 with respect to, for example, Figure 10A The integrated circuit 1002 is configured as the integrated circuit 1001. For example, the integrated circuit 1002 includes the circuits 160-180 and the connecting circuit 1020. The circuits 160-180 are relative to, for example, Figure 10A The circuits 110, 120 and 140 are configured. The connection circuit 1020 is relative to, for example Figure 10A For example, the connection circuit 1020 is coupled to the buses BUSH4 - BUSH6 via the bus unit circuits 100j - 1001 in the integrated circuit 1001 .

[0108] In some embodiments, two integrated circuits on two different dies are used to operate as a master circuit and a slave circuit respectively, and are further implemented to control each other. For example, in some embodiments, integrated circuit 1001 is formed in die D1, and integrated circuit 1002 is formed in die D2, which is different from die D1. Connection circuits 1010 and 1020 are coupled to each other and used to transmit signals between dies D1 and D2. In some embodiments, one of integrated circuits 1001 and 1002 is used to operate as a master circuit, and the other is used to operate as a slave circuit. Therefore, via Figure 10B In the configuration provided in FIG, integrated circuit 1001 on die D1 controls integrated circuit 1002 on die D2. In various embodiments, integrated circuits 1001 and 1002 operate as a slave circuit and a master circuit, respectively. Thus, integrated circuit 1002 on die D2 controls integrated circuit 1001 on die D1.

[0109] See now Figure 11 . Figure 11 FIG. 1 is a schematic diagram of an integrated circuit 1100 according to some embodiments of the present disclosure. In some embodiments, the integrated circuit 1100 is configured to be connected to, for example, Figure 7 and Figure 8 The integrated circuit 70 is configured.

[0110] and Figure 8 In contrast, integrated circuit 1100 includes multiple registers (e.g., pipelines) P coupled to vertical buses BUSV1-BUSV3. For illustration, register P is coupled between OR gate OR4 in bus unit circuits 100a-100c and OR gate OR6 in bus unit circuits 100g-100i, and another register P is coupled between OR gate OR5 in bus unit circuits 100a-100c and OR gate OR7 in bus unit circuits 100g-100i.

[0111] In some embodiments, the register P is used to store data of a received signal and further output the stored data as a bus data signal to the next component coupled thereto. Figure 11 The configuration can improve the delay of bus data signals transmitted over long distances.

[0112] Figure 11 The configuration is for illustration purposes only. Various implementations are contemplated within the scope of an embodiment of the present disclosure. For example, in some embodiments, register P is coupled to a horizontal bus.

[0113] See now Figure 12 . Figure 12 FIG1 is a flow chart of a method 1200 according to some embodiments of the present disclosure. It should be understood that for other embodiments of the method 1200, Figure 12 Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Method 1200 includes operations S1201, S1202, and the corresponding operations are described below. Figures 1 to 11 These operations are described with reference to the integrated circuits 10, 13-16, 70, 1001, and 1100.

[0114] In operation S1201, Figure 4 As shown, the bus unit circuit 100a performs an OR operation between the output signal SO111 of the circuit 110 and the bus data signal WrBUSL0 to generate the bus data signal WrBUSL1 on the bus BUSH1.

[0115] In S1202, the bus unit circuit 100d performs an OR operation between the bus data signal WrBUSL1 and the bus data signal WrBUSR1 on the bus BUSH1 to generate an input signal S121 to the circuit 120, as shown in FIG. Figure 4 In some embodiments, the bus data signal WrBUSL1 and the bus data signal WrBUSR1 are transmitted in opposite directions (horizontally to the left and right).

[0116] In some embodiments, as Figure 8 As shown, method 1200 further includes the following steps: bus unit circuit 100a performs an OR operation between bus data signal WrBUSL1 and bus data signal WrBUSD1 on bus BUSV1 to generate bus data signal WrBUSD2 on bus BUSV1, which is transmitted to bus unit circuit 100g coupled to bus BUSH4. In some embodiments, bus BUSH1 and bus BUSH4 extend in a horizontal direction, and bus BUSV1 extends in a vertical direction.

[0117] In some embodiments, as Figure 11As shown, the method 1200 further includes the following steps: storing data corresponding to the bus data signal WrBUSD2 output by the OR gate OR4 of the bus unit circuit 100a through the register P coupled to the bus BUSV1; and transmitting the bus data signal to the operation of the OR gate OR6 in the bus unit circuit 100g coupled to the bus BUSH4 through the register P according to the data.

[0118] See now Figure 13 . Figure 13 1300 is a schematic diagram illustrating a design process according to some embodiments. Figures 1 to 11 The design flow 1300 for the integrated circuits 10, 13-16, 70, 1001, 1002, and 1100 depicted in FIG. 1 utilizes one or more electronic design automation (EDA) tools to perform design operations. These tools are executed using a workstation or personal computer to perform the design flow 1300. The design flow 1300 includes a system design phase 1301, a logic design phase 1302, a synthesis phase 1303, a pre-layout simulation phase 1304, a placement and routing phase 1305, a parameter extraction phase 1306, a physical verification and signoff phase 1307, a layout file generation phase 1308, and a manufacturing phase 1309.

[0119] Initially, in the system design phase 1301, a high-level description of the system architecture of the chip of interest is generated. During this phase, each chip function and performance requirement is determined based on the design specifications. These functions are typically represented by corresponding schematic functional modules or blocks. Furthermore, optimizations or performance trade-offs may be sought to achieve the design specifications at an acceptable cost and power.

[0120] In the logic design phase 1302, functional modules or blocks are described in register transfer level (RTL) using a hardware description language. Language tools are typically available from commercial software (such as Verilog or VHDL). For example, Figure 1 The bus unit circuit 100 corresponds to a module described using a language tool, which provides a regular pattern that facilitates register transfer hierarchy encoding and reduces the complexity of integrated circuit design. A preliminary functional check is performed in the logic design stage 1302 to verify whether the implemented functions meet the specifications specified in the system design stage 1301.

[0121] Subsequently, in the synthesis phase 1303, the modules in the RTL description are converted into netlist data, which establishes the circuit structure within each functional module, such as logic gates and registers. These logic gates and registers can be mapped to available cells in the standard cell library. Furthermore, netlist data is provided to describe the functional relationships of the chip devices at the gate level. The netlist data is converted from the gate level to a transistor level view. As used herein, the term "netlist" refers to both graphical representations, such as schematics, and text-based circuit representations.

[0122] Next, the gate-level netlist data is verified during the pre-layout simulation phase 1304. If certain functions fail to verify during the verification process in phase 1304, the design process 1300 can be temporarily paused and returned to phases 1301 or 1302 for further corrections or modifications. After the pre-layout simulation phase 1304, the IC chip design has been initially verified and the front-end design process is complete. Subsequently, the back-end physical design process will proceed.

[0123] During the placement and routing phase 1305, the physical architecture representing the circuitry determined during the front-end process is implemented. The detailed structure and associated geometry of each component and device are determined during the placement operation, and the interconnections between the various components are routed after the placement operation. Furthermore, the placement operation involves deciding where to place each IC chip component and circuit within the limited space, while the routing operation determines the actual routing of the connecting wires. The placement and routing operations are performed to satisfy a design rule check (DRC) station (such as from a wafer fabrication facility) to meet the wafer's manufacturing standards. Following the placement and routing phase 1305, placement and routing layout data is created, and a netlist containing the placement and routing data is generated based on this data.

[0124] In the parameter extraction stage 1306 , a layout parameter extraction (LPE) operation is performed to obtain layout-related parameters such as parasitic resistance and capacitance generated by the developed layout in stage 1305 .

[0125] During the physical verification and signoff phase 1307, a layout-versus-schematic (LVS) check is performed on the physical netlist generated from the design layout to ensure that the design layout corresponds to the semiconductor circuit. Furthermore, a design rule check (DRC) is performed on the design layout to ensure the design is clean, such as for electrical and lithographic issues that may occur during manufacturing. Incremental repairs can be performed to achieve final signoff of the IC chip design before tapeout.

[0126] In some embodiments, if the results of the physical verification and signoff phase 1307 are unfavorable, the design flow 1300 may return to a previous phase to perform functional or performance tuning. For example, the design flow 1300 may return to the placement and routing phase 1305, where the layout is redeveloped to fix issues at the layout level. Alternatively, the design flow 1300 may return to an earlier phase, the system design phase 1301 or the logic design phase 1302, to redesign the chip if issues could not be resolved in the back-end phase.

[0127] After the circuit design is verified and signed off, a layout file corresponding to the circuit design is generated in a layout file generation phase 1308. The layout file is described / expressed in a binary file format (e.g., a Graphic Database System II (GDSII) stream format), where the binary file format represents planar geometric shapes, text labels, and other information. In some embodiments, the GDSII file is a graphical representation of the integrated circuit wafer, which can subsequently be used to create a mask used in the IC manufacturing process. In some embodiments, the integrated circuit design layout can be represented in any suitable format.

[0128] In the fabrication phase 1309, a fabrication tool receives a layout design file (eg, a GDSII file) corresponding to the IC wafer for fabrication. In the fabrication phase 1309, a semiconductor device corresponding to the GDSII file is produced.

[0129] Figure 13 The design flow 1300 illustrated in FIG. 1 is illustrative. Other orders of stages or operations, divisions of stages, or additional stages before, between, or after the illustrated stages are still within the contemplated scope of an embodiment of the present disclosure.

[0130] In some approaches, a three-state bus structure is implemented. However, this presents significant challenges in managing current leakage and maximum operating speed. Furthermore, as the number of components and capacitance on the bus increases, bus float requires specialized control, potentially multiple drivers (with high current flow), and timing closure issues. In other applications, multiplexing-based buses have a non-fixed network complexity that degrades linearly with the number of masters and slaves on the bus.

[0131] The present disclosure employs an OR-gate-based bus structure configuration. This provides regularity through the regular pattern of bus unit circuits for each master and slave circuit, avoiding circuitous loops and facilitating channel resource estimation during chip design. Furthermore, the bus network complexity is reduced, regardless of the number of master / slave devices on the bus. This configuration further ensures that any block can be easily coupled to the bus and attached to the bus to form a new bus element, wherein signals propagate from one component (circuit) to another via the bus network.

[0132] A device is also disclosed. The device includes a first bus; a first circuit and a first bus unit circuit, wherein the first circuit is coupled to the first bus via the first bus unit circuit and the first bus unit circuit is configured to transmit a first output signal from the first circuit as a first bus data signal on the first bus; and a second circuit and a second bus unit circuit, wherein the second circuit is coupled to the first bus via the second bus unit circuit and the second bus unit circuit is configured to perform an OR operation between the first bus data signal and a second bus data signal on the first bus to generate a first input signal to the second circuit.

[0133] In some embodiments, the first bus unit circuit includes a first OR gate configured to perform an OR operation between the first output signal and a third bus data signal having a low logic value to output the first bus data signal.

[0134] In some embodiments, the first bus unit circuit further includes: a second OR gate having a plurality of input terminals coupled to the first bus and an output terminal coupled to a pin of the first circuit.

[0135] In some embodiments, the second bus unit circuit includes: a third OR gate, wherein a plurality of input terminals of the third OR gate are coupled to the first bus, and an output terminal of the third OR gate is used to output the first input signal to the second circuit.

[0136] In some embodiments, the second bus unit circuit further includes: a fourth OR gate and a fifth OR gate having a plurality of input terminals coupled together at a pin of the second circuit, the input terminals being connected to a ground voltage.

[0137] In some embodiments, the first circuit is configured to operate as a first master component, and the second circuit is configured to operate as a first slave component.

[0138] In some embodiments, the device further includes: a third circuit and a third bus unit circuit coupled to the first bus, wherein the third circuit is used to operate as a second master component, and the third bus unit circuit is used to output a third bus data signal having a low logic value on the first bus to the first bus unit circuit.

[0139] In some embodiments, the device further includes: a fourth circuit and a fourth bus unit circuit coupled to the first bus, wherein the fourth circuit is configured to operate as a second slave component, and the fourth bus unit circuit is configured to perform an OR operation between a first bus data signal and a second bus data signal on the first bus to generate a second input signal to the fourth circuit.

[0140] In some embodiments, the device further includes: a fourth circuit and a fourth bus unit circuit coupled to the first bus, wherein the second bus unit circuit includes a plurality of OR gates, the OR gates are coupled in series to the first bus and are used to transmit the first bus data signal to the fourth circuit, and wherein the fourth circuit is used to operate as a second slave component to receive a second input signal that is the same as the first bus data signal.

[0141] In some embodiments, the device further includes: a second bus; and a third bus unit circuit and a fourth bus unit circuit; wherein the second circuit is further coupled to the second bus via the third bus unit circuit, and the third bus unit circuit is used to transmit a second output signal from the second circuit as a third bus data signal on the second bus, and wherein the first circuit is coupled to the second bus via the fourth bus unit circuit, and the fourth bus unit circuit is used to perform an OR operation between the third bus data signal and the fourth bus data signal on the second bus to generate a second input signal to the first circuit.

[0142] In some embodiments, the device further includes: a third bus; and a fifth bus unit circuit coupled between the third bus and the first circuit and a sixth bus unit circuit coupled between the third bus and the second circuit, wherein the fifth bus unit circuit is used to transmit a third output signal from the first circuit as a fifth bus data signal on the third bus, and wherein the sixth bus unit circuit is used to perform an OR operation between the fifth bus data signal and a sixth bus data signal on the third bus to generate a third input signal to the second circuit.

[0143] In some embodiments, the device further includes a fourth bus, wherein the first bus unit circuit includes a logic circuit coupled to the first bus and the fourth bus and configured to transmit the first bus data signal from the first bus to the fourth bus.

[0144] In some embodiments, the logic circuit includes: a first OR gate and a second OR gate coupled in series to a first signal line of a first bus; and a third OR gate and a fourth OR gate coupled in series to a second signal line of the first bus, wherein the first OR gate and the third OR gate are coupled in series to a first signal line of a fourth bus, and the second OR gate and the fourth OR gate are coupled in series to a second signal line of a fourth bus.

[0145] A device is also disclosed. The device includes: a first die including a first circuit and a second circuit; a plurality of first buses; and a plurality of first bus unit circuits. The first circuit and the second circuit are coupled to the plurality of first buses via the plurality of first bus unit circuits. Each of the plurality of first bus unit circuits is configured to perform an OR operation based on an input signal on a corresponding one of the plurality of first buses coupled to the first bus unit circuit to generate a corresponding bus data signal to the first circuit and the second circuit.

[0146] In some embodiments, a first portion of the first bus is used to transmit a first portion of the bus data signal in a horizontal direction, and a second portion of the first bus is used to transmit a second portion of the bus data signal in a vertical direction.

[0147] In some embodiments, the first die further includes: a plurality of second bus unit circuits coupled to a portion of the first bus; and a first connection circuit coupled to a portion of the first bus via the second bus unit circuit, wherein the device further includes: a second die including: a third circuit; a plurality of second buses coupled to the third circuit; a plurality of third bus unit circuits coupled to the second bus; and a second connection circuit coupled to the second bus via the third bus unit circuit, wherein the first connection circuit and the second connection circuit are coupled to each other.

[0148] In some embodiments, the second circuit is used to operate as a master circuit, and the third circuit is used to operate as a slave circuit, wherein each of the third bus unit circuits is used to perform an OR operation based on a corresponding bus data signal received from the first circuit via the second connection circuit and multiple signals on the second bus, and generate an output bus data signal to the third circuit.

[0149] A method is also disclosed, comprising the steps of: performing a first OR operation on a first bus unit circuit between a first output signal of a master circuit and a first bus data signal to generate a second bus data signal on the first bus; and performing a second OR operation on a second bus unit circuit between the second bus data signal and a third bus data signal on the first bus to generate a first input signal to the slave circuit. The second bus data signal and the third bus data signal are transmitted in opposite directions.

[0150] In some embodiments, the method further includes the following steps: performing a second OR operation between the second bus data signal and a fourth bus data signal on a second bus by the first bus unit circuit to generate a fifth bus data signal on the second bus to a third bus unit circuit coupled to a third bus, wherein the first bus and the third bus extend along a first direction, and the second bus extends along a second direction different from the first direction.

[0151] In some embodiments, the method further includes the following steps: performing a second OR operation between the second bus data signal and a fourth bus data signal on a second bus by a first bus unit circuit to generate a fifth bus data signal on the second bus; storing data corresponding to the fifth bus data signal by a register coupled to the second bus; and sending a sixth bus data signal to a third unit circuit coupled to a third bus according to the data by the register.

[0152] A device is also disclosed. The device includes: a first die including a first circuit and a second circuit; a plurality of first buses; and a plurality of first bus unit circuits. The first circuit and the second circuit are coupled to the plurality of first buses via the plurality of first bus unit circuits, and each of the plurality of first bus unit circuits is used to perform an OR operation based on an input signal on a corresponding one of the plurality of first buses coupled to the first bus unit circuit to generate a corresponding bus data signal to the first circuit and the second circuit; a plurality of second bus unit circuits coupled to a portion of the first buses; and a first connection circuit coupled to a portion of the first buses via the second bus unit circuit. The device also includes a second die including: a third circuit; a plurality of second buses coupled to the third circuit; a plurality of third bus unit circuits coupled to the second bus; and a second connection circuit coupled to the second bus via the third bus unit circuit, wherein the first connection circuit and the second connection circuit are coupled to each other.

[0153] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of an embodiment of the present disclosure. Those skilled in the art will understand that one embodiment of the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that the multiple equivalent constructions described do not depart from the spirit and scope of an embodiment of the present disclosure, and that various changes, substitutions, and modifications may be made to the multiple equivalent constructions without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A bus structure device, characterized in that: Include: a first bus; a first circuit and a first bus unit circuit, wherein the first circuit is coupled to the first bus via the first bus unit circuit, and the first bus unit circuit is configured to transmit a first output signal from the first circuit as a first bus data signal on the first bus; and a second circuit and a second bus unit circuit, wherein the second circuit is coupled to the first bus via the second bus unit circuit, and the second bus unit circuit is used to perform an OR operation on the first bus data signal and a second bus data signal on the first bus to generate a first input signal to the second circuit.

2. The bus structure device according to claim 1, wherein: The first bus unit circuit includes: A first OR gate is used to perform an OR operation between the first output signal and a third bus data signal having a low logic value to output the first bus data signal.

3. The bus structure device according to claim 2, wherein: The first bus unit circuit further comprises: A second OR gate has a plurality of input terminals coupled to the first bus and an output terminal coupled to a pin of the first circuit.

4. The bus structure device according to claim 3, wherein: The second bus unit circuit includes: a third OR gate, wherein a plurality of input terminals of the third OR gate are coupled to the first bus, and an output terminal of the third OR gate is used to output the first input signal to the second circuit.

5. The bus structure device according to claim 4, wherein: The second bus unit circuit further comprises: A fourth OR gate and a fifth OR gate have a plurality of input terminals coupled together at a pin of the second circuit, the plurality of input terminals being connected to a ground voltage.

6. The bus structure device according to claim 1, wherein: Further including: a second bus; and a third bus unit circuit and a fourth bus unit circuit; wherein the second circuit is further coupled to the second bus via the third bus unit circuit, and the third bus unit circuit is used to transmit a second output signal from the second circuit as a third bus data signal on the second bus, and The first circuit is coupled to the second bus via the fourth bus unit circuit, and the fourth bus unit circuit is used to perform an OR operation between the third bus data signal and the fourth bus data signal on the second bus to generate a second input signal to the first circuit.

7. The bus structure device according to claim 6, wherein: Further including: a third bus; and a fifth bus unit circuit coupled between the third bus and the first circuit and a sixth bus unit circuit coupled between the third bus and the second circuit, wherein the fifth bus unit circuit is used to transmit a third output signal from the first circuit as a fifth bus data signal on the third bus, and The sixth bus unit circuit is configured to perform an OR operation between the fifth bus data signal and a sixth bus data signal on the third bus to generate a third input signal to the second circuit.

8. The bus structure device according to claim 7, wherein: Further including: a fourth bus, The first bus unit circuit includes: A logic circuit is coupled to the first bus and the fourth bus and is used to transmit the first bus data signal from the first bus to the fourth bus.

9. A bus structure device, characterized in that: Include: A first die comprising: a first circuit and a second circuit; a plurality of first buses; and a plurality of first bus unit circuits, wherein the first circuit and the second circuit are coupled to the plurality of first buses via the plurality of first bus unit circuits, Each of the plurality of first bus unit circuits is configured to perform an OR operation based on a plurality of input signals on a corresponding first bus among the plurality of first buses coupled to the first bus unit circuit to generate a corresponding bus data signal.

10. A bus structure device, characterized in that: Include: A first die comprising: a first circuit and a second circuit; a plurality of first buses; a plurality of first bus unit circuits, wherein the first circuit and the second circuit are coupled to the plurality of first buses via the plurality of first bus unit circuits, wherein each of the plurality of first bus unit circuits is configured to perform an OR operation based on a plurality of input signals on a corresponding first bus among the plurality of first buses coupled to the first bus unit circuit to generate a corresponding bus data signal; a plurality of second bus unit circuits coupled to a portion of the plurality of first buses; and a first connection circuit coupled to the portion of the plurality of first buses via the plurality of second bus unit circuits; and a second die comprising: a third circuit; a plurality of second buses coupled to the third circuit; a plurality of third bus unit circuits coupled to the plurality of second buses; and a second connection circuit coupled to the plurality of second buses via the plurality of third bus unit circuits, The first connecting circuit and the second connecting circuit are coupled to each other.

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