Circuit for simulating JTAG to load FPGA at high speed
By setting a switching circuit unit between the MCU and the FPGA, using the time-sharing analog switching of the GPIO and SPI interface groups, the problem of slow loading rate caused by the low GPIO flip frequency of the MCU is solved, and the rapidity of analog JTAG loading FPGA is achieved.
Patent Information
- Application Number
- CN202422241985.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-09-12
AI Technical Summary
The low GPIO flip frequency of the MCU leads to a very slow rate when loading the FPGA in analog JTAG, which cannot meet the load rate requirements of some application scenarios that require startup time, and lacks a mode switching circuit for 8-bit/non-8-bit integer multiple read and write.
A circuit that simulates JTAG high-speed loading of FPGAs is designed. By setting a switching circuit unit between the MCU chip unit and the FPGA chip unit, using the time-sharing analog switching of the GPIO interface group and the SPI interface group, selecting a suitable channel to connect the FPGA, solving the hardware speed limit between the MCU and the FPGA.
It realizes the selection of suitable channels to connect FPGAs in different situations, solves the speed limit between the MCU and FPGA, improves the loading rate, and meets the requirements for startup time.
Smart Images
Figure CN223296372U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronic circuit design, in particular to a circuit for simulating JTAG high-speed loading of FPGA. Background Art
[0002] In a project, the MCU usually loads the FPGA via Slave-Serial or Slave SelectMAP. However, in some applications where the FPGA needs to be reconfigured, these methods are not suitable.
[0003] Therefore, a more convenient loading method is to use the MCU to simulate JTAG for secondary reconfiguration loading. However, due to the low GPIO toggle frequency of the MCU, the simulated JTAG loading rate is very slow when performing 8-bit integer multiples of reads and writes. In some application scenarios with strict boot time requirements, the loading speed of the FPGA using this method is insufficient and may even fail to meet the boot requirements. The reason is that there is a hardware speed limitation between the MCU and FPGA that cannot be circumvented through software improvements, and there is a lack of mode switching circuitry for 8-bit / non-8-bit integer multiples of reads and writes.
[0004] Therefore, a circuit for simulating JTAG high-speed loading of FPGA is needed to solve the above technical problems. Utility Model Content
[0005] In order to solve the above technical problems, the utility model provides a circuit for simulating JTAG high-speed loading of FPGA, including an MCU chip unit, a switching circuit unit and an FPGA chip unit; wherein,
[0006] The MCU chip unit includes an MCU chip body, a GPIO interface group and an SPI interface group; wherein the MCU chip body is electrically connected to the GPIO interface group and the SPI interface group respectively, and the GPIO interface group is also electrically connected to the switching circuit unit and the FPGA chip unit respectively; the SPI interface group is also electrically connected to the switching circuit unit;
[0007] The switching circuit unit includes a switching circuit body, a switching circuit input interface group, and a switching circuit output interface group; wherein the switching circuit body is electrically connected to the GPIO interface group and the SPI interface group respectively through the switching circuit input interface group, and is electrically connected to the FPGA chip unit through the switching circuit output interface group;
[0008] The FPGA chip unit includes an FPGA chip body and a JTAG standard interface group; wherein, the FPGA chip body is electrically connected to the GPIO interface group of the MCU chip unit and the switching circuit output interface group of the switching circuit unit through the JTAG standard interface group.
[0009] As a further solution, the GPIO interface group includes a GPIO1 interface, a GPIO2 interface, a GPIO3 interface, a GPIO4 interface and a GPIO5 interface; wherein, the GPIO1 interface, the GPIO2 interface and the GPIO5 interface are electrically connected to the JTAG standard interface group respectively; the GPIO3 interface and the GPIO4 interface are electrically connected to the switching circuit input interface group respectively.
[0010] As a further solution, the SPI interface group includes an SPI_MOSI interface, an SPI_CLK interface and an SPI_CS interface; wherein the SPI_MOSI interface, SPI_CLK interface and SPI_CS interface are electrically connected to the switching circuit input interface group respectively.
[0011] As a further solution, the JTAG standard interface group includes a DONE interface, a TMS interface, a TDO interface, a TDI interface and a TCK interface; wherein the DONE interface, the TMS interface and the TDO interface are electrically connected to the GPIO interface group respectively; the TDI interface and the TCK interface are electrically connected to the switching circuit output interface group respectively.
[0012] As a further solution, the switching circuit body includes an electronic switching switch U2 and a switch peripheral switching circuit; wherein, the electronic switching switch U2 is provided with a 1A0 port, a 1A1 port, a 2A0 port, a 2A1 port, a 1Y0 port, a 1Y1 port, a 2Y0 port, a 2Y1 port, a 1 Port, 2 port, VCC port and GND port; the 1A0 port and 1A1 port are electrically connected to the GPIO interface group respectively, the 2A0 port and 2A1 port are electrically connected to the SPI interface group respectively, the 1Y0 port and 2Y0 port are electrically connected to the TCK interface of the JTAG standard interface group respectively, and the 1Y1 port and 2Y1 port are electrically connected to the TDI interface of the JTAG standard interface group respectively.
[0013] As a further solution, the 1A0 port of the electronic switch U2 is electrically connected to the GPIO3 port of the GPIO interface group, and the 1A1 port of the electronic switch U2 is electrically connected to the GPIO4 port of the GPIO interface group.
[0014] As a further solution, the 2A0 port of the electronic switch U2 is electrically connected to the SPI_CLK interface of the SPI interface group, and the 2A1 port of the electronic switch U2 is electrically connected to the SPI_MOSI interface of the SPI interface group.
[0015] As a further solution, the switch peripheral switching circuit includes a power supply VCC, a power supply GND, a capacitor C2, a resistor R3, a resistor R4, a MOS transistor Q3, and a MOS transistor Q4; wherein the power supply VCC is electrically connected to the VCC port, the power supply GND is electrically connected to the GND port, and the capacitor C2 is arranged between the VCC port and the GND port; the drain D of the MOS transistor Q3 and one end of the resistor R3 are electrically connected to the 2 The gate G of the MOS tube Q3, the drain D of the MOS tube Q4 and one end of the resistor R4 are electrically connected to the 1 The other end of the resistor R4 is electrically connected to the power supply GND, the source S of the MOS transistor Q3 and the MOS transistor Q4 are electrically connected to the power supply GND respectively, and the gate G of the MOS transistor Q4 is electrically connected to the SPI_CS interface of the SPI interface group.
[0016] As a further solution, the resistor R3 and the resistor R4 are both 4.7K ohm resistors, the capacitor C2 is a 0.1 uF capacitor, and the power supply VCC is a 3.3V DC power supply.
[0017] As a further solution, the MOS transistor Q3 and the MOS transistor Q4 are both configured as NMOS type MOS transistors.
[0018] Compared with related technologies, the circuit for simulating JTAG high-speed loading of FPGA provided by the present invention has the following beneficial effects:
[0019] The utility model includes an MCU chip unit, a switching circuit unit and an FPGA chip unit; wherein the MCU chip unit includes an MCU chip body, a GPIO interface group and an SPI interface group; the switching circuit unit includes a switching circuit body, a switching circuit input interface group and a switching circuit output interface group; the FPGA chip unit includes an FPGA chip body and a JTAG standard interface group; the switching circuit unit provides hardware switching support for time-sharing analog switching of the GPIO and SPI buses; the FPGA chip unit is connected via the GPIO interface group when reading and writing non-8-bit integer multiples, and then the SPI interface group is used to connect the FPGA chip unit when reading and writing 8-bit integer multiples; the circuit provided by the utility model enables the MCU to select an appropriate channel to connect to the FPGA in different situations, thereby solving the problem of hardware speed limitation between the MCU and the FPGA and the lack of a mode switching circuit for 8-bit / non-8-bit integer multiple reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of a circuit for simulating JTAG high-speed loading of FPGA provided by the utility model;
[0021] Figure 2 This is a circuit diagram of a switching circuit body provided by the utility model. DETAILED DESCRIPTION
[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.
[0023] Example 1
[0024] like Figure 1 As shown, this embodiment provides a circuit for simulating JTAG high-speed loading of FPGA, including an MCU chip unit, a switching circuit unit and an FPGA chip unit; wherein,
[0025] The MCU chip unit includes an MCU chip body, a GPIO interface group and an SPI interface group; wherein the MCU chip body is electrically connected to the GPIO interface group and the SPI interface group respectively, and the GPIO interface group is also electrically connected to the switching circuit unit and the FPGA chip unit respectively; the SPI interface group is also electrically connected to the switching circuit unit;
[0026] The switching circuit unit includes a switching circuit body, a switching circuit input interface group, and a switching circuit output interface group; wherein the switching circuit body is electrically connected to the GPIO interface group and the SPI interface group respectively through the switching circuit input interface group, and is electrically connected to the FPGA chip unit through the switching circuit output interface group;
[0027] The FPGA chip unit includes an FPGA chip body and a JTAG standard interface group; wherein, the FPGA chip body is electrically connected to the GPIO interface group of the MCU chip unit and the switching circuit output interface group of the switching circuit unit through the JTAG standard interface group.
[0028] It should be noted that due to the low MCU GPIO toggle frequency (generally no more than 2MHz), when using the MCU's GPIO to simulate JTAG loading of the FPGA, the read and write speed for 8-bit integer multiples is very slow. In some scenarios where device startup time is critical and JTAG secondary reconfiguration is required, it cannot meet the requirements of fast loading and startup.
[0029] However, the lack of relevant hardware circuit support means that the SPI interface group with high-speed characteristics cannot participate in the FPGA loading process. To this end, this embodiment sets a switching circuit unit between the MCU chip unit and the FPGA chip unit, and uses the switching circuit unit to provide hardware support for time-sharing analog switching between the GPIO and SPI buses. The GPIO interface group is used to connect to the FPGA chip unit when reading and writing non-8-bit integer multiples, and then the SPI interface group is used to connect to the FPGA chip unit when reading and writing 8-bit integer multiples. The circuit provided by the utility model enables the MCU to select the appropriate channel to connect to the FPGA in different situations, thereby resolving the hardware speed limitation between the MCU and FPGA and the lack of a mode switching circuit for 8-bit / non-8-bit integer multiple reading and writing.
[0030] As a further solution, the GPIO interface group includes a GPIO1 interface, a GPIO2 interface, a GPIO3 interface, a GPIO4 interface and a GPIO5 interface; wherein, the GPIO1 interface, the GPIO2 interface and the GPIO5 interface are electrically connected to the JTAG standard interface group respectively; the GPIO3 interface and the GPIO4 interface are electrically connected to the switching circuit input interface group respectively.
[0031] As a further solution, the SPI interface group includes an SPI_MOSI interface, an SPI_CLK interface and an SPI_CS interface; wherein the SPI_MOSI interface, SPI_CLK interface and SPI_CS interface are electrically connected to the switching circuit input interface group respectively.
[0032] As a further solution, the JTAG standard interface group includes a DONE interface, a TMS interface, a TDO interface, a TDI interface and a TCK interface; wherein the DONE interface, the TMS interface and the TDO interface are electrically connected to the GPIO interface group respectively; the TDI interface and the TCK interface are electrically connected to the switching circuit output interface group respectively.
[0033] It should be noted that: Figure 1 As shown, the MCU of this embodiment receives the DONE signal sent by the JTAG standard interface group through the GPIO5 interface, sends a simulated TMS signal to the TMS interface of the JTAG standard interface group through the GPIO1 interface, simulates the TDI interface through the GPIO2 interface and receives the signal sent by the TDO interface group; when using GPIO to simulate TCK and TDO, the simulated TDO signal is sent to the TDI interface of the JTAG standard interface through the GPIO4 interface, and the simulated TCK signal is sent to the TCK interface of the JTAG standard interface through the GPIO3 interface.
[0034] When using SPI to simulate TCK and TDO, the SPI_CLK interface and SPI_MOSI interface are the clock signal interface and data output signal interface of the MCU's SPI bus respectively, which are connected to the TCK interface and TDI interface port of the FPGA's JTAG standard interface group through the switching circuit; the SPI_CS interface is the SPI chip select signal interface and also the switching signal interface of the switching circuit. When it is high, the switching circuit connects the GPIO analog TCK and TDO interfaces, and when it is low, it connects the SPI analog TCK and TDO interfaces.
[0035] Example 2
[0036] like Figure 2 As shown, a switching circuit body provided in this embodiment includes an electronic switching switch U2 and a switch peripheral switching circuit; wherein, the electronic switching switch U2 is provided with a 1A0 port, a 1A1 port, a 2A0 port, a 2A1 port, a 1Y0 port, a 1Y1 port, a 2Y0 port, a 2Y1 port, a 1 Port, 2 port, VCC port and GND port; the 1A0 port and 1A1 port are electrically connected to the GPIO interface group respectively, the 2A0 port and 2A1 port are electrically connected to the SPI interface group respectively, the 1Y0 port and 2Y0 port are electrically connected to the TCK interface of the JTAG standard interface group respectively, and the 1Y1 port and 2Y1 port are electrically connected to the TDI interface of the JTAG standard interface group respectively.
[0037] As a further solution, the 1A0 port of the electronic switch U2 is electrically connected to the GPIO3 port of the GPIO interface group, and the 1A1 port of the electronic switch U2 is electrically connected to the GPIO4 port of the GPIO interface group.
[0038] As a further solution, the 2A0 port of the electronic switch U2 is electrically connected to the SPI_CLK interface of the SPI interface group, and the 2A1 port of the electronic switch U2 is electrically connected to the SPI_MOSI interface of the SPI interface group.
[0039] As a further solution, the switch peripheral switching circuit includes a power supply VCC, a power supply GND, a capacitor C2, a resistor R3, a resistor R4, a MOS transistor Q3, and a MOS transistor Q4; wherein the power supply VCC is electrically connected to the VCC port, the power supply GND is electrically connected to the GND port, and the capacitor C2 is arranged between the VCC port and the GND port; the drain D of the MOS transistor Q3 and one end of the resistor R3 are electrically connected to the 2 The gate G of the MOS tube Q3, the drain D of the MOS tube Q4 and one end of the resistor R4 are electrically connected to the 1 The other end of the resistor R4 is electrically connected to the power supply GND, the source S of the MOS transistor Q3 and the MOS transistor Q4 are electrically connected to the power supply GND respectively, and the gate G of the MOS transistor Q4 is electrically connected to the SPI_CS interface of the SPI interface group.
[0040] It should be noted that the electronic switch U2 of this embodiment uses a two-channel high-speed electronic switch (model SM3244). When using SPI to simulate TCK and TDO, the chip select signal output of the SPI_CS interface is low. At this time, the MOS tube Q4 cannot be turned on, and the 1 of the electronic switch U2 The port is pulled high, MOS tube Q3 is turned on, and the 2 The port is pulled low; when the SPI simulation TCK and TDO are completed, the SPI_CS interface outputs a high level. At this time, the MOS tube Q4 cannot be turned on, and the 1 of the electronic switching switch U2 The interface is pulled low, MOS tube Q3 cannot be turned on, and the 2 The port is pulled high. The specific corresponding relationship is shown in Table 1 below:
[0041] Table 1 Correspondence between the SPI_CS interface and the level of the electronic switch U2
[0042]
[0043] As a further solution, the resistor R3 and the resistor R4 are both 4.7K ohm resistors, the capacitor C2 is a 0.1 uF capacitor, and the power supply VCC is a 3.3V DC power supply.
[0044] As a further solution, the MOS transistor Q3 and the MOS transistor Q4 are both configured as NMOS type MOS transistors.
[0045] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A circuit for simulating JTAG high-speed loading of FPGA, characterized in that: It includes MCU chip unit, switching circuit unit and FPGA chip unit; among them, The MCU chip unit includes an MCU chip body, a GPIO interface group and an SPI interface group; wherein the MCU chip body is electrically connected to the GPIO interface group and the SPI interface group respectively, and the GPIO interface group is also electrically connected to the switching circuit unit and the FPGA chip unit respectively; the SPI interface group is also electrically connected to the switching circuit unit; The switching circuit unit includes a switching circuit body, a switching circuit input interface group, and a switching circuit output interface group; wherein the switching circuit body is electrically connected to the GPIO interface group and the SPI interface group respectively through the switching circuit input interface group, and is electrically connected to the FPGA chip unit through the switching circuit output interface group; The FPGA chip unit includes an FPGA chip body and a JTAG standard interface group; wherein, the FPGA chip body is electrically connected to the GPIO interface group of the MCU chip unit and the switching circuit output interface group of the switching circuit unit through the JTAG standard interface group.
2. The circuit for simulating JTAG high-speed loading of FPGA according to claim 1, characterized in that: The GPIO interface group includes a GPIO1 interface, a GPIO2 interface, a GPIO3 interface, a GPIO4 interface and a GPIO5 interface; wherein the GPIO1 interface, the GPIO2 interface and the GPIO5 interface are electrically connected to the JTAG standard interface group respectively; the GPIO3 interface and the GPIO4 interface are electrically connected to the switching circuit input interface group respectively.
3. The circuit for simulating JTAG high-speed loading of FPGA according to claim 1, characterized in that: The SPI interface group includes an SPI_MOSI interface, an SPI_CLK interface and an SPI_CS interface; wherein the SPI_MOSI interface, the SPI_CLK interface and the SPI_CS interface are electrically connected to the switching circuit input interface group respectively.
4. The circuit for simulating JTAG high-speed loading of FPGA according to claim 1, characterized in that: The JTAG standard interface group includes a DONE interface, a TMS interface, a TDO interface, a TDI interface and a TCK interface; wherein the DONE interface, TMS interface and TDO interface are electrically connected to the GPIO interface group respectively; the TDI interface and TCK interface are electrically connected to the switching circuit output interface group respectively.
5. The circuit for simulating JTAG high-speed loading of FPGA according to claim 4, characterized in that: The switching circuit body includes an electronic switching switch U2 and a switch peripheral switching circuit; wherein the electronic switching switch U2 is provided with a 1A0 port, a 1A1 port, a 2A0 port, a 2A1 port, a 1Y0 port, a 1Y1 port, a 2Y0 port, a 2Y1 port, a 1 Port, 2 port, VCC port and GND port; the 1A0 port and 1A1 port are electrically connected to the GPIO interface group respectively, the 2A0 port and 2A1 port are electrically connected to the SPI interface group respectively, the 1Y0 port and 2Y0 port are electrically connected to the TCK interface of the JTAG standard interface group respectively, and the 1Y1 port and 2Y1 port are electrically connected to the TDI interface of the JTAG standard interface group respectively.
6. The circuit for simulating JTAG high-speed loading of FPGA according to claim 5, characterized in that: The 1A0 port of the electronic switch U2 is electrically connected to the GPIO3 port of the GPIO interface group, and the 1A1 port of the electronic switch U2 is electrically connected to the GPIO4 port of the GPIO interface group.
7. The circuit for simulating JTAG high-speed loading of FPGA according to claim 5, characterized in that: The 2A0 port of the electronic switch U2 is electrically connected to the SPI_CLK port of the SPI interface group, and the 2A1 port of the electronic switch U2 is electrically connected to the SPI_MOSI port of the SPI interface group.
8. The circuit for simulating JTAG high-speed loading of FPGA according to claim 5, characterized in that: The switch peripheral switching circuit includes a power supply VCC, a power supply GND, a capacitor C2, a resistor R3, a resistor R4, a MOS transistor Q3, and a MOS transistor Q4; wherein the power supply VCC is electrically connected to the VCC port, the power supply GND is electrically connected to the GND port, and the capacitor C2 is arranged between the VCC port and the GND port; the drain D of the MOS transistor Q3 and one end of the resistor R3 are electrically connected to the 2 The gate G of the MOS tube Q3, the drain D of the MOS tube Q4 and one end of the resistor R4 are electrically connected to the 1 The other end of the resistor R4 is electrically connected to the power supply GND, the source S of the MOS transistor Q3 and the MOS transistor Q4 are electrically connected to the power supply GND respectively, and the gate G of the MOS transistor Q4 is electrically connected to the SPI_CS interface of the SPI interface group.
9. The circuit for simulating JTAG high-speed loading of FPGA according to claim 8, characterized in that: The resistor R3 and the resistor R4 are both 4.7K ohm resistors, the capacitor C2 is a 0.1uF capacitor, and the power supply VCC is a 3.3V DC power supply.
10. The circuit for simulating JTAG high-speed loading of FPGA according to claim 8, characterized in that: The MOS transistor Q3 and the MOS transistor Q4 are both configured as NMOS type MOS transistors.