Dynamic random access memory chip

Abstract

The utility model discloses a dynamic random access memory chip, which comprises a dynamic random access memory and a silicon capacitor which are sealed in a substrate, and the silicon capacitor is connected in parallel with a power supply pin end of the dynamic random access memory. The DRAM Die and the silicon capacitor are directly sealed in the packaging substrate, so that the equivalent inductance can be reduced to the minimum extent, the maximum capacitance performance benefit can be obtained, the stray noise of a power supply can be effectively filtered out under the high working frequency, and the DRAM high-frequency working signal quality can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a dynamic random access memory chip. Background Art

[0002] Due to process deviations in the DRAM manufacturing process, the working eye diagram waveform of the DRAM chip with large process deviations contains many stray waveforms, resulting in many glitches in the eye diagram and unclear eye diagram, which leads to misreading when reading data. Summary of the Invention

[0003] The present application provides a dynamic random access memory chip to solve the problems existing in the related art.

[0004] In a first aspect, the present invention provides a dynamic random access memory chip, comprising a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory, and wherein the dynamic random access memory chip is used to filter power supply noise signals under high-frequency signals.

[0005] Optionally, during sealing, the silicon capacitors are arranged around the dynamic random access memory.

[0006] Optionally, during sealing, the silicon capacitor is arranged above the dynamic memory.

[0007] Optionally, during sealing, an RDL layer is laid above the dynamic memory, and the silicon capacitor is connected to a power pin end of the dynamic memory through the RDL layer.

[0008] Optionally, the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, which includes: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

[0009] Optionally, when multiple silicon capacitors are connected in parallel, the silicon capacitors are connected in parallel.

[0010] In a second aspect, the present invention provides an electronic device terminal, comprising the dynamic random access memory chip described in any one of the first aspects.

[0011] The present invention discloses a dynamic random access memory chip comprising a dynamic random access memory (DRAM) and a silicon capacitor encapsulated within a substrate, wherein the silicon capacitor is connected in parallel to the DRAM power pin. By encapsulating the DRAM die and silicon capacitor directly within the package substrate, equivalent inductance is minimized, maximizing capacitor performance gains. At high operating frequencies, this effectively filters out power supply stray noise, significantly improving the quality of the DRAM's high-frequency operating signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0013] Figure 1 This is a schematic diagram of an application circuit structure of a dynamic random access memory chip of the present application;

[0014] Figure 2 This is a side view of a packaging structure of a dynamic random access chip of the present application;

[0015] Figure 3 This is a top view of a packaging structure of a dynamic random access memory chip of the present application;

[0016] Figure 4a A structural side view of the dynamic random access memory chip packaged for this application;

[0017] Figure 4b A top view of the structure of the dynamic random access memory chip packaged for this application;

[0018] Figure 4c This is a schematic diagram of a specific structure of a dynamic random access memory chip of the present application;

[0019] Figure 5 This is a side view of another packaging structure of a dynamic random access memory chip of the present application;

[0020] Figure 6 This is a top view of another packaging structure of a dynamic random access memory chip of the present application;

[0021] Figure 7a A side view of another packaging structure of the dynamic random access memory chip packaged for this application;

[0022] Figure 7b A top view of another packaging structure of the dynamic random access memory chip packaged for this application;

[0023] Figure 7c This is another specific structural diagram of a dynamic random access memory chip of the present application. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] The following is combined with Figure 1 A dynamic random access memory chip is exemplarily described, including a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to a power pin end of the dynamic random access memory.

[0026] In this embodiment, due to process variations in the DRAM manufacturing process, the operating eye diagram waveform of DRAM chips with large process variations contains many spurious waveforms, resulting in numerous glitches and unclear eye diagrams, leading to misreading when reading data. To address this issue, the DRAM power supply itself can be made cleaner, reducing the impact of power load variations and thereby enhancing the signal quality of the DRAM data.

[0027] This embodiment can minimize the equivalent inductance and maximize the capacitor performance benefit by directly sealing the DRAM die and silicon capacitor in the package substrate. At high operating frequencies, it can effectively filter out power supply stray noise, effectively improving the quality of the DRAM high-frequency operating signal.

[0028] As an optional implementation of this embodiment, during the sealing process, the silicon capacitors are arranged around the dynamic random access memory.

[0029] In this optional implementation, refer to Figure 2 The side view after sealing is shown. Figure 3 The top view after sealing is shown. Figure 2 and Figure 3 It can be seen that the silicon capacitors are arranged around the dynamic random access memory, and after packaging, the power pins are connected in parallel with the silicon capacitors.

[0030] Schematic diagram reference after packaging is completed Figure 4a is a side view, Figure 4b This is a top view.

[0031] More specifically, refer to Figure 4cThe package size of dynamic random access memory chips follows the JEDEC standard. If the package is a single-die chip with ample internal space, the silicon capacitors can be distributed on both sides of the die. C101 to C104, C201 to C204, and C301 to C304 are all silicon capacitors distributed between the substrate pad (P101) and the DRAM die pad (P201), as well as between the substrate pad (P102) and the DRAM die pad (P202). Regarding the capacitance size, C101 is larger than C102, C201 is larger than C202, and C301 is larger than C302; C104 is larger than C103, C204 is larger than C203, and C304 is larger than C303. In terms of placement position, C101, C201 and C301 are close to P101; C102, C202 and C302 are close to P201; C103, C203 and C303 are close to P202; C104, C204 and C304 are close to P102; C101 and C102 are in parallel, C201 and C202 are in parallel, C301 and C302 are in parallel; C103 and C104 are in parallel, C203 and C204 are in parallel, C303 and C304 are in parallel; all capacitors are connected in parallel between VDD and GND.

[0032] As an optional implementation of this embodiment, when the package is closed, the silicon capacitor is arranged above the dynamic memory.

[0033] In this optional implementation, refer to Figure 5 The side view after sealing is shown. Figure 6 The top view after sealing is shown. Figure 5 and Figure 6 It can be seen that the silicon capacitor is arranged on top of the dynamic random access memory, and this structure can shorten the pin distance.

[0034] Schematic diagram reference after packaging is completed Figure 7a is a side view, Figure 7b This is a top view.

[0035] More specifically, see Figure 7c The package size of dynamic random access memory chips follows the JEDEC standard. If the package is a multi-die chip with limited internal space, the silicon capacitor needs to be placed directly above the DRAM die. After the silicon capacitor is placed in this way, the silicon capacitor distribution is similar to Figure 4c The positions of the silicon capacitors are the same except for the difference in position. The positions of the silicon capacitors need to be swapped as follows: C101 and C102, C201 and C202, C301 and C302; C104 and C103, C204 and C203, and C304 and C303.

[0036] As an optional implementation of this embodiment, during sealing, an RDL layer is provided above the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer.

[0037] In this optional implementation, an RDL layer is provided above the dynamic memory, and then the power pin end and the silicon capacitor are connected based on the RDL layer.

[0038] As an optional implementation of this embodiment, the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, including: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

[0039] As an optional implementation of this embodiment, when multiple silicon capacitors are connected in parallel, the silicon capacitors are connected in parallel.

[0040] In this optional implementation, one or more silicon capacitors are connected in parallel to the DRAM die power pins for package sealing. The specific number of silicon capacitors can be determined based on actual circuit simulation results.

[0041] After encapsulation, the DRAM chip does not require PCB-level capacitors for decoupling and filtering.

[0042] As an optional implementation of this embodiment, the dynamic random access memory chip is used to filter the power supply noise signal under the high frequency signal.

[0043] By connecting one or more silicon capacitors in parallel to the DRAM die power pins for filtering, the DRAM chip's operating eye diagram becomes smoother and data reading becomes more accurate. Sealing the DRAM die and silicon capacitors directly within the package substrate minimizes equivalent inductance and maximizes capacitor performance. At high operating frequencies, this effectively filters out power supply stray noise, significantly improving the quality of DRAM high-frequency operating signals.

[0044] The present application also provides an electronic device terminal, which can be a terminal device with different uses, and a dynamic random access memory chip is integrated in the device content, and the dynamic random access memory chip includes a dynamic random access memory and a silicon capacitor sealed in a substrate, wherein the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory. When sealed, the silicon capacitor is arranged around the dynamic random access memory. When sealed, the silicon capacitor is arranged above the dynamic memory. When sealed, an RDL layer is laid above the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer. The silicon capacitor connected in parallel to the power pin end of the dynamic random access memory includes: each power pin end of the dynamic random access memory is connected in parallel with one or more silicon capacitors. When multiple silicon capacitors are connected in parallel, each silicon capacitor is in a parallel relationship. The dynamic random access memory chip is used to filter the power supply noise signal under high-frequency signals.

[0045] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made thereto. Therefore, such modifications and improvements, without departing from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A dynamic random access memory chip, characterized in that: include: A dynamic random access memory and a silicon capacitor are sealed in a substrate, wherein the silicon capacitor is connected in parallel to the power pin end of the dynamic random access memory, and wherein the dynamic random access memory chip is used to filter the power supply noise signal under the high frequency signal.

2. The dynamic random access memory chip according to claim 1, wherein: When the package is closed, the silicon capacitors are arranged around the dynamic random access memory.

3. The dynamic random access memory chip according to claim 1, wherein: When the package is closed, the silicon capacitor is arranged above the dynamic memory.

4. The dynamic random access memory chip according to claim 3, wherein: During the sealing process, an RDL layer is laid on the dynamic memory, and the silicon capacitor is connected to the power pin end of the dynamic memory through the RDL layer.

5. The dynamic random access memory chip according to claim 1, wherein: The silicon capacitor connected in parallel to the power pin end of the dynamic random access memory includes: Each power pin of the dynamic random access memory is connected in parallel with one or more silicon capacitors.

6. The dynamic random access memory chip according to claim 5, wherein: When multiple silicon capacitors are connected in parallel, the silicon capacitors are in a parallel relationship.

7. An electronic equipment terminal, characterized in that: A dynamic random access memory chip comprising any one of items 1-6.

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