Consumption reduction framework and controller

Abstract

The utility model discloses a consumption reduction architecture and a controller. The consumption reduction architecture comprises a power supply module, a power supply management integration module and a pre-stage DCDC step-down circuit. The input end of the pre-stage DCDC step-down circuit is electrically connected with the output end of the power supply module, and the first output end of the pre-stage DCDC step-down circuit is electrically connected with the input end of the power supply management integrated module so as to reduce the voltage input into the power supply management integrated module. The consumption reduction architecture can reduce self-heating of the power management integrated module, reduce power consumption and improve thermal performance of products.

Description

Technical Field

[0001] The present application relates to the field of controller technology, and in particular to a power-saving architecture and a controller. Background Art

[0002] like Figure 1 As shown, in the controller architecture of the related technology, the 24V power supply KL30 enters the board through the clamping circuit and the anti-reverse protection circuit, and is divided into two paths, one is used as the power supply for the minimum system (power management integrated module, microprocessor, controller local area network), and the other is used as the power supply for the driver level.

[0003] The 24V power supply for the minimum system is converted to a 5V output via a single power management integrated circuit (PMIC). The 5V output is used to power the microcontroller unit (MCU) and the controller area network (CAN) chip. The wake-up portion of the CAN chip is powered by VBAT_DIA (24V). After receiving the wake-up frame, the CAN chip pulls the INH pin high, triggering the PMIC wake-up function and waking up the minimum system. At this time, the direct current (DC) motor pre-driver chip in the driver power supply section is directly powered by 24V, and the external full-bridge is also powered by 24V. The direct input of the high input voltage increases the voltage drop of the PMIC, which in turn increases the PMIC's own heat generation, power consumption, and reduced product thermal performance. At the same time, the controller architecture in the related art cannot meet the Local Interconnect Network (LIN) communication function. Summary of the Invention

[0004] The present application provides a power consumption reduction architecture to solve the problem of excessive heat generation of the PMIC itself in the prior art.

[0005] A power consumption reduction architecture, comprising:

[0006] Power module;

[0007] Power management integrated module; and

[0008] A front-stage DCDC buck circuit, wherein the input end of the front-stage DCDC buck circuit is electrically connected to the output end of the power module, and the first output end of the front-stage DCDC buck circuit is electrically connected to the input end of the power management integrated module, so as to reduce the voltage input to the power management integrated module.

[0009] Furthermore, it includes a load module, in which a pre-driver chip is arranged. The second output end of the front-stage DCDC buck circuit is electrically connected to the input end of the pre-driver chip to reduce the voltage input to the pre-driver chip.

[0010] Furthermore, the load module is a brushless motor, a solenoid valve or a DC motor.

[0011] Furthermore, the power management integrated module has a rear-stage DCDC buck circuit, which is connected in series between the front-stage DCDC buck circuit and the second output terminal of the power management integrated module.

[0012] Furthermore, a local area Internet chip is included, and the front-stage DCDC buck circuit is electrically connected to the power supply end of the local area Internet chip through the first output end of the power management integrated module, so that after the power management integrated module is awakened, the voltage at the output end of the front-stage DCDC buck circuit is input to the power supply end of the local area Internet chip, and the voltage at the output end of the front-stage DCDC buck circuit matches the operating voltage of the local area Internet chip.

[0013] Furthermore, a power switch is provided in the power management integrated module, and the power switch is arranged in series between the front-stage DCDC buck circuit and the first output terminal of the power management integrated module.

[0014] Furthermore, the second output end of the power management integrated module is electrically connected to the communication end of the local area Internet chip, so as to supply power to the communication end of the local area Internet chip after the power management integrated module is awakened.

[0015] Furthermore, the power consumption reduction architecture also includes a controller area network chip, the front-stage DCDC buck circuit is arranged in series between the power module and the power supply end of the controller area network chip, the voltage at the output end of the front-stage DCDC buck circuit matches the operating voltage of the controller area network chip, and the controller area network chip is configured to support specific frame wake-up.

[0016] Furthermore, the post-stage DCDC step-down circuit is electrically connected to the communication terminal of the controller area network chip through the second output terminal of the power management integrated module, and is used to power the communication terminal of the controller area network chip after the power management integrated module is awakened.

[0017] Furthermore, the front-stage DCDC step-down circuit is used to reduce the supply voltage of the power module to 14V-16V.

[0018] The technical solution of this application has at least the following advantages:

[0019] This application reduces the voltage drop of the power management integrated module, reduces the self-heating of the power management integrated module, reduces power consumption, and improves the thermal performance of the product.

[0020] The present application arranges the front-stage DCDC step-down circuit in series between the power module and the power management integrated module, so that the front-stage DCDC step-down circuit is electrically connected to the power supply end of the local area Internet chip through the first output end of the power management integrated module, thereby reducing the power supply voltage of the local area Internet chip, so that the voltage at the output end of the front-stage DCDC step-down circuit matches the operating voltage of the local area Internet chip, thereby meeting the requirements for LIN communication.

[0021] The present application arranges the front-stage DCDC step-down circuit in series between the power module and the power management integrated module, which reduces the withstand voltage of the power management integrated module and reduces the cost of the power management integrated module. Compared with the existing technology, the present application is more robust.

[0022] This application can select a controller LAN chip that supports specific frame wake-up, which has stronger support functions than arbitrary frame wake-up of other products.

[0023] The present application reduces the power consumption of the DC motor pre-driver chip itself, reduces costs, optimizes the overall heat dissipation design, and reduces the cost of the heat dissipation design. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 is a schematic diagram of a controller architecture in the related art;

[0026] Figure 2 It is a schematic diagram of the power saving architecture in this application. DETAILED DESCRIPTION

[0027] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0028] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0031] like Figure 1 As shown, the existing system has a 24V supply voltage. This 24V supply voltage passes through the power management integrated module, converting it into a 5V output voltage. The 5V output is used to power the MCU and the controller area network chip. The wake-up portion of the controller area network chip is powered by VBAT_DIA (24V). After receiving the wake-up frame, the controller area network chip pulls the INH pin high, triggering the power management integrated module's wake-up function and waking up the minimum system. The driver-stage power supply, including the DC motor pre-driver chip, is directly powered by 24V, as is the external full-bridge.

[0032] In the existing product architecture, the internal power module PIN VS of the DC motor pre-driver chip is directly powered by VBAT_DIA (24V). Due to the influence of high input voltage, the motor pre-driver chip itself has a large thermal power consumption. At the same time, existing commercial vehicles have more stringent requirements on temperature and lifespan. Therefore, the motor pre-driver chip needs to be upgraded from a grade 1 temperature level product to a grade 0. When VS is powered by 28V (the normal power-on voltage of a 24V system), the internal power consumption is 2.099W, which is high power consumption and high cost.

[0033] At the same time, existing technologies cannot meet the needs of commercial vehicle customers for LIN functions.

[0034] Figure 1 For the 24V system shown in the figure, ISO16750-2 clearly defines standards for load dump conditions. These standards include the unclamped PULSE 5A standard at the engine end, with a maximum pulse voltage of 202V (duration 350ms), and the clamped PULSE 5B waveform at the engine end, with a maximum pulse voltage of 58V. Currently, existing technologies can only meet the requirements of PULSE 5B. For the most stringent 202V PULSE 5A, while ensuring protection from the normal operating voltage (9-32V), the power management integrated module (PMIM) must still have a withstand voltage of 65V or above after clamping protection. Currently, most PIMs with a 40V withstand voltage, and a few with a 60V withstand voltage, cannot meet this requirement.

[0035] Due to limitations in Controller Area Network (CAN) chip capabilities, the VBAT withstand voltage of current CAN chips with specific frame wakeup capabilities does not exceed 40V, which cannot fully meet the 5A pulse load dump condition.

[0036] In view of the above problems, this embodiment proposes the following Figure 2 The power-saving architecture shown includes a power module 1, a front-stage DC-DC step-down circuit 2, and a power management integrated module 4. The power supply voltage of the power module 1 passes through two paths: one for powering the minimum system (power management integrated module, MCU, CAN), and one for powering the driver stage (DC). The power management integrated module 4 is the power module management circuit. The front-stage DC-DC step-down circuit 2 in this embodiment has a low-current, low-power mode that can control the quiescent current in standby mode to below 1mA.

[0037] In the circuit of the minimum system power supply, the front-stage DCDC buck circuit 2 is arranged in series between the power module 1 and the power management integrated module 4. The power management integrated module 4 has a rear-stage DCDC buck circuit 41. The current passing through the front-stage DCDC buck circuit 2 achieves a secondary voltage reduction after passing through the rear-stage DCDC buck circuit 41.

[0038] The power management integrated module 4 has a first output terminal, namely the VBS pin in the figure, and the power management integrated module 4 also has a second output terminal, namely Figure 2 The VDD5_COM pin in the .

[0039] After being stepped down by the post-stage DCDC step-down circuit 41, it is divided into two paths. One path is output to the controller LAN chip 6 and the LAN chip 5 through the second output terminal, and the other path is connected to the VCC of the motor pre-driver chip 7 (DC) through the VDD5 pin. Therefore, after the power supply voltage is stepped down twice, the power consumption of the motor pre-driver chip 7 and the heat generation of the power management integrated module 4 itself can be reduced. In this embodiment, the pre-stage DCDC step-down circuit 2 reduces the power supply voltage of the power module 1 to 14v-16v. Depending on the specific implementation environment, under certain circumstances, the pre-stage DCDC step-down circuit can also reduce the power supply voltage of the power module 1 to 14.002v-15.466v to ensure the voltage reduction effect.

[0040] In this embodiment, VCC in the motor pre-driver chip 7 represents digital IO power supply, VS represents main power supply, PWM represents square wave control input, SPI represents communication line, SOFF represents safety shutdown, and Current represents current sampling feedback.

[0041] In this embodiment, because a front-stage DCDC step-down circuit 2 is provided to step down the supply voltage, a power management integrated module 4 with a lower voltage resistance can be selected (it is understood that the power management integrated module includes a power management integrated chip), thereby reducing costs. Simultaneously, the rear-stage DCDC step-down circuit 41 steps down the lower input voltage, reducing the voltage drop of the power management integrated module 4, reducing the self-heating of the power management integrated module 4, reducing power consumption, and improving the thermal performance of the product. In this embodiment, a power management integrated module 4 with a voltage resistance of no more than 80V can be selected.

[0042] For example, the power supply voltage of the power module is 24V. After passing through the front-stage DCDC step-down circuit 2, the 24V is reduced to 14.002V. When input to the power management integrated module 4, it passes through the rear-stage DCDC step-down circuit 41 to reduce the voltage of 14.002V to 5V before output. Therefore, the existing technology directly reduces 24V to 5V output, while the architecture proposed in this embodiment is a 24V-14.002V-5V output mode, which can reduce the power consumption of the power management integrated module 4.

[0043] In terms of the PULSE 5A standard, since the voltage input to the power management integrated module 4 is reduced, the selection of voltage-resistant materials is wider, thereby being able to meet the PULSE 5A standard.

[0044] In this architecture, the voltage output by the pre-stage DCDC voltage drop circuit 2 is input via the VBAT_DIA pin to the main power supply pin of the CAN chip 6 for main power supply. If the supply voltage is higher, a CAN chip with specific frame wakeup is unsuitable, and only a CAN chip with any frame wakeup can be used. Because the pre-stage DCDC voltage drop circuit 2 reduces the supply voltage of the CAN chip 6, the CAN chip 6 in this embodiment is a CAN chip with specific frame wakeup, providing enhanced support. The operating voltage of the CAN chip 6 is compatible with the voltage output by the pre-stage DCDC voltage drop circuit 2.

[0045] This embodiment includes a local area network chip 5, adding LIN communication functionality. The power management integrated module 4 is connected to the VBS pin of the local area network chip 5 via its first output terminal, providing the main power supply for the local area network chip 5. The power management integrated module 4 is equipped with a power switch 42, which is arranged in series between the pre-stage DCDC voltage drop circuit 2 and the first output terminal. Specifically, the power switch 42 is connected to the local area network chip 5 via the VBS pin. This allows the power switch 42 to be turned off before the power management integrated module 4 wakes up, reducing the system's quiescent current. In this embodiment, the power management integrated module 4 is connected to the communication power pin of the local area network chip 5, VDD5_COM, for communication power supply. The operating voltage of the local area network chip 5 is compatible with the voltage output by the first output terminal.

[0046] The power switch 42 in this embodiment refers to the output of the input power module with a switch.

[0047] In this embodiment, when the controller LAN chip 6 is powered through the VBAT_DIA pin and a CAN signal with a specific frame wake-up is received, the PIN value of INH is pulled high, and then the power management integrated module 4 is enabled to wake up. After the power management integrated module 4 is awakened, the power management integrated module 4 supplies power to the controller LAN chip 6, the local Internet chip 5 and VCC for communication through the VDD5_COM pin.

[0048] In this embodiment, the motor pre-driver chip 7 is the load. The load module in this embodiment can also be a brushless motor, solenoid valve, etc. In this embodiment, after the supply voltage passes through the pre-stage DCDC step-down circuit 2, 14.002V is used to power the VS of the motor pre-driver chip 7, reducing power consumption to 0.862W. This is used for internal chip driving. The external full-bridge component is still driven by 24V (the supply voltage of the power module), meeting the vehicle's temperature durability requirements without increasing costs.

[0049] In this embodiment, based on the above architecture, the withstand voltage of the front-stage DCDC step-down circuit 2 does not exceed 80V, and the withstand voltage of the power management integrated module 4 does not exceed 40V. Specifically, a PMIC with a high DCDC voltage plus a 40V voltage is less expensive than a 60V PMIC and offers greater robustness.

[0050] This embodiment further provides a controller including the above-mentioned energy-saving architecture. It is understood that the controller in this embodiment may include a transmission controller or other controllers on the vehicle.

[0051] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A power-saving architecture, characterized in that: include: Power module; Power management integrated module; as well as A front-stage DCDC buck circuit, wherein the input end of the front-stage DCDC buck circuit is electrically connected to the output end of the power module, and the first output end of the front-stage DCDC buck circuit is electrically connected to the input end of the power management integrated module, so as to reduce the voltage input to the power management integrated module.

2. The power reduction architecture according to claim 1, wherein: It also includes a load module, in which a pre-driver chip is arranged. The second output end of the front-stage DCDC buck circuit is electrically connected to the input end of the pre-driver chip to reduce the voltage input to the pre-driver chip.

3. The power reduction architecture according to claim 2, wherein: The load module is a brushless motor, a solenoid valve or a DC motor.

4. The power reduction architecture according to any one of claims 1 to 3, characterized in that: The power management integrated module comprises a rear-stage DCDC buck circuit, which is connected in series between the front-stage DCDC buck circuit and the second output terminal of the power management integrated module.

5. The power reduction architecture according to claim 4, wherein: The system further includes a local area Internet chip, wherein the front-stage DCDC step-down circuit is electrically connected to the power supply end of the local area Internet chip through the first output end of the power management integrated module, so as to input the voltage of the output end of the front-stage DCDC step-down circuit to the power supply end of the local area Internet chip after the power management integrated module is awakened, and the voltage of the output end of the front-stage DCDC step-down circuit matches the operating voltage of the local area Internet chip.

6. The power consumption reduction architecture according to claim 5, characterized in that: The power management integrated module is provided with a power switch, and the power switch is arranged in series between the front-stage DCDC buck circuit and the first output terminal of the power management integrated module.

7. The power consumption reduction architecture according to claim 5, wherein: The second output end of the power management integrated module is electrically connected to the communication end of the local area Internet chip, and is used to supply power to the communication end of the local area Internet chip after the power management integrated module is awakened.

8. The power consumption reduction architecture according to claim 4, wherein: The power consumption reduction architecture also includes a controller area network chip. The front-stage DCDC buck circuit is arranged in series between the power module and the power supply end of the controller area network chip. The voltage at the output end of the front-stage DCDC buck circuit matches the operating voltage of the controller area network chip. The controller area network chip is configured to support specific frame wake-up.

9. The power consumption reduction architecture according to claim 8, wherein: The post-stage DCDC step-down circuit is electrically connected to the communication terminal of the controller area network chip through the second output terminal of the power management integrated module, and is used to supply power to the communication terminal of the controller area network chip after the power management integrated module is awakened.

10. The power consumption reduction architecture according to claim 1, wherein: The front-stage DCDC step-down circuit is used to reduce the supply voltage of the power module to 14V-16V.

11. A controller, characterized in that: The invention comprises the power-saving architecture according to any one of claims 1 to 10.

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