Semiconductor field effect transistor device
By adopting specific structures and contact methods in semiconductor field effect tube devices, the high opening voltage and long reverse recovery time of power MOS devices are solved, and low power loss and high reliability are achieved.
Patent Information
- Application Number
- CN202422306515.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-09-20
AI Technical Summary
The existing power MOS devices have high turn-on voltage, long reverse recovery time, large power loss, and insufficient device reliability.
A semiconductor field effect tube device is designed, using an N-type epitaxial layer and an N-type heavily doped layer, including a single cell and a trench structure arranged at intervals, using Schottky contacts in parallel with metal columns, combining deep trench and insulating dielectric layer to reduce the opening voltage and reverse recovery time and reduce leakage current.
It effectively reduces the device turn-on voltage, shortens the reverse recovery time, reduces power loss, and improves the device reliability.
Smart Images
Figure CN223297938U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a semiconductor field effect tube device. Background Art
[0002] Power MOS devices feature high integration, low on-resistance, fast switching speeds, and minimal switching losses, making them widely used in various power management and switching applications. With industrial development, demands for the power consumption and conversion efficiency of power MOS devices are becoming increasingly stringent. Existing power MOS devices suffer from high turn-on voltages, long reverse recovery times, and significant power losses. Summary of the Invention
[0003] The purpose of the utility model is to provide a semiconductor field effect transistor device, which effectively reduces the device turn-on voltage, shortens the device reverse recovery time, reduces power loss and also improves the overall reliability of the device.
[0004] To achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: a semiconductor field effect transistor device, comprising a silicon substrate having an N-type epitaxial layer and an N-type heavily doped layer, wherein the N-type heavily doped layer is located at the bottom of the silicon substrate, and an N-type epitaxial layer located above the N-type heavily doped layer is located in the middle and upper parts of the silicon substrate, a P-type well region is provided on the upper part of the N-type epitaxial layer, and two spaced-apart unit cells are provided on the P-type well region, the N-type epitaxial layer, and the N-type heavily doped layer;
[0005] The unit cell further includes a first trench, a second trench, and a shallow trench extending from the upper surface of the P-type well region into the N-type epitaxial layer, the shallow trench being located between the first trench and the second trench, the depths of the first trench and the second trench being greater than the depth of the shallow trench; the first trench and the second trench each have a gate silicon oxide layer on their inner walls, a first conductive polysilicon and a second conductive polysilicon are located in the first trench and the second trench, respectively; a first N-type source region is located above the P-type well region and around the first trench, a second N-type source region is located above the P-type well region and around the second trench, the shallow trench is located between the first N-type source region and the second N-type source region, and a metal column is located in the shallow trench; a first insulating dielectric layer and a second insulating dielectric layer respectively cover the first conductive polysilicon and the second conductive polysilicon;
[0006] A deep trench is provided between the N-type epitaxial layers of adjacent units, and the deep trench extends from the surface of the N-type epitaxial layer to the lower part, and the bottom end of the deep trench is located below the bottom ends of the first trench and the second trench respectively, and the deep trench is filled with an insulating dielectric layer; an upper metal electrode layer is located on the first insulating dielectric layer, the second insulating dielectric layer, the first N-type source region, the second N-type source region and the metal column, and the surface of the N-type heavily doped layer opposite to the N-type epitaxial layer has a lower metal electrode layer.
[0007] The further improved scheme in the above technical scheme is as follows:
[0008] 1. In the above solution, the width of the shallow groove is smaller than the width of the first groove and the second groove.
[0009] 2. In the above solution, the depth ratio of the first trench, the second trench and the shallow trench is 10:6~8.
[0010] 3. In the above solution, one end of the metal column contacts the first N-type source region, and the other end contacts the second N-type source region.
[0011] 4. In the above solution, the lower end of the deep trench is located in the middle of the N-type heavily doped layer.
[0012] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0013] 1. A semiconductor field-effect transistor device of the present invention comprises a first deep trench, a second deep trench, and a shallow trench extending from the upper surface of the P-type well region into the N-type epitaxial layer. The shallow trench is located between the first deep trench and the second deep trench. The depths of the first deep trench and the second deep trench are greater than those of the shallow trench. The shallow trench is located between the first N-type source region and the second N-type source region. A metal pillar is provided in the shallow trench. An upper metal electrode layer is located on the first N-type source region, the second N-type source region, and the metal pillar. The metal pillar is connected in parallel with the first N-type source region and the second N-type source region. The metal pillar forms a Schottky contact with the N-type epitaxial layer, thereby effectively reducing the device turn-on voltage, shortening the reverse recovery time of the device, and reducing the power loss of the device under high-frequency use.
[0014] 2. The semiconductor field effect transistor device of the present invention has two spaced-apart unit cells on its P-type well region, N-type epitaxial layer and N-type heavily doped layer, and a deep trench is provided between the N-type epitaxial layers of adjacent unit cells. The deep trench extends from the surface of the N-type epitaxial layer to the lower part, and the bottom end of the deep trench is located below the bottom ends of the first trench and the second trench respectively. The deep trench is filled with an insulating dielectric layer, which effectively avoids interference between unit cells, greatly reduces the probability of leakage current, and thus improves the overall reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Attachment Figure 1 This is a schematic structural diagram of a semiconductor field effect tube device of the present invention.
[0016] In the above figures: 1. N-type epitaxial layer; 2. N-type heavily doped layer; 3. Silicon substrate; 4. P-type well region; 51. First trench; 52. Second trench; 6. Shallow trench; 7. Gate silicon oxide layer; 81. First conductive polysilicon; 82. Second conductive polysilicon; 91. First N-type source region; 92. First N-type source region; 10. Metal pillar; 111. First insulating dielectric layer; 112. Second insulating dielectric layer; 12. Upper metal electrode layer; 13. Lower metal electrode layer; 14. Unit cell; 15. Deep trench; 16. Insulating dielectric layer portion. DETAILED DESCRIPTION
[0017] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.
[0018] Embodiment 1: A semiconductor field-effect transistor device comprises a silicon substrate 3 having an N-type epitaxial layer 1 and an N-type heavily doped layer 2, wherein the N-type heavily doped layer 2 is located at the bottom of the silicon substrate 3, and the N-type epitaxial layer 1 located above the N-type heavily doped layer 2 is located in the middle and upper portions of the silicon substrate 3. A P-type well region 4 is located at the upper portion of the N-type epitaxial layer 1, and two spaced-apart unit cells 14 are formed on the P-type well region 4, the N-type epitaxial layer 1, and the N-type heavily doped layer 2.
[0019] The unit cell 14 further includes a first trench 51, a second trench 52, and a shallow trench 6 extending from the upper surface of the P-type well region 4 to the N-type epitaxial layer 1. The shallow trench 6 is located between the first trench 51 and the second trench 52. The depths of the first trench 51 and the second trench 52 are greater than the depth of the shallow trench 6. The inner walls of the first trench 51 and the second trench 52 each have a gate silicon oxide layer 7. A first conductive polysilicon 81 and a second conductive polysilicon 82 are located in the first trench 51 and the second trench respectively. The first conductive polysilicon 81 and the second conductive polysilicon 82 are covered with a first insulating dielectric layer 111 and a second insulating dielectric layer 112 respectively; a first N-type source region 91 is provided on the upper portion of the P-type well region 4 and around the first trench 51; a second N-type source region 92 is provided on the upper portion of the P-type well region 4 and around the second trench 52; the shallow trench 6 is located between the first N-type source region 91 and the second N-type source region 92; a metal column 10 is provided in the shallow trench 6; a first insulating dielectric layer 111 and a second insulating dielectric layer 112 are respectively covered on the first conductive polysilicon 81 and the second conductive polysilicon 82;
[0020] A deep trench 15 is provided between the N-type epitaxial layers 1 of adjacent unit cells 14. The deep trench 15 extends from the surface of the N-type epitaxial layer 1 to the bottom. The bottom of the deep trench 15 is located below the bottom of each of the first trench 51 and the second trench 52. The deep trench 15 is filled with an insulating dielectric layer 16. An upper metal electrode layer 12 is located on the first insulating dielectric layer 111, the second insulating dielectric layer 112, the first N-type source region 91, the second N-type source region 92 and the metal pillar 10. The surface of the N-type heavily doped layer 2 opposite to the N-type epitaxial layer 1 has a lower metal electrode layer 13.
[0021] The width of the shallow trench 6 is smaller than the width of the first trench 51 and the second trench 52 .
[0022] The depth ratio of the first trench 51 , the second trench 52 and the shallow trench 6 is 10:6.5.
[0023] Example 2: A semiconductor field-effect transistor device comprises a silicon substrate 3 having an N-type epitaxial layer 1 and an N-type heavily doped layer 2, wherein the N-type heavily doped layer 2 is located at the bottom of the silicon substrate 3, and the N-type epitaxial layer 1 located above the N-type heavily doped layer 2 is located in the middle and upper portions of the silicon substrate 3. A P-type well region 4 is provided on the upper portion of the N-type epitaxial layer 1, and two spaced-apart unit cells 14 are provided on the P-type well region 4, the N-type epitaxial layer 1, and the N-type heavily doped layer 2.
[0024] The unit cell 14 further includes a first trench 51, a second trench 52, and a shallow trench 6 extending from the upper surface of the P-type well region 4 to the N-type epitaxial layer 1. The shallow trench 6 is located between the first trench 51 and the second trench 52. The depths of the first trench 51 and the second trench 52 are greater than the depth of the shallow trench 6. The inner walls of the first trench 51 and the second trench 52 each have a gate silicon oxide layer 7. A first conductive polysilicon 81 and a second conductive polysilicon 82 are located in the first trench 51 and the second trench respectively. The first conductive polysilicon 81 and the second conductive polysilicon 82 are covered with a first insulating dielectric layer 111 and a second insulating dielectric layer 112 respectively; a first N-type source region 91 is provided on the upper portion of the P-type well region 4 and around the first trench 51; a second N-type source region 92 is provided on the upper portion of the P-type well region 4 and around the second trench 52; the shallow trench 6 is located between the first N-type source region 91 and the second N-type source region 92; a metal column 10 is provided in the shallow trench 6; a first insulating dielectric layer 111 and a second insulating dielectric layer 112 are respectively covered on the first conductive polysilicon 81 and the second conductive polysilicon 82;
[0025] A deep trench 15 is provided between the N-type epitaxial layers 1 of adjacent unit cells 14. The deep trench 15 extends from the surface of the N-type epitaxial layer 1 to the bottom. The bottom of the deep trench 15 is located below the bottom of each of the first trench 51 and the second trench 52. The deep trench 15 is filled with an insulating dielectric layer 16. An upper metal electrode layer 12 is located on the first insulating dielectric layer 111, the second insulating dielectric layer 112, the first N-type source region 91, the second N-type source region 92 and the metal pillar 10. The surface of the N-type heavily doped layer 2 opposite to the N-type epitaxial layer 1 has a lower metal electrode layer 13.
[0026] The depth ratio of the first trench 51 , the second trench 52 and the shallow trench 6 is 10:7.6.
[0027] One end of the metal pillar 10 contacts the first N-type source region 91 , and the other end contacts the second N-type source region 92 .
[0028] The bottom end of the deep trench 15 is located in the middle of the N-type heavily doped layer 2 .
[0029] When the above-mentioned semiconductor field-effect transistor device is used, its metal pillar is connected in parallel with the first N-type source region and the second N-type source region, and the metal pillar forms a Schottky contact with the N-type epitaxial layer, which effectively reduces the device turn-on voltage, shortens the reverse recovery time of the device, and reduces the power loss of the device under high-frequency use; in addition, its P-type well region, N-type epitaxial layer and N-type heavily doped layer have two spaced-apart unit cells, and a deep trench is provided between the N-type epitaxial layers of adjacent unit cells. This deep trench extends from the surface of the N-type epitaxial layer to the lower part, and the bottom end of the deep trench is located below the bottom ends of the first trench and the second trench respectively. This deep trench is filled with an insulating dielectric layer, which effectively avoids interference between unit cells and greatly reduces the probability of leakage current, thereby improving the overall reliability of the device.
[0030] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.
Claims
1. A semiconductor field effect transistor device, characterized in that: The invention comprises a silicon substrate (3) having an N-type epitaxial layer (1) and an N-type heavily doped layer (2), wherein the N-type heavily doped layer (2) is located at the bottom of the silicon substrate (3), and the N-type epitaxial layer (1) located above the N-type heavily doped layer (2) is located in the middle and upper parts of the silicon substrate (3); the upper part of the N-type epitaxial layer (1) has a P-type well region (4), and the P-type well region (4), the N-type epitaxial layer (1) and the N-type heavily doped layer (2) have two spaced-apart unit cells (14); The unit cell (14) further includes a first trench (51), a second trench (52) and a shallow trench (6) extending from the upper surface of the P-type well region (4) to the N-type epitaxial layer (1), wherein the shallow trench (6) is located between the first trench (51) and the second trench (52), and the depth of the first trench (51) and the second trench (52) is greater than the depth of the shallow trench (6); the first trench (51) and the second trench (52) each have a gate silicon oxide layer (7) on their inner walls, and a first conductive polysilicon (81) and a second conductive polysilicon (82) are respectively located in the first trench (51) and the second trench (52). The first conductive polysilicon (81) and the second conductive polysilicon (82) are covered with a first insulating dielectric layer (111) and a second insulating dielectric layer (112); a first N-type source region (91) is provided on the upper portion of the P-type well region (4) and located around the first trench (51); a second N-type source region (92) is provided on the upper portion of the P-type well region (4) and located around the second trench (52); the shallow trench (6) is located between the first N-type source region (91) and the second N-type source region (92); and a metal column (10) is provided in the shallow trench (6); a first insulating dielectric layer (111) and a second insulating dielectric layer (112) are respectively covered on the first conductive polysilicon (81) and the second conductive polysilicon (82); A deep trench (15) is provided between the N-type epitaxial layers (1) of adjacent cells (14), and the deep trench (15) extends from the surface of the N-type epitaxial layer (1) to the bottom, and the bottom of the deep trench (15) is located below the bottom of each of the first trench (51) and the second trench (52). The deep trench (15) is filled with an insulating dielectric layer (16); an upper metal electrode layer (12) is located on the first insulating dielectric layer (111), the second insulating dielectric layer (112), the first N-type source region (91), the second N-type source region (92) and the metal column (10), and a lower metal electrode layer (13) is provided on the surface of the N-type heavily doped layer (2) opposite to the N-type epitaxial layer (1).
2. The semiconductor field effect transistor device according to claim 1, characterized in that: The width of the shallow groove (6) is smaller than the width of the first groove (51) and the second groove (52).
3. The semiconductor field effect transistor device according to claim 1, wherein: The depth ratio of the first groove (51), the second groove (52) and the shallow groove (6) is 10:6-8.
4. The semiconductor field effect transistor device according to claim 1, wherein: One end of the metal column (10) contacts the first N-type source region (91), and the other end contacts the second N-type source region (92).
5. The semiconductor field effect transistor device according to claim 1, wherein: The lower end of the deep trench (15) is located in the middle of the N-type heavily doped layer (2).