Semiconductor test board

Abstract

The utility model relates to the technical field of semiconductor testing, in particular to a semiconductor testing board. The semiconductor test board comprises a first test base group, a second test base group, a first group of power supply connection terminals and a second group of power supply connection terminals, and each first test base in the first test base group is connected to the first group of power supply connection terminals. Each second test base in the second test base group is connected to the second group of power supply connecting terminals, and each first test base and each second test base are used for bearing a semiconductor to be tested during testing; the first test base group is used for enabling the to-be-tested semiconductor to execute a reverse bias test, and the second test base group is used for enabling the to-be-tested semiconductor to execute a gate bias test. The single test board can be used for performing various tests on the semiconductor, and the various tests are mutually independent, so that the cost of the semiconductor device is reduced, and the flexibility and the precision of the tests are enhanced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a semiconductor testing board. Background Art

[0002] Semiconductor devices are core components of modern electronic devices and are widely used in a variety of fields, including computers, communications equipment, and household appliances. Ensuring the quality and performance of these devices is crucial to the reliability and efficiency of the final product. Therefore, testing semiconductor devices is a very important step.

[0003] Semiconductor device testing can be divided into multiple stages and types. Different test boards are required for different semiconductor test types. High-quality professional test boards are expensive. For small-batch production or R&D, frequent test board replacements can lead to high costs. Utility Model Content

[0004] In view of this, the present invention provides a semiconductor test board that effectively solves the problem in the prior art of requiring different test boards for different semiconductor test types, and the high cost of high-quality professional test boards. For small-batch production or R&D stages, frequent replacement of test boards can bring high cost pressure.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor test board, comprising: a first test base group, a second test base group, a first group of power connection terminals, and a second group of power connection terminals;

[0006] Each first test socket in the first test socket group is connected to the first group of power connection terminals, which are used to connect to a first power supply; each second test socket in the second test socket group is connected to the second group of power connection terminals, which are used to connect to a second power supply; each first test socket and each second test socket is used to carry a semiconductor device to be tested during testing;

[0007] The first test pad group is used to perform a reverse bias test on each of the semiconductor devices, and the second test pad group is used to perform a gate bias test on each of the semiconductor devices.

[0008] In some embodiments, each column of first test sockets in the first test socket group is spaced apart from each column of second test sockets in the second test socket group, or each row of first test sockets in the first test socket group is spaced apart from each row of second test sockets in the second test socket group.

[0009] In some embodiments, each of the first test bases is spaced apart from each of the second test bases in a width direction and a length direction of the test board.

[0010] In some embodiments, each of the first test bases includes a source pin, a drain pin, and a gate pin, wherein the gate pin is connected to the source pin.

[0011] In some embodiments, each of the second test bases includes a source pin, a drain pin, and a gate pin, wherein the drain pin is connected to the source pin.

[0012] In some embodiments, the number of the pedestals on the semiconductor test board ranges from 40 to 200.

[0013] In some embodiments, the first group of power connection terminals includes a first power input terminal and a first power output terminal. When performing the reverse bias test, the first power input terminal is used for grounding, and the first power output terminal is used for connecting to the first power supply.

[0014] In some embodiments, the second group of power connection terminals includes a second power input terminal and a second power output terminal. When performing a forward gate bias test, the second power input terminal is used to connect the second power supply, and the second power output terminal is used to be grounded.

[0015] In some embodiments, the second group of power connection terminals includes a second power input terminal and a second power output terminal. When performing a reverse gate bias test, the second power input terminal is used for grounding, and the second power output terminal is used for connecting the second power supply.

[0016] In some embodiments, the semiconductor test board also includes several fuses, and the input end of each first test base is electrically connected to the first power input terminal through each fuse, and the input end of each second test base is electrically connected to the second power input terminal through each fuse.

[0017] The embodiments of the present application have the following beneficial effects:

[0018] The semiconductor test board of the present application includes a first test base group, a second test base group, a first group of power connection terminals and a second group of power connection terminals, wherein each first test base in the first test base group is connected to the first group of power connection terminals, and each second test base in the second test base group is connected to the second group of power connection terminals. The first group of power connection terminals is used to connect to the first power supply, and the second group of power connection terminals is used to connect to the second power supply. Each first test base and each second test base is used to carry the semiconductor to be tested during testing. The first test base group is used to make the semiconductor to be tested perform a reverse bias test, and the second test base group is used to make the semiconductor to be tested perform a gate bias test. The present application can perform multiple tests on the semiconductor using a single test board. The multiple tests are independent of each other, which reduces the cost of semiconductor devices while enhancing the flexibility and accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A first structural schematic diagram of a semiconductor test board according to an embodiment of the present application is shown;

[0021] Figure 2 A second structural schematic diagram of a semiconductor test board according to an embodiment of the present application is shown;

[0022] Figure 3 A schematic diagram showing the structure of the first group of power connection terminals and the second group of power connection terminals in an embodiment of the present application is shown;

[0023] Figure 4 A circuit diagram of a semiconductor test board according to an embodiment of the present application is shown.

[0024] Description of main component symbols:

[0025] 10: First test base group; 20: Second test base group; 30: First group of power connection terminals; 40: Second group of power connection terminals; 301: First power input terminal; 302: First power output terminal; 401: Second power input terminal; 402: Second power output terminal. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0028] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0030] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.

[0031] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0032] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0034] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0035] Considering the different types of semiconductor tests in existing solutions, different test boards need to be set up, and high-quality professional test boards are expensive. For small-batch production or the R&D stage, frequent replacement of test boards will bring about high cost pressure. The present application provides a semiconductor test board. The semiconductor test board of the present application can perform multiple tests on semiconductors using a single test board. The multiple tests are independent of each other, which reduces the cost of semiconductor devices while enhancing the flexibility and accuracy of the tests.

[0036] The semiconductor test board will be described below with reference to some specific embodiments.

[0037] Figure 1A schematic diagram of the structure of a semiconductor test board according to an embodiment of the present application is shown. Exemplarily, the board includes: a first test pedestal group 10, a second test pedestal group 20, a first set of power connection terminals 30, and a second set of power connection terminals 40. It is understood that the first test pedestal group 10 in this embodiment may include any number of first test pedestals, and the second test pedestal group 20 may include any number of second test pedestals.

[0038] Semiconductor devices are electronic components made of semiconductor materials and play a vital role in modern electronic technology. Semiconductor devices can be MOS tubes, IGBTs, BJTs, thyristors, etc.

[0039] Specifically, the first test base assembly 10 is used to perform a reverse bias test on each semiconductor device, and the second test base assembly 20 is used to perform a gate bias test on each semiconductor device. It is understood that, depending on actual application conditions, the semiconductor to be tested can be tested using a test board. The semiconductor test board can be used alone to perform a reverse bias test on the semiconductor; a constant temperature and humidity test chamber can be used to perform a high-temperature reverse bias test on the semiconductor; a constant temperature and humidity test chamber can be used to perform a high-temperature and high-humidity reverse bias test on the semiconductor; the semiconductor test board can be used to perform a forward gate bias test on the semiconductor; the semiconductor test board can be used to perform a reverse gate bias test on the semiconductor; the constant temperature and humidity test chamber can be used to perform a high-temperature gate bias test on the semiconductor; further, the test board can be used to perform both a reverse bias test and a gate bias test on the semiconductor. This can reduce the preparation time and downtime caused by replacing different test boards, speed up the testing process, reduce the R&D cost and logistics cost of semiconductor devices by reducing the number of test boards, and use a single test board to perform multiple tests on the semiconductor, increasing testing flexibility, ensuring that tests are performed under the same environment, and improving the consistency of test results.

[0040] It is understood that the first set of power connection terminals 30 includes power input terminals and power output terminals, and can be used to connect to an external power source according to actual application conditions. The second set of power terminals includes power input terminals and power output terminals, and can be used to connect to an external power source according to actual application conditions via the second set of power connection terminals 40. Each first test pedestal in the first test pedestal group 10 is connected to the first set of power connection terminals 30, and the input terminal of each first test pedestal in the first test pedestal group 10 is connected to the power input terminal of the first set of power connection terminals 30, and the output terminal of each first test pedestal in the first test pedestal group 10 is connected to the power output terminal of the first set of power connection terminals 30. Each second test pedestal in the second test pedestal group 20 is connected to the second set of power connection terminals 40, and the input terminal of each second test pedestal in the second test pedestal group 20 is connected to the power input terminal of the second set of power connection terminals 40, and the output terminal of each second test pedestal in the second test pedestal group 20 is connected to the power output terminal of the second set of power connection terminals 40.

[0041] Each first test base and each second test base are used to carry the semiconductor device to be tested during testing; it can be understood that the first test base and the second test base can be surface mount pins, and the first test base and the second test base can be pin pins. Furthermore, component holders can be set on the first test base and the second test base to facilitate the installation and removal of semiconductor devices.

[0042] The number of first and second measurement bases on a semiconductor test board can be set based on actual application requirements. Exemplarily, the number of bases on a semiconductor test board ranges from 40 to 200. The number of first and second measurement bases can be the same, or the number of second and second measurement bases can be different. Exemplarily, if the number of first and second measurement bases is the same, a test board can have 40 first and 40 second measurement bases, or 80 first and 80 second measurement bases. Multiple test bases on a semiconductor test board enable simultaneous testing of multiple semiconductors, shortening test time and significantly improving production efficiency. It also ensures consistency in test conditions, enhancing the comparability and reliability of test results.

[0043] The test bases in the test board can be arranged according to actual application conditions. The first test base and the second test base can be set separately, or the first test base and the second test base can be set crosswise. For example, Figure 1As shown, the first test bases in each column of the first test base group 10 and the second test bases in each column of the second test base group 20 are arranged at intervals, wherein the reverse bias test performed using the first test base dissipates higher heat, and the gate bias test performed using the second test base dissipates lower heat. The two types of test bases in the test board are cross-arranged in columns, which can ensure the number of test bases on the test board while allowing the first test base to fully dissipate heat during testing.

[0044] The semiconductor test board of the present embodiment is provided with a first test pedestal group 10 for performing reverse bias testing on semiconductor devices, and a second test pedestal group 20 for performing gate bias testing on semiconductor devices. This allows users to perform both reverse bias and gate bias testing simultaneously, improving test parallelism and efficiency and adapting to different types of semiconductor devices and testing requirements. Furthermore, the two test pedestals in the test board of this embodiment are arranged in rows, interleaved with each other, to reduce mutual interference between tests and improve the accuracy and reliability of test results.

[0045] In one embodiment, based on the above embodiment, Figure 2 Another structural schematic diagram of the semiconductor test board of an embodiment of the present application is shown, in which the first test bases in each row of the first test base group 10 and the second test bases in each row of the second test base group 20 are arranged at intervals. It can be understood that the test bases in each row can be arranged correspondingly to the test bases in other rows, and the test bases in each row can also be staggered with the test bases in other rows. In this embodiment, the test bases in each row are arranged correspondingly to the test bases in other rows to form a base matrix.

[0046] The semiconductor test board of the embodiment of the present application can arrange more test bases in a limited space by cross-arranging the two test bases in the test board in rows, thereby improving the space utilization of the test board. At the same time, test data can be collected and analyzed centrally, which is convenient for statistics and quality control.

[0047] In one embodiment, based on the above embodiment, Figure 3 A schematic structural diagram of the first group of power connection terminals and the second group of power connection terminals in an embodiment of the present application, in which each first test base is spaced apart from each second test base in the width direction and the length direction of the test board. It can be understood that the test board in this embodiment has several rows of test boards in the width direction and several columns of test boards in the length direction, that is, the first test base and the second test base in each row of the test board are spaced apart, and the first test base and the second test base in each column of the test board are spaced apart.

[0048] The semiconductor test board of the embodiment of the present application arranges the first test base and the second test base in each row of the test board at intervals, and arranges the first test base and the second test base in each column of the test board at intervals, which makes it easier to dissipate heat for the first test base during testing and ensures the space utilization of the test board.

[0049] As an optional solution, Figure 4 A circuit diagram of a semiconductor test board according to an embodiment of the present application is shown.

[0050] In one embodiment, if Figure 4 As shown, on the basis of the above embodiments, each first test base includes a source pin S, a drain pin D and a gate pin G, wherein the gate pin G is connected to the source pin S. Specifically, the reverse bias test of the semiconductor device requires the gate pin G of the semiconductor device to be short-circuited with the source pin S of the semiconductor device. In this embodiment, the gate pin G and the source pin S on each first test base are short-circuited. When the semiconductor device needs to be tested, the various pins of the semiconductor can be connected to the corresponding pins on the test board.

[0051] Furthermore, the first group of power connection terminals 30 includes a first power input terminal 301 and a first power output terminal 302. The source pin S of each first test base is electrically connected to the first power input terminal 301 as the input terminal of the first test base, and the drain pin D of each first test base is electrically connected to the first power output terminal 302 as the output terminal of the first test base. When a reverse bias test is performed using a semiconductor test board, the first power input terminal 301 is used for grounding, and the first power output terminal 302 is used to connect to the first power supply. The size of the first power supply can be set according to actual application conditions. Exemplarily, the first power supply is 30V.

[0052] The semiconductor test board of the embodiment of the present application short-circuits the gate pin G and the source pin S of each first test base. When the user needs to perform a reverse bias test on the semiconductor device, the first power input terminal 301 can be grounded, the first power output terminal 302 can be connected to the first power supply, and the semiconductor device can be placed on the base of the test board. There is no need for complicated welding or connection processes, which simplifies the operation steps and eliminates the need to use connecting wires to connect the semiconductor device, reducing the material cost of the test.

[0053] In one embodiment, if Figure 4As shown, on the basis of the above embodiments, each second test base includes a source pin S, a drain pin D and a gate pin G, wherein the drain pin D is connected to the source pin S. Specifically, the gate bias test of the semiconductor device requires short-circuiting the drain pin D of the semiconductor device and the source pin S of the semiconductor device. In this embodiment, the drain pin D and the source pin S on each second test base are short-circuited. When the semiconductor device needs to be tested, the various pins of the semiconductor are connected to the various pins of the test board accordingly.

[0054] Furthermore, the second group of power connection terminals 40 includes a second power input terminal 401 and a second power output terminal 402. The source pin S of each second test base is electrically connected to the second power input terminal 401 as the input terminal of the second test base, and the gate pin G of each second test base is electrically connected to the second power output terminal 402 as the output terminal of the second test base. The connection between the second power input terminal 401 and the second power output terminal 402 can be set according to actual application conditions. Specifically, when a forward gate bias test is performed using a semiconductor test board, the second power input terminal 401 is used to connect the second power supply, and the second power output terminal 402 is used for grounding; when a reverse gate bias test is performed using a semiconductor test board, the second power input terminal 401 is used for grounding, and the second power output terminal 402 is used to connect the second power supply. The size of the second power supply can be set according to actual application conditions. For example, the second power supply is 520V.

[0055] The semiconductor test board of the embodiment of the present application short-circuits the drain pin D and the source pin S of each second test base. When the user needs to perform a gate bias test on the semiconductor device, the second group of power connection terminals 40 are connected to the second power supply, and the semiconductor device is placed on the base of the test board. There is no need for complicated welding or connection processes, which simplifies the operation steps and eliminates the need to use connecting wires to connect the semiconductor device, reducing the material cost of the test.

[0056] In one embodiment, if Figure 4 As shown, based on the above embodiment, the semiconductor test board also includes a plurality of fuses F1, and the input end of each first test base is electrically connected to the first power input terminal 301 through each fuse F1, and the input end of each second test base is electrically connected to the second power input terminal 401 through each fuse F1.

[0057] The semiconductor test board of the embodiment of the present application is provided with a fuse between the power supply and the input end of the test base. When the current exceeds its rated value, the fuse will melt and cut off the circuit, thereby preventing excessive current from passing through the test base and the device under test, avoiding equipment damage caused by overcurrent. The fuse can also prevent excessive current from flowing back to the power supply, protecting the power supply equipment, and greatly improving the reliability of the test board.

[0058] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0059] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0060] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0061] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A semiconductor test board, characterized in that: include: a first test base group, a second test base group, a first group of power connection terminals, and a second group of power connection terminals, Each first test socket in the first test socket group is connected to the first group of power connection terminals, which are used to connect to a first power supply; each second test socket in the second test socket group is connected to the second group of power connection terminals, which are used to connect to a second power supply; each first test socket and each second test socket is used to carry a semiconductor device to be tested during testing; The first test base group is used to perform a reverse bias test on each of the semiconductor devices, and the second test base group is used to perform a gate bias test on each of the semiconductor devices.

2. The semiconductor test board according to claim 1, wherein Each column of first test sockets in the first test socket group is spaced apart from each column of second test sockets in the second test socket group; or each row of first test sockets in the first test socket group is spaced apart from each row of second test sockets in the second test socket group.

3. The semiconductor test board according to claim 1, wherein: In the width direction of the test board and the length direction of the test board, each of the first test seats is spaced apart from each of the second test seats.

4. The semiconductor test board according to claim 1, characterized in that The first test bases each include a source pin, a drain pin, and a gate pin, wherein the gate pin is connected to the source pin.

5. The semiconductor test board according to claim 1, wherein Each of the second test bases includes a source pin, a drain pin, and a gate pin, wherein the drain pin is connected to the source pin.

6. The semiconductor test board according to claim 1, wherein: The number of bases on the semiconductor test board ranges from 40 to 200.

7. The semiconductor test board according to claim 1, wherein: The first group of power connection terminals includes a first power input terminal and a first power output terminal. When performing the reverse bias test, the first power input terminal is used for grounding, and the first power output terminal is used for connecting to the first power supply.

8. The semiconductor test board according to claim 7, wherein: The second group of power connection terminals includes a second power input terminal and a second power output terminal. When performing a forward gate bias test, the second power input terminal is used to connect the second power supply, and the second power output terminal is used to be grounded.

9. The semiconductor test board according to claim 1, wherein: The second group of power connection terminals includes a second power input terminal and a second power output terminal. When performing a reverse gate bias test, the second power input terminal is used for grounding, and the second power output terminal is used for connecting the second power supply.

10. The semiconductor test board according to claim 8, wherein The semiconductor test board also includes a plurality of fuses, and the input end of each first test base is electrically connected to the first power input terminal through each fuse, and the input end of each second test base is electrically connected to the second power input terminal through each fuse.

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