Display device

Abstract

The display device includes a pixel including: a first sub-pixel including a first pulse width modulator outputting a first gate output signal for pulse width modulation in response to a first pulse width data voltage and controlling a first driving current of a first light emitting element, and a first pulse amplitude modulator outputting a second gate output signal for pulse width modulation in response to a second pulse width data voltage; a first pulse amplitude modulator applies a first driving current to a first light emitting element in response to a first pulse amplitude data voltage; and a second sub-pixel including a second pulse width modulator and a second pulse amplitude modulator, the second pulse width modulator outputting a second gate output signal for pulse width modulation in response to a second pulse width data voltage and controlling a second driving current of a second light emitting element, a second pulse amplitude modulator applies a second driving current to a second light emitting element in response to a second pulse amplitude data voltage; and an initializer that initializes the first gate output signal and the second gate output signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device, and more particularly, to a display device used in various electronic devices. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, an emission driver that provides emission signals to the emission lines, and a drive controller that controls the gate driver, the data driver, and the emission driver. In addition, the pixels may include sub-pixels.

[0003] Each of the sub-pixels may include multiple transistors and multiple capacitors. When each of the sub-pixels includes multiple transistors and multiple capacitors, the pixel may not be applied to an ultra-high-resolution display device due to limitations in integration. Utility Model Content

[0004] Embodiments of the present disclosure may provide a display device for improving integration and being applicable to an ultra-high-resolution display device by reducing the number of transistors and capacitors included in a pixel by sharing some functional circuits of sub-pixels.

[0005] In an embodiment of a display device according to the present disclosure, the display device includes a display panel, a data driver, an emission driver, a gate driver, and a drive controller. The display panel includes pixels. The data driver provides data voltages to the pixels. The emission driver provides emission signals to the pixels. The gate driver provides gate signals to the pixels. The drive controller controls the data driver, the emission driver, and the gate driver. The pixel includes: a first subpixel, including a first pulse width modulator and a first pulse amplitude modulator, the first pulse width modulator being configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and being configured to control a period of a first drive current applied to a first light-emitting element, the first pulse amplitude modulator being configured to apply the first drive current to the first light-emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage; a second subpixel, including a second pulse width modulator and a second pulse amplitude modulator, the second pulse width modulator being configured to output a second gate output signal for pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second drive current applied to a second light-emitting element, the second pulse amplitude modulator being configured to apply the second drive current to the second light-emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage; and an initializer being configured to initialize the first gate output signal and the second gate output signal in response to a second initialization signal.

[0006] In an embodiment of the present disclosure, the initializer may include a third transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to the second node, and a second electrode configured to receive the initialization voltage.

[0007] In an embodiment of the present disclosure, the pixel may further include a voltage drop compensator configured to compensate for a voltage drop of the first pulse amplitude modulator and a voltage drop of the second pulse amplitude modulator.

[0008] In an embodiment of the present disclosure, a voltage drop compensator may include: a first transistor, including a control electrode configured to receive a second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and a second transistor, including a control electrode configured to receive a first transmission signal, a first electrode connected to the first node, and a second electrode configured to receive a second power voltage.

[0009] In an embodiment of the present disclosure, the pixel may further include a light emitting element initializer configured to initialize the first light emitting element and the second light emitting element in response to a second initialization signal.

[0010] In an embodiment of the present disclosure, the light-emitting element initializer may include: a fourth transistor, including a control electrode configured to receive a second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and a first capacitor, including a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

[0011] In an embodiment of the present disclosure, the pixel may further include: a voltage drop compensator configured to compensate for the voltage drop of the first pulse amplitude modulator and the voltage drop of the second pulse amplitude modulator; and a light-emitting element initializer configured to initialize the first light-emitting element and the second light-emitting element in response to a second initialization signal.

[0012] In an embodiment of the present disclosure, a voltage drop compensator may include: a first transistor including a control electrode configured to receive a second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and a second transistor including a control electrode configured to receive a first emission signal, a first electrode connected to the first node, and a second electrode configured to receive the second power voltage. A light-emitting element initializer may include: a fourth transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and a first capacitor including a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

[0013] In an embodiment of the present disclosure, the pixel may further include a third subpixel, the third subpixel including a third pulse width modulator and a third pulse amplitude modulator, the third pulse width modulator being configured to output a third gate output signal for pulse width modulation in response to a third pulse width data voltage different from the first pulse width data voltage and the second pulse width data voltage and being configured to control a period of a third drive current applied to a third light-emitting element, the third pulse amplitude modulator being configured to apply the third drive current to the third light-emitting element in response to the third pulse amplitude data voltage different from the third pulse width data voltage. The initializer may further initialize the third gate output signal in response to the second initialization signal.

[0014] In an embodiment of the present disclosure, the pixel may further include a voltage drop compensator configured to compensate for the voltage drop of the first pulse amplitude modulator, the voltage drop of the second pulse amplitude modulator, and the voltage drop of the third pulse amplitude modulator.

[0015] In an embodiment of the present disclosure, the pixel may further include a light emitting element initializer configured to initialize the first light emitting element, the second light emitting element, and the third light emitting element in response to a second initialization signal.

[0016] In an embodiment of the present disclosure, the pixel may further include: a voltage drop compensator configured to compensate for the voltage drop of the first pulse amplitude modulator, the voltage drop of the second pulse amplitude modulator, and the voltage drop of the third pulse amplitude modulator; and a light-emitting element initializer configured to initialize the first light-emitting element, the second light-emitting element, and the third light-emitting element in response to a second initialization signal.

[0017] In an embodiment of the present disclosure, a voltage drop compensator may include: a first transistor including a control electrode configured to receive a second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and a second transistor including a control electrode configured to receive a first emission signal, a first electrode connected to the first node, and a second electrode configured to receive the second power voltage. A light-emitting element initializer may include: a fourth transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and a first capacitor including a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

[0018] In an embodiment of a display device according to the present disclosure, the display device includes a display panel, a data driver, an emission driver, a gate driver, and a drive controller. The display panel includes pixels. The data driver provides a data voltage to the pixel. The emission driver provides an emission signal to the pixel. The gate driver provides a gate signal to the pixel. The drive controller controls the data driver, the emission driver, and the gate driver. The pixel includes: a first sub-pixel, including a first pulse width modulator, a first pulse amplitude modulator, and a first initializer, the first pulse width modulator being configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and being configured to control a period of a first drive current applied to a first light-emitting element, the first pulse amplitude modulator being configured to apply the first drive current to the first light-emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage, the first initializer being configured to initialize the first gate output signal in response to a second initialization signal; a second sub-pixel, including a second pulse width modulator, a second pulse amplitude modulator a second initializer, the second pulse width modulator being configured to output a second gate output signal for pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second driving current applied to the second light-emitting element, the second pulse amplitude modulator being configured to apply a second driving current to the second light-emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage, the second initializer being configured to initialize the second gate output signal in response to a second initialization signal; and a voltage drop compensator being configured to compensate for a voltage drop of the first pulse amplitude modulator and a voltage drop of the second pulse amplitude modulator.

[0019] In an embodiment of a display device according to the present disclosure, the display device includes a display panel, a data driver, an emission driver, a gate driver, and a drive controller. The display panel includes pixels. The data driver provides a data voltage to the pixel. The emission driver provides an emission signal to the pixel. The gate driver provides a gate signal to the pixel. The drive controller controls the data driver, the emission driver, and the gate driver. The pixel includes: a first sub-pixel, including a first pulse width modulator, a first pulse amplitude modulator, and a first initializer, the first pulse width modulator being configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and being configured to control a period of a first drive current applied to a first light-emitting element, the first pulse amplitude modulator being configured to apply the first drive current to the first light-emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage, the first initializer being configured to initialize the first gate output signal in response to a second initialization signal; a second sub-pixel, including a second pulse width modulator, a second pulse amplitude modulator a second initializer, the second pulse width modulator being configured to output a second gate output signal for pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second driving current applied to the second light-emitting element, the second pulse amplitude modulator being configured to apply a second driving current to the second light-emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage, the second initializer being configured to initialize the second gate output signal in response to a second initialization signal; and a light-emitting element initializer being configured to initialize the first light-emitting element and the second light-emitting element in response to the second initialization signal.

[0020] According to the above display device, a pixel included in the display device can include sub-pixels, and the sub-pixels can share some functional circuits. Accordingly, the number of transistors and capacitors included in the pixel can be reduced compared to conventional pixels. Accordingly, the integration density of the pixel can be improved, and the pixel production can be increased. In addition, the pixel can be suitable for ultra-high-resolution display devices.

[0021] In addition, since the integration of pixels is improved, it is possible to manufacture products including display panels suitable for ultra-high resolution and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features and advantages of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0023] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0024] Figure 2 It is an icon Figure 1 A block diagram of a display panel;

[0025] Figure 3 The diagram is included in Figure 2 a circuit diagram of an example of a pixel in a display panel;

[0026] Figure 4A is a circuit diagram illustrating a first sub-pixel connected to an initializer, a voltage drop compensator, and a light emitting element initializer;

[0027] Figure 4B is a circuit diagram illustrating a second sub-pixel connected to an initializer, a voltage drop compensator, and a light emitting element initializer;

[0028] Figure 4C is a circuit diagram illustrating a third sub-pixel connected to an initializer, a voltage drop compensator, and a light emitting element initializer;

[0029] Figure 5A is a circuit diagram of a first sub-pixel connected to a voltage drop compensator and a light emitting element initializer in the illustrated embodiment;

[0030] Figure 5B is a circuit diagram of a second sub-pixel connected to a voltage drop compensator and a light emitting element initializer in the illustrated embodiment;

[0031] Figure 5C is a circuit diagram of a third sub-pixel connected to a voltage drop compensator and a light emitting element initializer in the illustrated embodiment;

[0032] Figure 6 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and

[0033] Figure 7 The diagram shows Figure 6 FIG. 4 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0034] Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is an icon Figure 1 1 is a block diagram of a display panel 100.

[0036] refer to Figure 1 and Figure 2 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0037] The display panel 100 includes a display area configured to display an image and a peripheral area adjacent to the display area.

[0038] The display panel 100 includes a plurality of gate lines GWL, GIL, and GI2L, a plurality of data lines WDL and ADL, a plurality of emission lines WEML and AEML, and a plurality of pixels PX electrically connected to the gate lines GWL, GIL, and GI2L, the data lines WDL and ADL, and the emission lines WEML and AEML, respectively. The gate lines GWL, GIL, and GI2L may extend in a first direction D1, the data lines WDL and ADL may extend in a second direction D2 intersecting the first direction D1, and the emission lines WEML and AEML may extend in the first direction D1.

[0039] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0040] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0041] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the generated first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0042] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the generated second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0043] The driving controller 200 generates a data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500 .

[0044] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the generated third control signal CONT3 to the gamma reference voltage generator 400 .

[0045] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the generated fourth control signal CONT4 to the emission driver 600 .

[0046] The gate driver 300 generates gate signals GW, GI, and GI2 for driving the gate lines GWL, GIL, and GI2L in response to the first control signal CONT1 received from the drive controller 200. The gate driver 300 may output the gate signals GW, GI, and GI2 to the gate lines GWL, GIL, and GI2L. The gate signals GW, GI, and GI2 may include a write signal GW, an initialization signal GI, and a second initialization signal GI2.

[0047] In an embodiment of the present disclosure, the gate driver 300 may be integrated on a peripheral area of ​​the display panel 100. In an embodiment of the present disclosure, the gate driver 300 may be mounted on a peripheral area of ​​the display panel 100.

[0048] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to each of the data signals DATA.

[0049] For example, the gamma reference voltage generator 400 may be provided in the driving controller 200 or the data driver 500 .

[0050] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type by using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data lines WDL and ADL. The data voltage may include a pulse width data voltage WDATA and a pulse amplitude data voltage ADATA. In this embodiment, the pulse width data voltage WDATA may include a first pulse width data voltage WDATA1 (see Figure 4A ), the second pulse width data voltage WDATA2 (see Figure 4B ) and the third pulse width data voltage WDATA3 (see Figure 4C In this embodiment, the pulse amplitude data voltage ADATA may include a first pulse amplitude data voltage ADATA1 (see Figure 4A ), the second pulse amplitude data voltage ADATA2 (see Figure 4B ) and the third pulse amplitude data voltage ADATA3 (see Figure 4C ).

[0051] In an embodiment of the present disclosure, the data driver 500 may be integrated on a peripheral area of ​​the display panel 100. In an embodiment of the present disclosure, the data driver 500 may be mounted on a peripheral area of ​​the display panel 100.

[0052] The emission driver 600 generates emission signals WEM and AEM for driving the emission lines WEML and AEML in response to the fourth control signal CONT4 received from the drive controller 200. The emission driver 600 can output the emission signals WEM and AEM to the emission lines WEML and AEML. In this embodiment, the emission signals WEM and AEM can include a first emission signal WEM and a second emission signal AEM.

[0053] In an embodiment of the present disclosure, the emission driver 600 may be integrated on a peripheral area of ​​the display panel 100. In an embodiment of the present disclosure, the emission driver 600 may be mounted on a peripheral area of ​​the display panel 100.

[0054] Although for ease of explanation, Figure 1 In the embodiment, the gate driver 300 is disposed on a first side of the display panel 100 and the emission driver 600 is disposed on a second side of the display panel 100, but the present disclosure is not limited thereto. The gate driver 300 and the emission driver 600 may be disposed on the first side of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be disposed on a peripheral area of ​​the display panel 100 on the same side of the display area of ​​the display panel 100. For example, the gate driver 300 and the emission driver 600 may be formed integrally with each other.

[0055] refer to Figure 1 and Figure 2 In an embodiment, the display panel 100 may include a pixel PX. The pixel PX may receive gate signals GW, GI, and GI2 from the gate driver 300, may receive emission signals WEM and AEM from the emission driver 600, and may receive a pulse width data voltage WDATA and a pulse amplitude data voltage ADATA from the data driver 500.

[0056] In this embodiment, the pixel PX may include a sub-pixel SUB-PX. The sub-pixel SUB-PX may emit light according to the color of the light-emitting element. In an embodiment, the light-emitting element may be an organic light-emitting diode (OLED). However, the present disclosure is not limited thereto. Alternatively, Figure 3 The light emitting element EE may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode and an inorganic light emitting diode or any other suitable light emitting element. For example, the color may be red, green or blue. However, the present disclosure is not limited thereto. For example, the number of sub-pixels SUB-PX included in the pixel PX may be three. However, the present disclosure is not limited to this number of sub-pixels SUB-PX. In the present embodiment, the sub-pixel SUB-PX may mean one of the first sub-pixel, the second sub-pixel and the third sub-pixel. In addition, in an embodiment, the first light emitting element of the first sub-pixel (for example, Figure 4A The color of the first light-emitting element EEA of the second sub-pixel (for example, Figure 4B The color of the second light-emitting element EEB) of the third sub-pixel and the third light-emitting element of the third sub-pixel (for example, Figure 4C The color of the third light emitting element EEC) may be different. However, the present disclosure is not limited to Figure 4A The color of the first light-emitting element EEA, Figure 4B The color of the second light emitting element EEB and Figure 4C The color of the third light emitting element EEC. For example, Figure 4A The color of the first light-emitting element EEA, Figure 4B The color of the second light emitting element EEB and Figure 4C The colors of the third light emitting elements EEC may be the same.

[0057] In an embodiment, the pulse width data voltage WDATA and the pulse amplitude data voltage ADATA applied to the first subpixel, the second subpixel, and the third subpixel may be different.

[0058] Figure 3 The diagram is included in Figure 2 FIG. 1 is a circuit diagram of an example of a pixel PX in the display panel 100 .

[0059] refer to Figure 3 The pixel PX may include a sub-pixel SUB-PX, an initializer 730, a voltage drop compensator 740, a light emitting element initializer 750 and a sensing transistor T19, and the sub-pixel SUB-PX includes a pulse width modulator 710, a pulse amplitude modulator 720 and a light emitting element EE.

[0060] In this embodiment, the pulse width modulator 710 may include: a fifth transistor T5, including a control electrode receiving the first emission signal WEM, a first electrode receiving the first power voltage VDDW, and a second electrode connected to the fourth node N4; a sixteenth transistor T16, including a control electrode receiving the write signal GW[n], a first electrode receiving the pulse width data voltage WDATA, and a second electrode connected to the fourth node N4; a seventh transistor T7, including a control electrode connected to the sixth node N6, a first electrode connected to the fourth node N4, and a second electrode connected to the fifth node N5; a sixth transistor T6, including a control electrode receiving the first emission signal WEM, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4. a first electrode connected to the sixth node N6, and a second electrode connected to the fifth node N5; a seventeenth transistor T17 including a control electrode receiving the write signal GW[n], a first electrode connected to the sixth node N6, and a second electrode connected to the fifth node N5; an eighteenth transistor T18 including a control electrode receiving the initialization signal GI[n], a first electrode connected to the sixth node N6, and a second electrode receiving the initialization voltage VINT; an eighth transistor T8 including a control electrode receiving the second initialization signal GI2[n], a first electrode receiving the scan signal SWEEP[n], and a second electrode receiving the high voltage VGH; and a fourth capacitor C4 including a first electrode receiving the scan signal SWEEP[n] and a second electrode connected to the sixth node N6. For example, the high voltage VGH may be substantially the same as the first power voltage VDDW or the second power voltage VDDA.

[0061] The pulse width modulator 710 controls the voltage of the second node N2 by generating a gate output signal GO[n] in response to the pulse width data voltage WDATA. The pulse amplitude modulator 720 can operate in response to the gate output signal GO[n]. The pulse width of the drive current flowing through the light-emitting element EE can be controlled by the gate output signal GO[n] of the pulse width modulator 710, so that the pulse width modulator 710 can perform pulse width modulation of the drive current of the light-emitting element EE. For example, the pulse width modulator 710 can control the period of the drive current applied to the light-emitting element EE.

[0062] In this embodiment, the voltage drop compensator 740 may include: a first transistor T1, including a control electrode receiving the second initialization signal GI2[n], a first electrode receiving the first power voltage VDDW, and a second electrode connected to the first node N1; and a second transistor T2, including a control electrode receiving the first emission signal WEM, a first electrode connected to the first node N1, and a second electrode receiving the second power voltage VDDA.

[0063] The voltage drop compensator 740 may minimize the influence of the voltage drop of the second power voltage VDDA when the threshold voltage of the pulse amplitude modulator 720 is compensated.

[0064] In this embodiment, the pulse amplitude modulator 720 may include: a thirteenth transistor T13, including a control electrode receiving the first transmission signal WEM, a first electrode receiving the second power voltage VDDA, and a second electrode connected to the seventh node N7; a tenth transistor T10, including a control electrode receiving the write signal GW[n], a first electrode receiving the pulse amplitude data voltage ADATA, and a second electrode connected to the seventh node N7; a ninth transistor T9, including a control electrode connected to the eighth node N8, a first electrode connected to the seventh node N7, and a second electrode connected to the ninth node N9; an eleventh transistor T11, including a control electrode receiving the write signal GW[n], a first electrode connected to the eighth node N8, and a second electrode connected to the ninth node N9. a first electrode connected to the ninth node N9 and a second electrode connected to the thirteenth node N13; a twelfth transistor T12, including a control electrode receiving the initialization signal GI[n], a first electrode connected to the eighth node N8 and a second electrode receiving the initialization voltage VINT; a fourteenth transistor T14, including a control electrode receiving the second emission signal AEM, a first electrode connected to the thirteenth node N13 and a second electrode connected to the third node N3; a fifteenth transistor T15, including a control electrode connected to the second node N2, a first electrode connected to the ninth node N9 and a second electrode connected to the thirteenth node N13; and a second capacitor C2, including a first electrode connected to the first node N1 and a second electrode connected to the eighth node N8.

[0065] The pulse amplitude modulator 720 generates a driving current applied to the light emitting element EE in response to the pulse amplitude data voltage ADATA. The pulse amplitude modulator 720 may perform pulse amplitude modulation. The pulse amplitude modulator 720 may be a constant current generator that generates a constant driving current according to the pulse amplitude data voltage ADATA.

[0066] In this embodiment, the initializer 730 may include: a third transistor T3, including a control electrode receiving the second initialization signal GI2[n], a first electrode connected to the second node N2, and a second electrode receiving the initialization voltage VINT; and a third capacitor C3, including a first electrode connected to the second node N2 and a second electrode receiving the initialization voltage VINT.

[0067] The initializer 730 may initialize the voltage of the second node N2 to the initialization voltage VINT in response to the second initialization signal GI2[n]. For example, the voltage of the second node N2 is initialized to the initialization voltage VINT so that the gate output signal GO[n] may have the initialization voltage VINT.

[0068] In this embodiment, the light-emitting element initializer 750 may include: a fourth transistor T4, including a control electrode receiving a second initialization signal GI2[n], a first electrode connected to a third node N3, and a second electrode receiving a third power voltage VSSL; and a first capacitor C1, including a first electrode connected to the third node N3 and a second electrode receiving the third power voltage VSSL.

[0069] The light emitting element initializer 750 may initialize the voltage of the third node N3 to the third power voltage VSSL in response to the second initialization signal GI2[n].

[0070] The sensing transistor T19 may include a control electrode receiving the test signal TEST, a first electrode receiving the pulse width data voltage WDATA, and a second electrode connected to the third node N3.

[0071] The light emitting element EE may include a first electrode (eg, an anode) connected to the third node N3 and a second electrode (eg, a cathode) receiving the third power voltage VSSL.

[0072] Figure 4A is a circuit diagram illustrating a first subpixel SUB-PX1A connected to an initializer 730 , a voltage drop compensator 740 , and a light emitting element initializer 750 . Figure 4B The diagram is connected to Figure 4A 1B is a circuit diagram of a second subpixel SUB-PX1B including an initializer 730, a voltage drop compensator 740, and a light emitting element initializer 750.

[0073] Figure 4C The diagram is connected to Figure 4A 1 and 10. A circuit diagram of a third subpixel SUB-PX1C of the first subpixel SUB-PX1C including an initializer 730, a voltage drop compensator 740, and a light emitting element initializer 750.

[0074] refer to Figure 4A and Figure 4B In an embodiment, the display panel 100 may include a first gate output signal line GOL1 and a second gate output signal line GOL2.

[0075] In this embodiment, the first sub-pixel SUB-PX1A may include a first pulse width modulator 710A, a first pulse amplitude modulator 720A, a first sensing transistor T19A, and a first light emitting element EEA.

[0076] In addition to the first pulse width data voltage WDATA1 being applied to the first pulse width modulator 710A, the first pulse width modulator 710A may be connected to the first pulse width modulator 710A. Figure 3 The pulse width modulator 710 is substantially the same.

[0077] For example, the first pulse width modulator 710A may include a fifth transistor T5A, a sixth transistor T6A, a seventh transistor T7A, an eighth transistor T8A, a sixteenth transistor T16A, a seventeenth transistor T17A, an eighteenth transistor T18A, and a fourth capacitor C4A.

[0078] In addition to the first pulse amplitude data voltage ADATA1 being applied to the first pulse amplitude modulator 720A, the first pulse amplitude modulator 720A may be connected to the first pulse amplitude modulator 720A. Figure 3 The pulse amplitude modulator 720 is essentially the same.

[0079] For example, the first pulse amplitude modulator 720A may include ninth to fifteenth transistors T9A, T10A, T11A, T12A, T13A, T14A, T15A and a second capacitor C2A.

[0080] The first sensing transistor T19A may include a control electrode receiving the test signal TEST, a first electrode receiving the first pulse width data voltage WDATA1 , and a second electrode connected to the anode of the first light emitting element EEA.

[0081] In this embodiment, the second sub-pixel SUB-PX1B may include a second pulse width modulator 710B, a second pulse amplitude modulator 720B, a second sensing transistor T19B, and a second light emitting element EEB.

[0082] In addition to the second pulse width data voltage WDATA2 being applied to the second pulse width modulator 710B, the second pulse width modulator 710B may be connected to the second pulse width modulator 710B. Figure 3 The pulse width modulator 710 is substantially the same.

[0083] For example, the second pulse width modulator 710B may include a fifth transistor T5B, a sixth transistor T6B, a seventh transistor T7B, an eighth transistor T8B, a sixteenth transistor T16B, a seventeenth transistor T17B, an eighteenth transistor T18B, and a fourth capacitor C4B.

[0084] In addition to the second pulse amplitude data voltage ADATA2 being applied to the second pulse amplitude modulator 720B, the second pulse amplitude modulator 720B may be connected to the second pulse amplitude modulator 720B. Figure 3 The pulse amplitude modulator 720 is essentially the same.

[0085] For example, the second pulse amplitude modulator 720B may include ninth to fifteenth transistors T9B, T10B, T11B, T12B, T13B, T14B, T15B and a second capacitor C2B.

[0086] The second sensing transistor T19B may include a control electrode receiving the test signal TEST, a first electrode receiving the second pulse width data voltage WDATA2 , and a second electrode connected to the anode of the second light emitting element EEB.

[0087] The first gate output signal line GOL1 may be connected to the second node N2A of the first pulse width modulator 710A included in the first subpixel SUB-PX1A and the second node N2B of the second pulse width modulator 710B included in the second subpixel SUB-PX1B. The second gate output signal line GOL2 may be connected to the second electrode of the third transistor T3 included in the initializer 730 and the tenth node N10B of the second subpixel SUB-PX1B. Accordingly, the initializer 730 may jointly initialize the first gate output signal of the first subpixel SUB-PX1A and the second gate output signal of the second subpixel SUB-PX1B.

[0088] Each of the subpixels included in the conventional device may include an initializer 730. However, the initializer 730 according to the present disclosure is not included in each of the subpixels SUB-PX, but one initializer 730 may be commonly connected to the first and second subpixels SUB-PX1A and SUB-PX1B.

[0089] In an embodiment, the display panel 100 may include a first voltage drop compensation line VCL1 and a second voltage drop compensation line VCL2 .

[0090] The first voltage drop compensation line VCL1 may be connected to the eleventh node N11A of the first subpixel SUB-PX1A and the eleventh node N11B of the second subpixel SUB-PX1B. The second voltage drop compensation line VCL2 may be connected to the twelfth node N12A of the first subpixel SUB-PX1A and the twelfth node N12B of the second subpixel SUB-PX1B. Accordingly, the voltage drop compensator 740 may collectively minimize the effect of the voltage drop of the second power voltage VDDA when the threshold voltages of the first and second pulse amplitude modulators 720A and 720B are compensated.

[0091] Each of the subpixels included in the conventional device may include a voltage drop compensator 740. However, the voltage drop compensator 740 according to the present disclosure is not included in each of the subpixels SUB-PX, but one voltage drop compensator 740 may be commonly connected to the first subpixel SUB-PX1A and the second subpixel SUB-PX1B.

[0092] In an embodiment, the display panel 100 may include a first light emitting element initialization line EIL1 and a second light emitting element initialization line EIL2 .

[0093] The first light-emitting element initialization line EIL1 can be connected to the anode of the first light-emitting element EEA included in the first subpixel SUB-PX1A and the anode of the second light-emitting element EEB included in the second subpixel SUB-PX1B. The second light-emitting element initialization line EIL2 can be connected to the cathode of the first light-emitting element EEA included in the first subpixel SUB-PX1A and the cathode of the second light-emitting element EEB included in the second subpixel SUB-PX1B. Accordingly, the light-emitting element initializer 750 can jointly initialize the first light-emitting element EEA and the second light-emitting element EEB.

[0094] Each of the sub-pixels included in a conventional device may include an initializer 730, a voltage drop compensator 740, and a light-emitting element initializer 750. However, according to the present disclosure, the initializer 730, the voltage drop compensator 740, and the light-emitting element initializer 750 are not included in each sub-pixel SUB-PX. Instead, at least one of the initializer 730, the voltage drop compensator 740, and the light-emitting element initializer 750 may be commonly connected to the first sub-pixel SUB-PX1A and the second sub-pixel SUB-PX1B. Accordingly, compared to conventional pixels, the pixel PX of the present disclosure can have a reduced number of transistors and capacitors. Accordingly, the integration of the pixel PX can be improved, and the production volume of the pixel PX can be increased. In addition, the pixel PX can be applied to ultra-high-resolution display devices. The improved integration of the pixel PX makes it possible to produce products using the display panel 100 suitable for ultra-high resolution and low power consumption.

[0095] In addition, although the initializer 730, the voltage drop compensator 740 and the light-emitting element initializer 750 according to the present disclosure are not included in each of the sub-pixels SUB-PX, but at least one of the initializer 730, the voltage drop compensator 740 and the light-emitting element initializer 750 can be commonly connected to the first sub-pixel SUB-PX1A and the second sub-pixel SUB-PX1B, the driving current applied to the light-emitting element EE of the pixel PX can be substantially the same as the driving current applied to the light-emitting element of the conventional pixel.

[0096] refer to Figure 4A 、 Figure 4B and Figure 4CThe first gate output signal line GOL1 can be connected to the second node N2A of the first pulse width modulator 710A included in the first subpixel SUB-PX1A, the second node N2B of the second pulse width modulator 710B included in the second subpixel SUB-PX1B, and the second node N2C of the third pulse width modulator 710C included in the third subpixel SUB-PX1C. The second gate output signal line GOL2 can be connected to the second electrode of the third transistor T3 included in the initializer 730, the tenth node N10B of the second subpixel SUB-PX1B, and the tenth node N10C of the third subpixel SUB-PX1C. Accordingly, the initializer 730 can collectively initialize the first gate output signal of the first subpixel SUB-PX1A, the second gate output signal of the second subpixel SUB-PX1B, and the third gate output signal of the third subpixel SUB-PX1C.

[0097] In this embodiment, the third sub-pixel SUB-PX1C may include a third pulse width modulator 710C, a third pulse amplitude modulator 720C, a third sensing transistor T19C, and a third light emitting element EEC.

[0098] In addition to the third pulse width data voltage WDATA3 being applied to the third pulse width modulator 710C, the third pulse width modulator 710C may be connected to the third pulse width modulator 710C. Figure 3 The pulse width modulator 710 is substantially the same.

[0099] For example, the third pulse width modulator 710C may include a fifth transistor T5C, a sixth transistor T6C, a seventh transistor T7C, an eighth transistor T8C, a sixteenth transistor T16C, a seventeenth transistor T17C, an eighteenth transistor T18C, and a fourth capacitor C4C.

[0100] In addition to the third pulse amplitude data voltage ADATA3 being applied to the third pulse amplitude modulator 720C, the third pulse amplitude modulator 720C may be connected to the third pulse amplitude modulator 720C. Figure 3 The pulse amplitude modulator 720 is essentially the same.

[0101] For example, the third pulse amplitude modulator 720C may include ninth to fifteenth transistors T9C, T10C, T11C, T12C, T13C, T14C, and T15C and a second capacitor C2C.

[0102] The third sensing transistor T19C may include a control electrode receiving the test signal TEST, a first electrode receiving the third pulse width data voltage WDATA3 , and a second electrode connected to the anode of the third light emitting element EEC.

[0103] In an embodiment, a first voltage drop compensation line VCL1 may be connected to the eleventh node N11A of the first subpixel SUB-PX1A, the eleventh node N11B of the second subpixel SUB-PX1B, and the eleventh node N11C of the third subpixel SUB-PX1C. A second voltage drop compensation line VCL2 may be connected to the twelfth node N12A of the first subpixel SUB-PX1A, the twelfth node N12B of the second subpixel SUB-PX1B, and the twelfth node N12C of the third subpixel SUB-PX1C. Accordingly, the voltage drop compensator 740 may collectively minimize the impact of the voltage drop of the second power voltage VDDA when the threshold voltages of the first pulse amplitude modulator 720A, the second pulse amplitude modulator 720B, and the third pulse amplitude modulator 720C are compensated.

[0104] In an embodiment, the first light-emitting element initialization line EIL1 may be connected to the anode of the first light-emitting element EEA included in the first subpixel SUB-PX1A, the anode of the second light-emitting element EEB included in the second subpixel SUB-PX1B, and the anode of the third light-emitting element EEC included in the third subpixel SUB-PX1C. The second light-emitting element initialization line EIL2 may be connected to the cathode of the first light-emitting element EEA included in the first subpixel SUB-PX1A, the cathode of the second light-emitting element EEB included in the second subpixel SUB-PX1B, and the cathode of the third light-emitting element EEC included in the third subpixel SUB-PX1C. Accordingly, the light-emitting element initializer 750 may collectively initialize the first light-emitting element EEA, the second light-emitting element EEB, and the third light-emitting element EEC.

[0105] Each subpixel included in a conventional device may include an initializer 730, a voltage drop compensator 740, and a light-emitting element initializer 750. However, according to the present disclosure, the initializer 730, the voltage drop compensator 740, and the light-emitting element initializer 750 are not included in each subpixel SUB-PX. Instead, at least one of the initializer 730, the voltage drop compensator 740, and the light-emitting element initializer 750 may be commonly connected to the first subpixel SUB-PX1A, the second subpixel SUB-PX1B, and the third subpixel SUB-PX1C. Accordingly, compared to conventional pixels, the pixel PX of the present disclosure can have a reduced number of transistors and capacitors. Accordingly, the integration of the pixel PX can be improved, and the production yield of the pixel PX can be increased. In addition, the pixel PX can be applied to ultra-high-resolution display devices. The improved integration of the pixel PX makes it possible to produce products using the display panel 100 suitable for ultra-high resolution and low power consumption.

[0106] In addition, although the initializer 730, the voltage drop compensator 740 and the light-emitting element initializer 750 according to the present disclosure are not included in each of the sub-pixels SUB-PX, but at least one of the initializer 730, the voltage drop compensator 740 and the light-emitting element initializer 750 can be commonly connected to the first sub-pixel SUB-PX1A, the second sub-pixel SUB-PX1B and the third sub-pixel SUB-PX1C, the driving current applied to the light-emitting element EE of the pixel PX can be substantially the same as the driving current applied to the light-emitting element of the conventional pixel.

[0107] Figure 5A is a circuit diagram of a first subpixel SUB-PX2A connected to a voltage drop compensator 740 and a light emitting element initializer 750 in the illustrated embodiment. Figure 5B 2 is a circuit diagram of a second subpixel SUB-PX2B connected to a voltage drop compensator 740 and a light emitting element initializer 750 in the illustrated embodiment. Figure 5C 2 is a circuit diagram of a third subpixel SUB-PX2C connected to the voltage drop compensator 740 and the light emitting element initializer 750 in the illustrated embodiment.

[0108] The pixel PX according to the present embodiment includes the following: the first subpixel SUB-PX2A includes the first initializer 730A, the second subpixel SUB-PX2B includes the second initializer 730B, the third subpixel SUB-PX2C includes the third initializer 730C, the first voltage drop compensation line VCL1 and the second voltage drop compensation line VCL2 are connected to the first to third subpixels SUB-PX2A, SUB-PX2B and SUB-PX2C, and the first light emitting element initialization line EIL1 and the second light emitting element initialization line EIL2 are connected to the first to third subpixels SUB-PX2A, SUB-PX2B and SUB-PX2C. Figures 4A to 4C The same reference numerals are used for the same or similar components as those in the previous embodiment, and repeated descriptions are omitted.

[0109] In this embodiment, each of the first subpixel SUB-PX2A, the second subpixel SUB-PX2B, and the third subpixel SUB-PX2C may include an initializer 730. For example, the initializer 730 included in the first subpixel SUB-PX2A may be referred to as a first initializer 730A. For example, the initializer 730 included in the second subpixel SUB-PX2B may be referred to as a second initializer 730B. For example, the initializer 730 included in the third subpixel SUB-PX2C may be referred to as a third initializer 730C.

[0110] For example, the first initializer 730A may include a third transistor T3A and a third capacitor C3A, the second initializer 730B may include a third transistor T3B and a third capacitor C3B, and the third initializer 730C may include a third transistor T3C and a third capacitor C3C.

[0111] In an embodiment, the first voltage drop compensation line VCL1 may be connected to the eleventh node N11A of the first subpixel SUB-PX2A, the eleventh node N11B of the second subpixel SUB-PX2B, and the eleventh node N11C of the third subpixel SUB-PX2C. The second voltage drop compensation line VCL2 may be connected to the twelfth node N12A of the first subpixel SUB-PX2A, the twelfth node N12B of the second subpixel SUB-PX2B, and the twelfth node N12C of the third subpixel SUB-PX2C.

[0112] In an embodiment, the first light-emitting element initialization line EIL1 may be connected to the anode of the first light-emitting element EEA included in the first subpixel SUB-PX2A, the anode of the second light-emitting element EEB included in the second subpixel SUB-PX2B, and the anode of the third light-emitting element EEC included in the third subpixel SUB-PX2C. The second light-emitting element initialization line EIL2 may be connected to the cathode of the first light-emitting element EEA included in the first subpixel SUB-PX2A, the cathode of the second light-emitting element EEB included in the second subpixel SUB-PX2B, and the cathode of the third light-emitting element EEC included in the third subpixel SUB-PX2C.

[0113] Each of the sub-pixels included in a conventional device may have a voltage drop compensator 740 and a light-emitting element initializer 750. However, according to the present disclosure, the voltage drop compensator 740 and the light-emitting element initializer 750 are not included in each of the sub-pixels SUB-PX. Instead, at least one of the voltage drop compensator 740 and the light-emitting element initializer 750 may be commonly connected to the first sub-pixel SUB-PX2A, the second sub-pixel SUB-PX2B, and the third sub-pixel SUB-PX2C. Accordingly, compared to conventional pixels, the pixel PX of the present disclosure may have a reduced number of transistors and capacitors. Accordingly, the integration of the pixel PX may be improved, and the yield of the pixel PX may be increased. In addition, the pixel PX may be applied to an ultra-high-resolution display device. The improved integration of the pixel PX makes it possible to produce products using the display panel 100 suitable for ultra-high resolution and low power consumption.

[0114] Figure 6 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Figure 7 The diagram shows Figure 6FIG. 4 is a diagram of an example in which the electronic device is implemented as a smart phone.

[0115] refer to Figure 6 and Figure 7 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0116] According to the embodiment, Figure 7 As shown in FIG, the electronic device 1000 may be implemented as a smartphone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer, a car navigation system, a computer monitor, a laptop computer, and a head-mounted display (HMD) device.

[0117] The processor 1010 can perform various computing functions or tasks. The processor 1010 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0118] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 drive controller 200.

[0119] The memory device 1020 may store data used for the operation of the electronic apparatus 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0120] The storage device 1030 may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch panel, and a touch screen, and output devices such as a printer and a speaker. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication link.

[0121] According to the display device of the present disclosure described above, an ultra-high-resolution display device can be realized using pixels having a high degree of integration.

[0122] The foregoing is illustrative of the present disclosure and should not be construed as limiting thereof. Although embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications in the embodiments are possible without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. In the claims, means-plus-function clauses are intended to cover structures described herein as performing the detailed functions, not only structural equivalents, but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the present disclosure and should not be construed as limited to the specific embodiments disclosed, and is intended to include modifications to the disclosed embodiments as well as other embodiments within the scope of the claims. The present disclosure is defined by the claims, which include equivalents of the claims.

Claims

1. A display device comprising: a display panel, including pixels; a data driver configured to provide a data voltage to the pixel; an emission driver configured to provide an emission signal to the pixel; a gate driver configured to provide a gate signal to the pixel; as well as a driving controller configured to control the data driver, the emission driver, and the gate driver, The pixels include: a first subpixel including a first pulse width modulator and a first pulse amplitude modulator, the first pulse width modulator being configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and being configured to control a period of a first driving current applied to a first light emitting element, the first pulse amplitude modulator being configured to apply the first driving current to the first light emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage; a second subpixel including a second pulse width modulator and a second pulse amplitude modulator, the second pulse width modulator being configured to output a second gate output signal for the pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second driving current applied to a second light emitting element, the second pulse amplitude modulator being configured to apply the second driving current to the second light emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage; and The initializer is configured to initialize the first gate output signal and the second gate output signal in response to a second initialization signal.

2. The display device according to claim 1, wherein The initializer includes a third transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a second node, and a second electrode configured to receive an initialization voltage.

3. The display device according to claim 1, wherein The pixel further includes a voltage drop compensator configured to compensate for a voltage drop of the first pulse amplitude modulator and a voltage drop of the second pulse amplitude modulator.

4. The display device according to claim 3, wherein The voltage drop compensator comprises: a first transistor including a control electrode configured to receive the second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and The second transistor includes a control electrode configured to receive the first transmission signal, a first electrode connected to the first node, and a second electrode configured to receive a second power voltage.

5. The display device according to claim 1, wherein The pixel further includes a light emitting element initializer configured to initialize the first light emitting element and the second light emitting element in response to the second initialization signal. The display device according to claim 5 , wherein: The light emitting element initializer comprises: a fourth transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and The first capacitor includes a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

7. The display device according to claim 1, wherein The pixel further comprises: a voltage drop compensator configured to compensate for a voltage drop of the first pulse amplitude modulator and a voltage drop of the second pulse amplitude modulator; and The light emitting element initializer is configured to initialize the first light emitting element and the second light emitting element in response to the second initialization signal.

8. The display device according to claim 7, wherein: The voltage drop compensator comprises: a first transistor including a control electrode configured to receive the second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and a second transistor including a control electrode configured to receive a first transmission signal, a first electrode connected to the first node, and a second electrode configured to receive a second power voltage, and Wherein, the light emitting element initializer includes: a fourth transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and The first capacitor includes a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

9. The display device according to claim 1, wherein The pixel further includes a third subpixel, the third subpixel including a third pulse width modulator and a third pulse amplitude modulator, the third pulse width modulator being configured to output a third gate output signal for the pulse width modulation in response to a third pulse width data voltage different from the first pulse width data voltage and the second pulse width data voltage and configured to control a period of a third driving current applied to a third light emitting element, the third pulse amplitude modulator being configured to apply the third driving current to the third light emitting element in response to a third pulse amplitude data voltage different from the third pulse width data voltage, and The initializer is further configured to initialize the third gate output signal in response to the second initialization signal.

10. The display device according to claim 9, wherein The pixel further includes a voltage drop compensator configured to compensate for a voltage drop of the first pulse amplitude modulator, a voltage drop of the second pulse amplitude modulator, and a voltage drop of the third pulse amplitude modulator.

11. The display device according to claim 9, wherein The pixel further includes a light emitting element initializer configured to initialize the first light emitting element, the second light emitting element, and the third light emitting element in response to the second initialization signal.

12. The display device according to claim 9, wherein The pixel further comprises: a voltage drop compensator configured to compensate for a voltage drop of the first pulse amplitude modulator, a voltage drop of the second pulse amplitude modulator, and a voltage drop of the third pulse amplitude modulator; and The light emitting element initializer is configured to initialize the first light emitting element, the second light emitting element, and the third light emitting element in response to the second initialization signal.

13. The display device according to claim 12, wherein: The voltage drop compensator comprises: a first transistor including a control electrode configured to receive the second initialization signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first node; and a second transistor including a control electrode configured to receive a first transmission signal, a first electrode connected to the first node, and a second electrode configured to receive a second power voltage, and Wherein, the light emitting element initializer includes: a fourth transistor including a control electrode configured to receive the second initialization signal, a first electrode connected to a third node, and a second electrode configured to receive a third power voltage; and The first capacitor includes a first electrode connected to the third node and a second electrode configured to receive the third power voltage.

14. A display device comprising: a display panel, including pixels; a data driver configured to provide a data voltage to the pixel; an emission driver configured to provide an emission signal to the pixel; a gate driver configured to provide a gate signal to the pixel; as well as a driving controller configured to control the data driver, the emission driver, and the gate driver, The pixels include: a first subpixel, comprising a first pulse width modulator, a first pulse amplitude modulator, and a first initializer, wherein the first pulse width modulator is configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and is configured to control a period of a first driving current applied to a first light emitting element, the first pulse amplitude modulator is configured to apply the first driving current to the first light emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage, and the first initializer is configured to initialize the first gate output signal in response to a second initialization signal; a second subpixel, comprising a second pulse width modulator, a second pulse amplitude modulator, and a second initializer, the second pulse width modulator being configured to output a second gate output signal for the pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second driving current applied to a second light emitting element, the second pulse amplitude modulator being configured to apply the second driving current to the second light emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage, and the second initializer being configured to initialize the second gate output signal in response to the second initialization signal; and The voltage drop compensator is configured to compensate for the voltage drop of the first pulse amplitude modulator and the voltage drop of the second pulse amplitude modulator.

15. A display device comprising: a display panel, including pixels; a data driver configured to provide a data voltage to the pixel; an emission driver configured to provide an emission signal to the pixel; a gate driver configured to provide a gate signal to the pixel; as well as a driving controller configured to control the data driver, the emission driver, and the gate driver, The pixels include: a first subpixel, comprising a first pulse width modulator, a first pulse amplitude modulator, and a first initializer, wherein the first pulse width modulator is configured to output a first gate output signal for pulse width modulation in response to a first pulse width data voltage and is configured to control a period of a first driving current applied to a first light emitting element, the first pulse amplitude modulator is configured to apply the first driving current to the first light emitting element in response to a first pulse amplitude data voltage different from the first pulse width data voltage, and the first initializer is configured to initialize the first gate output signal in response to a second initialization signal; a second subpixel, comprising a second pulse width modulator, a second pulse amplitude modulator, and a second initializer, the second pulse width modulator being configured to output a second gate output signal for the pulse width modulation in response to a second pulse width data voltage different from the first pulse width data voltage and being configured to control a period of a second driving current applied to a second light emitting element, the second pulse amplitude modulator being configured to apply the second driving current to the second light emitting element in response to a second pulse amplitude data voltage different from the second pulse width data voltage, and the second initializer being configured to initialize the second gate output signal in response to the second initialization signal; and The light emitting element initializer is configured to initialize the first light emitting element and the second light emitting element in response to the second initialization signal.

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