Ultra-low frequency switching circuit capable of suppressing burrs

Abstract

The utility model discloses an ultra-low frequency switching circuit capable of suppressing burrs, which comprises a switching buffer circuit, the signal input end of the switching buffer circuit receives a PWM (Pulse Width Modulation) signal, and the signal output end of the switching buffer circuit is connected with the grid electrode of any MOS (Metal Oxide Semiconductor) tube of an H-bridge inverter circuit; and the switch buffer circuit is used for prolonging the turn-on and turn-off time of an MOS (Metal Oxide Semiconductor) tube of the H-bridge inverter circuit. According to the utility model, by prolonging the turn-on and turn-off time of the MOS tube, burr signals caused by transient voltage and current changes are suppressed, and drain electrode current signals are innovatively subjected to electromagnetic coupling to form negative feedback on the grid electrode, so that transient changes are suppressed, the safety of devices is guaranteed, the service life of equipment is prolonged, and the failure rate is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of switch buffer circuits, in particular to an ultra-low frequency switch circuit capable of suppressing burrs. Background Art

[0002] The inverter circuit is one of the most common circuits in electronic circuits and is widely used in various power supply designs.

[0003] During the on / off process of a MOSFET in a switching circuit, high voltage glitches are generated between the input and output terminals of the MOSFET. These glitches can break down the MOSFET, threatening the safe operation of the converter, increasing system losses, and exacerbating the converter's electromagnetic interference. Therefore, a voltage glitch absorption circuit must be installed for protection.

[0004] The root cause of this glitch is the parasitic inductance in the circuit. The parasitic inductance is difficult to estimate through analysis. A more realistic approach is to use small voltage and small current excitation to measure the glitch amplitude, and calculate the parasitic inductance through small signal analysis. Based on this, a simulation model is established to assist in the design of a reasonable suppression or absorption circuit.

[0005] Common absorption circuits include LCD type, RCD type, and simplified RC type. The basic idea is to reduce the impact of burrs on MOS tubes by quickly discharging the burrs. In essence, it is just a remedial measure and does not fundamentally suppress the generation of burrs.

[0006] Therefore, the applicant considers providing a solution to suppress burrs based on the idea of ​​burr generation. Utility Model Content

[0007] In order to overcome the deficiencies of the above-mentioned technologies, the purpose of the present invention is to provide a circuit for ultra-low frequency switching that suppresses burrs, thereby solving the problem of glitch voltage generated by MOS tubes in ultra-low frequency switches at the moment of turning on and off.

[0008] In order to achieve the above purpose, the technical solution adopted by the present utility model is as follows:

[0009] A glitch-suppressing ultra-low frequency switch circuit includes an H-bridge inverter circuit. The glitch-suppressing ultra-low frequency switch circuit includes a switch buffer circuit. The switch buffer circuit has a signal input end that receives a PWM signal and a signal output end that is connected to the gate of any MOS transistor of the H-bridge inverter circuit. The switch buffer circuit is used to extend the on and off times of the MOS transistor of the H-bridge inverter circuit.

[0010] Preferably, the switching buffer circuit includes a first resistor R1, a diode D1, a second resistor R2, a capacitor C2, and a third resistor R5; one end of the first resistor R1 serves as a PWM signal input end, and the other end is connected to the anode of the diode D1; the cathode of the diode D1 is connected to one end of the second resistor R2; one end of the capacitor C2 is connected to the connection point between the diode D1 and the second resistor R2, and the other end is grounded; the other end of the second resistor R2 away from the diode D1 serves as a signal output end and is connected to one end of the third resistor R5; the other end of the third resistor R5 away from the second resistor R2 is grounded; the second resistor R2 and the third resistor R5 form a voltage divider circuit.

[0011] Preferably, the voltage division ratio of the second resistor R2 and the third resistor R5 is 1:8-12.

[0012] Preferably, the glitch-suppressing ultra-low frequency switching circuit further includes an inductive coupling feedback circuit, wherein a signal input end of the inductive coupling feedback circuit is connected to a signal output end of the switch buffer circuit; a signal output end of the inductive coupling feedback circuit is connected to the gate of any one of the MOS transistors of the H-bridge inverter circuit, and the inductive coupling feedback circuit couples a signal at the drain of the MOS transistor and transmits it to the gate of the MOS transistor for coupling the drain capacitance of the MOS transistor to a gate drive waveform, thereby forming negative feedback.

[0013] Preferably, the inductive coupling feedback circuit includes an inductor L1, one end of which is connected to the signal output terminal of the switch buffer circuit, and the other end of which is connected to the gate of any MOS transistor of the H-bridge inverter circuit. This circuit is applicable to each MOS transistor of the H-bridge inverter circuit.

[0014] Preferably, the coil of the inductor L1 is wound around the wire of the drain of the MOS transistor connected to it, coupling the drain current of the MOS transistor to its gate drive waveform; the wire connects the drain of the MOS transistor connected to the inductor L1 and the source of another MOS transistor in the same bridge arm, and is connected to one end of the AC motor.

[0015] Preferably, the H-bridge inverter circuit includes a second MOS transistor M2, a third MOS transistor M3, a fifth MOS transistor M5, and a fourth MOS transistor M4; the gates of any one or more of the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, and the fourth MOS transistor M4 are respectively connected to one of the ultra-low frequency switching circuits for suppressing burrs. The ultra-low frequency switching circuit for suppressing burrs can be adapted to any one of the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, and the fourth MOS transistor M4 through simple level conversion.

[0016] Further preferably, the drain of the fifth MOS transistor M5 is connected to the source of the third MOS transistor M3, and the source is connected to the source of the fourth MOS transistor M4; the drain of the third MOS transistor M3 is connected to the drain of the second MOS transistor M2; the source of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4; the H-bridge inverter circuit further includes an AC motor MG1, one end of which is connected to the source of the third MOS transistor M3 and the drain of the fifth MOS transistor M5, and the other end is connected to the source of the second MOS transistor M2 and the drain of the fourth MOS transistor M4.

[0017] Preferably, the frequency of the ultra-low frequency switch is ≤2KHz.

[0018] Preferably, the ultra-low frequency switch is an ultra-low frequency switch of a gate opening and closing machine drive tube.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] This new design adjusts its approach, focusing on suppressing burrs. By analyzing the mechanism of burr generation, it slows down the on-time of the MOS tube, thereby suppressing burrs. This new design is suitable for gate hoist control applications and is suitable for ultra-low frequency switching below 2 kHz.

[0021] This utility model includes a switch buffer circuit and an electromagnetic coupling feedback circuit. The switch buffer circuit is only suitable for ultra-low switching frequency applications. This utility model reduces the glitch voltage generated by the MOS tube during the turn-on and turn-off moments and suppresses the glitch signal, protecting the MOS tube from overvoltage breakdown, ensuring device safety, extending equipment life, and reducing failure rates.

[0022] The utility model extends the turn-on and turn-off time of the MOS tube, suppresses the glitch signal caused by instantaneous voltage and current changes, increases coupling at the drain, and innovatively forms negative feedback at the gate through electromagnetic coupling of the drain current signal, suppressing transient changes, ensuring device safety, extending equipment service life, and reducing failure rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is the overall circuit diagram of a glitch-suppressing ultra-low frequency switch circuit of the utility model;

[0024] Figure 2 This is the gate voltage rise time diagram of the WSP6067A MOS tube;

[0025] Figure 3 This is the glitch diagram of the original circuit of the MOS tube;

[0026] Figure 4 These are two conventional glitch absorption circuit diagrams;

[0027] Figure 5 This is a comparison chart of the original glitch, the glitch after electromagnetic coupling feedback, and the gate voltage. In the figure, curve A is the MOS tube voltage drop curve, curve B is the MOS tube voltage drop curve with the addition of inductor L1 electromagnetic coupling, and curve C is the MOS tube gate voltage curve with the addition of inductor L1 electromagnetic coupling.

[0028] Figure 6 This is a comparison diagram of the turn-on delay effect of an embodiment of this solution, where curve A is the MOS tube boost curve, and curve B is the MOS tube boost curve after adding a switch buffer circuit;

[0029] Figure 7 The following figure compares the original turn-on glitch and the glitch after applying this solution. Curve A shows the turn-on glitch of the MOS tube, and curve B shows the turn-on glitch of the MOS tube after adding the switch buffer circuit.

[0030] Figure 8 The figure shows a comparison between the original turn-off glitch and the glitch after applying this solution. Curve A shows the turn-off glitch of the MOS tube, and curve B shows the turn-off glitch of the MOS tube after adding the switch buffer circuit. DETAILED DESCRIPTION

[0031] In order to better explain the present invention, the main contents of the present invention are further illustrated below in combination with specific embodiments, but the contents of the present invention are not limited to the following embodiments.

[0032] like Figure 1 As shown, the present invention provides a glitch-suppressing ultra-low-frequency switching circuit, comprising a switch buffer circuit and an inductive coupling feedback circuit, wherein the ultra-low-frequency switch includes an H-bridge inverter circuit. The switch buffer circuit receives a PWM signal at its signal input, and its signal output is connected to the signal input of the inductive coupling feedback circuit. The switch buffer circuit is used to extend the on- and off-times of the MOS transistor of the H-bridge inverter circuit; the signal output of the inductive coupling feedback circuit is connected to the MOS transistor of the H-bridge inverter circuit, and the inductive coupling feedback circuit couples a signal at the drain of the MOS transistor and transmits it to the gate of the MOS transistor to couple the drain current of the MOS transistor to the gate drive waveform.

[0033] The switching snubber circuit is used to extend the on- and off-times of each MOS transistor in the H-bridge inverter circuit. The switching snubber circuit consists of a first resistor R1, a diode D1, a second resistor R2, a capacitor C2, and a third resistor R5. One end of the first resistor R1 serves as the signal input, and the other end is connected to the anode of diode D1. The cathode of diode D1 is connected to the second resistor R2. One end of capacitor C2 is connected to the junction of diode D1 and the second resistor R2, and the other end is grounded. The other end of the second resistor R2, away from diode D1, serves as the signal output and is connected to the signal input of the inductively coupled feedback circuit. One end of the third resistor R5 is connected to the end of the second resistor R2, away from diode D1, forming a voltage divider circuit with the second resistor R2. The other end of the third resistor R5 is grounded. The voltage divider ratio between the second resistor R2 and the third resistor R5 is typically 1:8 to 12.

[0034] The inductively coupled feedback circuit is used to couple the drain current of the MOS transistor in the H-bridge inverter circuit to the gate drive waveform, forming negative feedback. The inductively coupled feedback circuit includes an inductor L1. One end of the inductor L1 is connected to the signal output terminal of the second resistor R2, and the other end is connected to the gate of the MOS transistor in the H-bridge inverter circuit.

[0035] like Figure 1 As shown, the H-bridge inverter circuit includes a second MOS transistor M2, a third MOS transistor M3, a fifth MOS transistor M5, and a fourth MOS transistor M4. The drain of the fifth MOS transistor M5 is connected to the source of the third MOS transistor M3, and its source is connected to the source of the fourth MOS transistor M4. The drain of the third MOS transistor M3 is connected to the drain of the second MOS transistor M2, and the source of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4. The H-bridge inverter circuit also includes an AC motor MGI, one end of which is connected to the source of the third MOS transistor M3 and the drain of the fifth MOS transistor M5, and the other end is connected to the source of the second MOS transistor M2 and the drain of the fourth MOS transistor M4. In actual use, the gates of the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, and the fourth MOS transistor M4 all use the ultra-low frequency switching circuit for glitch suppression of the present invention, wherein the third MOS transistor M3 and the second MOS transistor M2 only need to undergo simple level conversion.

[0036] In an inductively coupled feedback circuit, a wire connecting the drain of a MOS transistor passes through the magnetic core of inductor L1, coupling the drain current of the MOS transistor to its gate drive waveform. This wire connects the drain of the MOS transistor connected to inductor L1 to the source of another MOS transistor in the same bridge arm, and is also connected to one end of the load MG1. For example, the gate of the fifth MOS transistor M5 is connected to inductor L1, and the coil of inductor L1 is wrapped around the wire connecting the drain of the fifth MOS transistor M5 to the source of the third MOS transistor M3, coupling the drain current of the fifth MOS transistor M5 to the gate drive waveform of the fifth MOS transistor M5.

[0037] The glitch-suppressing ultra-low-frequency switch circuit described above can be used to eliminate the glitch voltage generated by the ultra-low-frequency switch during its turn-on and turn-off. The frequency of the ultra-low-frequency switch is ≤ 2 kHz. The ultra-low-frequency switch is used for the gate hoist drive tube.

[0038] The following describes the use principle and technical idea of ​​the present invention in detail by taking the gate of the fifth MOS tube M5 connected to the ultra-low frequency switch circuit for suppressing burrs of the present invention as an example.

[0039] MOS tubes are needed as switching tubes in many fields such as DC-DC voltage regulation, AC-DC inverter, motor drive, etc., and different voltage transformation purposes are achieved through different configurations. Figure 1 Part B is the H-bridge inverter circuit of the gate opening and closing machine drive tube.

[0040] The operating principle of the ultra-low frequency switching circuit for suppressing burrs in the utility model is as follows:

[0041] When the MOS transistor needs to be turned on, the high level of the control signal PWM is limited by the first resistor R1, and then charges the capacitor C2 through the diode D1. The voltage on the capacitor C2 is divided by the second resistor R2 and the third resistor R5 (in this specific embodiment, the voltage division ratio is 1:10), and then charges the gate of the fifth MOS transistor M5 through the electromagnetic coupling inductor L1. The gate level exceeds its turn-on threshold voltage V TH When , the MOS tube is turned on.

[0042] When the MOS transistor is turned off, the low level of the shutdown signal PWM cannot directly lower the gate voltage of the fifth MOS transistor M5 due to the blocking effect of the diode D1. The gate voltage can only be discharged through the inductor L1 and the third resistor R5.

[0043] There are three processes involved here:

[0044] First, the high level passes through the delay circuit composed of the first resistor R1 and the capacitor C2, which can slow down the rising time of the gate voltage of the fifth MOS transistor M5;

[0045] Second, due to the electromagnetic coupling effect of the inductor L1, a voltage signal is coupled from the drain (D) current of the fifth MOS transistor M5 to adjust the gate (G) voltage of the fifth MOS transistor M5. The greater the drain current, the higher the voltage coupled by the inductor L1, which further suppresses the gate voltage of the fifth MOS transistor M5, thus playing a negative feedback role.

[0046] Third, when the fifth MOS transistor M5 is turned off, the gate voltage of the fifth MOS transistor M5 is slowly discharged through the inductor L1 and the third resistor R5. Since the capacitor C2 is much larger than the equivalent gate capacitance of the fifth MOS transistor M5 itself, the turn-off time is further delayed. At this time, the coupling effect of the inductor L1 can also suppress the drop of the gate voltage of the fifth MOS transistor M5.

[0047] First, let's analyze the second process, specifically the role of the electromagnetic coupling signal of inductor L1 in reducing burrs in the present invention. For this specific analysis, we use the domestically produced WSP6067A MOS transistor (hereinafter referred to as the "MOS transistor") as a reference for the fifth MOS transistor M5. The following analysis is performed:

[0048] According to the test standard indicated in the device manual, the gate input resistance is 3.3Ω and the gate equivalent charge Q g is 19nC (equivalent to a capacitor), the voltage across the MOS tube is V DC is 30V, the gate drive voltage V GS is 10V, MOS conduction current I D The equivalent capacitance C across the MOS tube is 1A. DS It is about 1nF. According to the device manual, the turn-on time under this test condition is about 34ns.

[0049] The MOS tube turn-on time in the H-bridge inverter circuit is calculated by the following formula:

[0050]

[0051] Where, I D is the MOS conduction current, C DS is the equivalent capacitance across the MOS tube, V DC is the voltage across the MOS tube, and t is the turn-on time of the MOS tube.

[0052] First, we sort out the parameters and analysis methods related to glitch. Using the above formula, we calculate the turn-on time to be 30ns.

[0053]

[0054] WSP6067A MOS tube gate conduction threshold voltage V TH is 2V, the transconductance gfs of this type of MOS tube is 28S, I D =1A corresponds to a gate voltage increment of 0.035V (I D ÷gfs), so it takes about 4ns for the gate voltage to rise from 0V to 2.035V, such as Figure 2 As shown, adding the gate turn-on time of 30ns, the total is approximately 34ns, which is consistent with the device manual. This verifies that the calculation is reasonable and can be used for characteristic analysis.

[0055] Next, bring in the actual design value to estimate the burr risk. According to the specific working conditions of the project application, the conduction current (I D ) requires 5A, V DS =20V, then the turn-on time t can be calculated as 4ns. Adding the gate turn-on delay, the total delay is estimated to be 8ns. In actual circuits, long traces will bring parasitic inductance. This parasitic inductance will form burrs at the moment of turn-on and turn-off, becoming a hidden danger of MOSFET breakdown. Figure 3 shown.

[0056] like Figure 3 As shown, the V DC =20V, I D =5A, the voltage across the MOS tube before turning on is equal to V DC At the moment the MOS tube is turned on, the drain current suddenly increases, and the parasitic inductance in the circuit generates a glitch voltage. At this time, the glitch voltage is about 10V (the maximum voltage minus V DS ), according to the formula of parasitic inductance generating burrs:

[0057]

[0058] Where V is the glitch voltage, i.e. 10V, I D =5A, t is the estimated turn-on time (8ns) above, then the actual circuit parasitic inductance (L) can be calculated to be approximately 16nH. The glitch voltage here is approximately V DC In some circuits, especially those with higher power, the parasitic inductance is much larger than 16nH, I D It is also much larger than 5A. At this time, the glitch voltage can even reach V DC twice as much, which can easily cause the MOS tube to break down.

[0059] Therefore, it is necessary to add protection measures such as glitch suppression or absorption circuit for the MOS tube.

[0060] Common protection measures are glitch absorption circuits, usually CD type, CRD type, and simplified CR type, such as Figure 4 Figure 1 shows the CD and CRD spike absorption circuits used in prior art. The basic concept behind prior art spike absorption circuits is to absorb and limit spikes at both ends of the switching tube using capacitors and diodes, which is a post-processing remedy. The present invention uses electromagnetic coupling to couple the MOS tube drain capacitance to the gate drive waveform, creating negative feedback. This suppresses the gate voltage when high drain current appears at the turn-on instant.

[0061] like Figure 5As shown, curve A is the MOS tube voltage drop curve, curve B is the MOS tube voltage drop curve with the addition of inductor L1 electromagnetic coupling, and curve C is the MOS tube gate voltage curve with the addition of inductor L1 electromagnetic coupling. Figure 5 It can be seen that during normal switching, a glitch of approximately 10V is generated; after adding L1 coupling, the glitch voltage is significantly reduced to approximately 3V. The MOS transistor gate waveform also shows that when the MOS transistor is turned on, the gate voltage shows a significant slowdown, suppressing the generation of glitch. The higher the coupling degree of inductor L1, the greater the glitch suppression effect. In practical applications, for coupling circuits below 100W, the present invention wraps the coil of inductor L1 around a wire that connects the drain of the MOS transistor connected to inductor L1 to the source of another MOS transistor, coupling the drain capacitance of the MOS transistor to its gate drive waveform.

[0062] The following is an analysis of the switch buffer circuit, which is the first process mentioned above. According to the device manual, Figure 6 As shown in the curve A, it takes about 4ns for the gate voltage to rise from 0V to 2.035V. After the switch buffer circuit is used in the present invention, Figure 6 As shown in Curve B, after the delay caused by first resistor R1, diode D1, and capacitor C2, the gate voltage rises to approximately 320ns. A longer turn-on time means greater heat generation for the MOS transistor. Therefore, this delay circuit cannot be used indefinitely, as this could easily cause the MOS transistor to overheat and burn out. This is why most inverter circuits strive for a quick turn-on of the MOS transistor. This delay scheme is suitable for ultra-low switching frequencies (0.5-2 kHz).

[0063] After combining the two effects of gate turn-on delay and electromagnetic coupling inductor L1 feedback, the glitch waveform of the MOS tube is greatly improved, such as Figure 7 As shown, it can be seen that the original waveform is Figure 7 As shown in the middle curve A, there is a glitch of about 10V, and after turning on, there is a significant damping phenomenon due to the presence of parasitic inductance L1. After using the switch buffer circuit to delay the gate turn-on and the electromagnetic coupling inductance L1, as shown in the figure Figure 7 As shown in the middle curve B, the MOS tube voltage drop glitch voltage caused by the turn-on delay and electromagnetic coupling of the inductor L1 is only 3V, and there is no damping phenomenon after turning on.

[0064] The shutdown process is similar to the opening process, such as Figure 8 As shown in the curve A, the difference is that the burr becomes a downward negative voltage, and the oscillation damping phenomenon occurs at V DC That is around 20V. Figure 8 As shown in the middle curve B, after adding the electromagnetic coupling of inductor L1 and the switch snubber circuit, the glitch is only 2V and there is no damping phenomenon.

[0065] The above calculations and comparisons prove that the burr suppression scheme of the utility model, which is applicable to the ultra-low frequency switching of the gate hoist drive tube, is completely different from the current idea of ​​absorbing burrs in the MOS tube switch drive circuit. Instead, it is a scheme that suppresses the generation of burrs from the principle, and the effect is significant. In the application of the gate hoist drive, the MOS tube breakdown phenomenon caused by the instantaneous burrs of the switch can be effectively reduced. In the smart irrigation project, the failure of the gate will cause problems such as canal water overflowing the embankment and crops being soaked in water. The utility model ensures the normal operation of the electric gate equipment and avoids the loss of people's property caused by equipment failure.

[0066] It should be understood that the terms "first," "second," "third," "fourth," and "fifth" do not represent any sequential relationship, but are merely distinctions made for the convenience of description. Those skilled in the art will understand the specific meanings of the above terms in this utility model in specific circumstances.

[0067] It should be understood that the above description of the preferred embodiment is relatively detailed and cannot be regarded as limiting the scope of protection of the patent of the utility model. Under the guidance of the utility model, ordinary technicians in this field can also make substitutions or modifications without departing from the scope of protection of the claims of the utility model, which all fall within the scope of protection of the utility model. The scope of protection requested for the utility model shall be based on the attached claims.

Claims

1. A circuit for an ultra-low frequency switch for suppressing burrs, the ultra-low frequency switch comprising an H-bridge inverter circuit, characterized in that: The ultra-low frequency switching circuit for suppressing burrs includes a switch buffer circuit, wherein a signal input end of the switch buffer circuit receives a PWM signal, and a signal output end is connected to the gate of any MOS tube of the H-bridge inverter circuit; the switch buffer circuit is used to extend the on and off time of the MOS tube of the H-bridge inverter circuit.

2. The circuit according to claim 1, wherein: The switching buffer circuit includes a first resistor R1, a diode D1, a second resistor R2, a capacitor C2, and a third resistor R5; one end of the first resistor R1 serves as a PWM signal input end, and the other end is connected to the anode of the diode D1; the cathode of the diode D1 is connected to one end of the second resistor R2; one end of the capacitor C2 is connected to the connection between the diode D1 and the second resistor R2, and the other end is grounded; the other end of the second resistor R2 away from the diode D1 serves as a signal output end and is connected to one end of the third resistor R5; the other end of the third resistor R5 away from the second resistor R2 is grounded; the second resistor R2 and the third resistor R5 form a voltage divider circuit.

3. The circuit according to claim 2, wherein: The voltage division ratio of the second resistor R2 and the third resistor R5 is 1:8-12.

4. The circuit according to claim 1, wherein: The device further includes an inductive coupling feedback circuit, wherein the signal input end of the inductive coupling feedback circuit is connected to the signal output end of the switch buffer circuit; the signal output end of the inductive coupling feedback circuit is connected to the gate of any MOS tube of the H-bridge inverter circuit, and the inductive coupling feedback circuit couples a signal at the drain of the MOS tube and transmits it to the gate of the MOS tube for coupling the drain capacitance of the MOS tube to the gate drive waveform to form negative feedback.

5. The circuit according to claim 4, characterized in that: The inductive coupling feedback circuit includes an inductor L1 , one end of which is connected to the signal output end of the switch buffer circuit, and the other end of which is connected to the gate of any MOS transistor of the H-bridge inverter circuit.

6. The circuit according to claim 5, characterized in that: The coil of the inductor L1 is wound around the wire of the drain of the MOS transistor connected to it, coupling the drain capacitance of the MOS transistor to its gate drive waveform; the wire connects the drain of the MOS transistor connected to the inductor L1 and the source of another MOS transistor.

7. The circuit according to claim 1, wherein: The H-bridge inverter circuit includes a second MOS transistor M2, a third MOS transistor M3, a fifth MOS transistor M5, and a fourth MOS transistor M4; the gates of any one or more of the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, and the fourth MOS transistor M4 are respectively connected to one of the ultra-low frequency switching circuits for suppressing burrs.

8. The circuit according to any one of claims 1 to 7, characterized in that: The frequency of the ultra-low frequency switch is ≤2KHz.

9. The circuit according to claim 8, characterized in that: The ultra-low frequency switch is an ultra-low frequency switch of the gate opening and closing machine drive tube.

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