Startup and shutdown circuit

Abstract

The utility model discloses a startup and shutdown circuit, which relates to the field of startup and shutdown circuits, and is characterized in that a PMOS (P-channel Metal Oxide Semiconductor) tube is used for controlling connection and disconnection between a power supply and equipment, and a grid electrode of the PMOS tube is simultaneously connected with a key switch and a switching element controlled by startup and shutdown software. When the equipment is started, the key switch and the switch element are closed at will, so that conduction of the PMOS transistor can be achieved, and a user can select software starting or hardware starting according to actual requirements conveniently. When the equipment is shut down, the PMOS transistor can be cut off only when the key switch and the switch element are switched off at the same time, so that the equipment can be shut down only through startup and shutdown software, and the startup and shutdown software ensures that a data processing system in the equipment stops running and data in the equipment is stored completely before the equipment is powered off. According to the utility model, the problems that a software startup mode and a hardware startup mode cannot be selected according to requirements, important data is easy to lose when hardware is shut down, and a data processing system in equipment is easy to damage are solved.

Description

Technical Field

[0001] The utility model relates to the field of power on / off circuits, and more particularly to a power on / off circuit. Background Art

[0002] Currently, there are two main ways to design power on / off circuits in medical equipment: one is hardware-controlled power on / off, and the other is software-controlled power on / off.

[0003] The hardware power on / off method uses a push button to control the device's power on and off. Its advantages are its simple implementation and complete power cutoff. However, its disadvantages are that closing the push button immediately turns the device on, failing to prevent accidental touches. Opening the push button immediately turns the device off. Turning off the device while it's processing or storing data can easily lead to the loss of important data and damage to the device's data processing system.

[0004] To prevent the loss of important data and damage to the device's data processing system, current medical devices often use software to control the device's power on and off. This approach offers the advantage of waiting until the device's data processing system has ceased operation and all data has been stored before shutting down the device. Furthermore, software can be used to set power-on conditions to prevent accidental power-on triggering. For example, the device will only power on after the power-on command has been maintained for a certain period of time.

[0005] Therefore, it is necessary to provide a power-on / off circuit that takes into account the advantages of both hardware and software power-on and software power-off to meet the power-on requirements of different devices, while solving the problem that hardware power-off is prone to losing important data and damaging the data processing system in the device. Utility Model Content

[0006] In view of the problems in the prior art that the device startup mode is single and it is impossible to select software startup mode and hardware startup mode according to needs, and the problem that hardware shutdown is prone to loss of important data and damage to the data processing system in the device, the purpose of the present utility model is to provide a power on / off circuit, including a PMOS tube Q1, a resistor R1, a switching element and a push button switch.

[0007] The drain of the PMOS transistor Q1 is connected to the device, the source of the PMOS transistor Q1 is connected to the power supply, and the two ends of the resistor R1 are connected to the gate and source of the PMOS transistor Q1 respectively.

[0008] The switching element and the push-button switch are both connected to the gate of the PMOS transistor Q1. The switching element and the push-button switch are each grounded. When either the switching element or the push-button switch is closed, the PMOS transistor Q1 is turned on. When both the switching element and the push-button switch are open, the PMOS transistor Q1 is turned off. The switching element is turned on and off by signals from the power-on / off software.

[0009] The utility model is further configured as follows: the switching element is an NMOS tube Q2, the source of the NMOS tube Q2 is grounded, the drain of the NMOS tube Q2 is connected to the gate of the PMOS tube Q1, and the gate of the NMOS tube Q2 is used to receive the signal sent by the power on / off software.

[0010] The present invention is further configured to include a resistor R2, and the gate of the NMOS tube Q2 is connected to the component equipped with the power on / off software via the resistor R2.

[0011] The present invention is further configured to include a key detection component, which is used to detect the open and closed state of the key switch and output different signals to the power on and off software based on the open and closed states of the key switch.

[0012] The present invention further comprises an NMOS transistor Q3, a detector, and a diode D1. The gate of the PMOS transistor Q1 is connected to the key switch via the diode D1, the gate of the PMOS transistor Q1 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the key switch. The source of the NMOS transistor Q3 is grounded, the drain of the NMOS transistor Q3 is connected to the external power supply VCC1, the gate of the NMOS transistor Q3 is connected between the cathode of the diode D1 and the key switch, and the external power supply VCC2 is connected between the cathode of the diode D1 and the gate of the NMOS transistor Q3. The signal input terminal of the detector is connected between the drain of the NMOS transistor Q3 and the external power supply VCC1, and the signal of the detector is output to the component carrying the power on / off software. In this embodiment, the component carrying the power on / off software is an MCU chip.

[0013] The present invention is further configured to include: a diode D2, a gate of the NMOS tube Q3 is connected to the anode of the diode D2, and a cathode of the diode D2 is connected between the key switch and the cathode of the diode D1; an external power supply VCC2 is connected between the gate of the NMOS tube Q3 and the anode of the diode D2, and an external power supply VDD is connected between the cathode of the diode D1 and the cathode of the diode D2, and the external power supply VDD is the power supply connected to the PMOS tube Q1.

[0014] The present invention is further configured to include a resistor R3 , and the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2 and the anode of the diode D1 via the resistor R3 .

[0015] The present invention further comprises an LED lamp 1 and an LED lamp 2, wherein one end of the LED lamp 1 is grounded, and the other end of the LED lamp 1 is connected between the source of the PMOS transistor Q1 and a power supply. One end of the LED lamp 2 is grounded, and the other end of the LED lamp 2 is connected between the drain of the PMOS transistor Q1 and a device.

[0016] The utility model is further configured to include: a power common-mode filter PCMF, through which the power supply is connected to the source of the PMOS tube Q1; the power common-mode filter PCMF has four pins, two of which are connected to the power supply, one is grounded, and one is connected to the source of the PMOS tube Q1.

[0017] The utility model is further configured as follows: it also includes a TVS tube 1 and a TVS tube 2, the two ends of the TVS tube 1 are respectively connected to the two pins of the power common mode filter PCMF connected to the power supply; one end of the TVS tube 2 is connected to the pin of the key switch connected to the diode D2, and the other end of the TVS tube 2 is grounded.

[0018] In summary, the present invention has the following beneficial effects compared to the prior art: The present invention provides a circuit that takes into account both software power on and off and hardware power on, and controls the conduction and cutoff between the power supply and the device through the PMOS tube Q1. The gate of the PMOS tube Q1 is simultaneously connected to the key switch and the switch element controlled by the power on and off software. When the device is turned on, the PMOS tube Q1 can be turned on by closing the key switch and the switch element at will, which is convenient for users to choose software power on or hardware power on according to actual needs. When the device is turned off, the key switch and the switch element are disconnected at the same time to achieve the cutoff of the PMOS tube Q1, so that the device must be turned off through the power on and off software, so that the delay setting in the power on and off software can be used to ensure that the data processing system inside the device stops running and the data in the device is stored before the device is powered off. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the overall structure of Example 1. DETAILED DESCRIPTION

[0020] The technical solution of the present invention will be clearly described below in conjunction with the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the utility model.

[0021] It should be noted that the terms "center", "up", "down", "horizontal", "left", "right", "front", "back", "lateral", "longitudinal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0022] The key switch, equipment and power supply are not shown in the figure.

[0023] Example

[0024] like Figure 1 The figure shows a schematic diagram of the structure of a preferred embodiment of the present invention. This embodiment provides a power on / off circuit, which includes a PMOS transistor Q1, a resistor R1, a switch element, and a push button switch. The drain of the PMOS transistor Q1 is connected to the device, and the source of the PMOS transistor Q1 is connected to the power supply. The two ends of the resistor R1 are respectively connected to the gate and source of the PMOS transistor Q1. The switch element and the push button switch are both connected to the gate of the PMOS transistor Q1. The switch element and the push button switch are each grounded. When any one of the switch element and the push button switch is closed, the PMOS transistor Q1 is turned on. When all the switch elements and the push button switch are opened, the PMOS transistor Q1 is turned off. The opening and closing of the switch element is controlled by a signal sent by the power on / off software.

[0025] This embodiment provides a circuit that combines software-based and hardware-based power-on and power-off. To prevent accidental power-on, some devices require the power-on software to receive a power-on command for a period of time before controlling the power-on process. For such devices, a switch element is suitable for controlling the conduction of the PMOS transistor Q1. The power-on software determines whether the duration of the power-on command meets the required duration. After determining whether the duration of the power-on command meets the required duration, the power-on software sends a power-on signal to the switch element, closing the switch element, ultimately achieving the effect of preventing accidental power-on. For some devices that do not require accidental power-on protection, a pushbutton switch is suitable for controlling the conduction of the PMOS transistor Q1 to achieve a quick power-on. When shutting down the device, the switch element and pushbutton switch of this embodiment must be completely disconnected before the device can be shut down. This means that the device must go through the shutdown process of the power-on software. The power-on software can delay sending a signal to the switch element based on the operating status of the device's data processing system to ensure that the internal data processing system is stopped and the data stored in the device is complete before the device is powered off.

[0026] Specifically, the circuit also includes capacitor C1, with its two terminals connected to the gate and source of PMOS transistor Q1, respectively. Capacitor C1 filters high-frequency noise from PMOS transistor Q1 and reduces the impact of transient voltage changes on PMOS transistor Q1 when it is turned on. Resistor R1 is used for voltage division, ensuring that the VGS voltage of PMOS transistor Q1 reaches the turn-on voltage and turns on. Capacitor C1 improves circuit stability.

[0027] Specifically, the switch element is an NMOS transistor Q2 , the source of the NMOS transistor Q2 is grounded, the drain of the NMOS transistor Q2 is connected to the gate of the PMOS transistor Q1 , and the gate of the NMOS transistor Q2 is used to receive a signal sent by the power on / off software.

[0028] This embodiment further includes a resistor R2, through which the gate of the NMOS transistor Q2 is connected to the component carrying the power-on / off software. Resistor R2 reduces noise in the power-on / off software signal, thereby reducing the risk of false triggering of the NMOS transistor Q2.

[0029] This embodiment also includes a resistor R6. One end of the resistor R6 is grounded, and the other end of the resistor R6 is connected between the component carrying the power-on / off software and the gate of the NMOS transistor Q2. The resistor R6 is used to reduce the voltage fluctuation amplitude at the gate of the NMOS transistor Q2, thereby improving the anti-interference capability of the NMOS transistor Q2 and further reducing the risk of false triggering of the NMOS transistor Q2.

[0030] This embodiment also includes a Schottky diode D3 and a capacitor C2. The Schottky diode D3 is connected in parallel with the resistor R2, with the anode of the Schottky diode D3 connected to the gate of the NMOS transistor Q2, and the cathode of the Schottky diode D3 connected to the component that carries the power-on / off software. One end of the capacitor C2 is grounded, and the other end of the capacitor C2 is connected to the gate of the NMOS transistor Q2. The Schottky diode D3 is used to quickly discharge the gate voltage of the NMOS transistor Q2 when the software system shuts down, eliminating the need for current limiting through the resistor R2.

[0031] Resistor R2 and capacitor C2 cooperate to form an RC delay circuit to reduce the risk of uncontrollable shutdown.

[0032] This embodiment also includes a key detection component that detects the open and closed states of the key switch and outputs different signals to the power-on / off software based on the open and closed states of the key switch. If the key switch is non-self-locking and cannot remain closed without external force, the power-on / off software can be configured to determine the open and closed state of the key switch based on the signal output by the key detection component. After the key switch is closed once, it will continue to send power-on signals to control the closing of the switch element. This makes this embodiment compatible with both non-self-locking key switches and self-locking key switches.

[0033] Specifically, the key detection component includes an NMOS transistor Q3, a detector and a diode D1. The gate of the PMOS transistor Q1 is connected to the key switch through the diode D1, the gate of the PMOS transistor Q1 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the key switch; the source of the NMOS transistor Q3 is grounded, the drain of the NMOS transistor Q3 is connected to the external power supply VCC1, the gate of the NMOS transistor Q3 is connected between the cathode of the diode D1 and the key switch, and the external power supply VCC2 is connected between the cathode of the diode D1 and the gate of the NMOS transistor Q3; the signal input end of the detector is connected between the drain of the NMOS transistor Q3 and the external power supply VCC1, and the signal of the detector is output to the component equipped with the power on / off software.

[0034] Diode D1 blocks the voltage from external power supply VCC2 from flowing to the switch element, so the gate voltage of NMOS transistor Q3 is affected only by the on / off state of the pushbutton switch. When the pushbutton switch is open, the high voltage level provided by external power supply VCC2 turns on NMOS transistor Q3, generating the detector's output signal. When the pushbutton switch is closed, the gate voltage of NMOS transistor Q3 is pulled down, turning off NMOS transistor Q3 and ceasing the detector's output signal.

[0035] This embodiment also includes a diode D2. The gate of the NMOS transistor Q3 is connected to the anode of diode D2, and the cathode of diode D2 is connected between the key switch and the cathode of diode D1. An external power supply VCC2 is connected between the gate of the NMOS transistor Q3 and the anode of diode D2. An external power supply VDD is connected between the cathodes of diode D1 and diode D2. External power supply VDD is also the power supply connected to the PMOS transistor Q1. Diode D2 is used to prevent current from flowing into the gate of the NMOS transistor Q3, thereby protecting the NMOS transistor Q3. When the key switch is closed, the external power supply VDD is used to direct current to flow toward the key switch, turning on the NMOS transistor Q3. When the switch is open, the external power supply VDD maintains a high voltage, ensuring that the PMOS transistor Q1 is in a non-conducting state, thereby protecting the diode D2.

[0036] This embodiment further includes a resistor R7 and a capacitor C3. One end of the resistor R7 is grounded, and the other end is connected between the external power supply VCC2 and the gate of the NMOS transistor Q3. One end of the capacitor C3 is grounded, and the other end is connected between the external power supply VCC2 and the gate of the NMOS transistor Q3. Both the resistor R7 and the capacitor C3 reduce the voltage fluctuation amplitude at the gate of the NMOS transistor Q3, thereby improving the anti-interference capability of the NMOS transistor Q3 and reducing the risk of false triggering of the NMOS transistor Q3.

[0037] This embodiment also includes a resistor R8. The external power supply VCC3 is connected to the drain of the NMOS transistor Q3 via resistor R8. The detector's signal input is connected between resistor R8 and the drain of the NMOS transistor Q3. Resistor R8 acts as a pull-up resistor. When the NMOS transistor Q3 is on, the detector signal is low. When the NMOS transistor Q3 is off, the detector signal is pulled up to the external power supply VCC3 via R8, resulting in a high signal.

[0038] This embodiment further includes a resistor R9. The external power supply VCC2 is connected between the cathode of the diode D1 and the gate of the NMOS transistor Q3 through the resistor R9. The resistor R9 is used to keep the gate of the NMOS transistor Q3 at a high voltage when the switch button is turned off, thereby keeping the NMOS transistor Q3 turned on.

[0039] This embodiment further includes a diode D4, with its anode connected to the external power supply VDD and its cathode connected between the cathodes of diode D1 and diode D2. Diode D4 is used to protect the external power supply VDD when the power supply is connected to the power on / off circuit.

[0040] This embodiment further includes a resistor R10, through which the cathode of diode D4 is connected between the cathodes of diode D1 and diode D2. Resistor R10 is used to maintain a voltage drop across resistor R1 of PMOS transistor Q1 when the switch is off, thereby keeping PMOS transistor Q1 stably turned off.

[0041] This embodiment also includes a resistor R3. The gate of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q2 and the anode of the diode D1 via the resistor R3. After resistor R3 and resistor R1 are properly configured, when a key is pressed or the software is turned on, a voltage is applied across resistor R1 that enables Q1 to reach a stable turn-on voltage.

[0042] This embodiment also includes LED lamp 1 and LED lamp 2. One end of LED lamp 1 is grounded, and the other end is connected between the source of PMOS transistor Q1 and the power supply. One end of LED lamp 2 is grounded, and the other end is connected between the drain of PMOS transistor Q1 and the device. When LED lamp 1 lights up, the power supply is connected to the power on / off circuit. When LED lamp 2 lights up, the PMOS transistor Q1 is turned on, and the power supply is connected to the device.

[0043] This embodiment also includes a resistor R4. At least one resistor R4 is provided. If multiple resistors R4 are provided, all resistors R4 are connected in parallel. LED lamp 1 is connected between the source of PMOS transistor Q1 and the power supply via resistor R4. Resistor R4 is used to limit the current flowing through LED lamp 1 and protect it. In this embodiment, two resistors R4 are provided.

[0044] This embodiment also includes a resistor R5. At least one resistor R5 is provided. If multiple resistors R5 are provided, all resistors R5 are connected in parallel. LED lamp 2 is connected between the drain of PMOS transistor Q1 and the device via resistor R5. Resistor R5 is used to limit the current flowing through LED lamp 2 and protect it. In this embodiment, two resistors R5 are provided.

[0045] This embodiment also includes a power common-mode filter (PCMF), through which the power supply is connected to the source of the PMOS transistor Q1. The power common-mode filter (PCMF) has four pins: two connected to the power supply, one connected to ground, and one connected to the source of the PMOS transistor Q1. The power common-mode filter (PCMF) is used to filter out common-mode noise from the power supply to prevent it from affecting device operation.

[0046] This embodiment also includes TVS diodes 1 and 2. The two ends of TVS diode 1 are connected to the two pins of the power supply common-mode filter PCMF connected to the power supply. One end of TVS diode 2 is connected to the pin of the key switch connected to diode D2, and the other end of TVS diode 2 is grounded. TVS diode 1 is used to reduce the impact of transient voltage on the power supply common-mode filter PCMF when the power supply is connected to the power switch circuit, thereby protecting the power supply common-mode filter PCMF. TVS diode 2 is used to reduce the impact of transient voltage on the human body when the key switch is pressed to close, thereby protecting the safety of the person who presses the key to close the key.

[0047] This embodiment further includes a resistor R11, through which the key switch is connected to the diode D1, the diode D2, and the resistor R10. The resistor R11 is used to limit the current flowing to the key switch to protect the safety of the person pressing the key.

[0048] This embodiment further includes a fuse F, and one pin of the power common mode filter PCMF is connected to the power supply via the fuse F. The fuse F is configured to blow when the current provided by the power supply is too high, thereby protecting the device and other components in the power supply circuit.

[0049] Specifically, this embodiment further includes a connector HX1 and a connector HX2. The fuse F and the power common-mode filter PCMF are connected to the power supply via the connector HX1. The key switch is connected to the TVS tube 1 and the resistor R11 via the connector HX2, and the key switch is grounded via the connector HX2.

[0050] In summary, this embodiment provides a circuit that allows for both software-based and hardware-based power-ups. The PMOS transistor Q1 controls the conduction and cutoff between the power supply and the device. The gate of the PMOS transistor Q1 is connected to both a key switch and a switch element controlled by the power-up and power-down software. When the device is powered on, the PMOS transistor Q1 can be turned on by closing either the key switch or the switch element, making it easy for the user to choose between software-based and hardware-based power-ups. When the device is powered off, the key switch and the switch element must be opened simultaneously to cut off the PMOS transistor Q1. This means that the device must be powered off using the power-up and power-down software. This ensures that the device's internal data processing system stops running and data storage is complete before the device is powered off, using the delay settings within the power-up and power-down software.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A power on / off circuit, characterized in that: Including PMOS tube Q1, resistor R1, switch element and key switch; The drain of the PMOS tube Q1 is connected to the device, and the source of the PMOS tube Q1 is connected to the power supply; the two ends of the resistor R1 are respectively connected to the gate and source of the PMOS tube Q1; The switching element and the key switch are both connected to the gate of the PMOS tube Q1. The switching element and the key switch are grounded respectively. When any one of the switching element and the key switch is closed, the PMOS tube Q1 is turned on; when all the switching elements and the key switches are opened, the PMOS tube Q1 is turned off. The opening and closing of the switching element is controlled by the signal sent by the power on and off software.

2. The power on / off circuit according to claim 1, wherein: The switch element is an NMOS transistor Q2 , the source of the NMOS transistor Q2 is grounded, the drain of the NMOS transistor Q2 is connected to the gate of the PMOS transistor Q1 , and the gate of the NMOS transistor Q2 is used to receive a signal sent by the power on / off software.

3. The power on / off circuit according to claim 2, wherein: It also includes a resistor R2, and the gate of the NMOS tube Q2 is connected to the component equipped with the power on / off software through the resistor R2.

4. The power on / off circuit according to claim 1, wherein: It also includes a key detection component, which is used to detect the open and closed state of the key switch and output different signals to the power on and off software based on the open and closed states of the key switch.

5. The power on / off circuit according to claim 4, wherein: The key detection component includes an NMOS transistor Q3, a detector and a diode D1. The gate of the PMOS transistor Q1 is connected to the key switch through the diode D1, the gate of the PMOS transistor Q1 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the key switch; the source of the NMOS transistor Q3 is grounded, the drain of the NMOS transistor Q3 is connected to the external power supply VCC1, the gate of the NMOS transistor Q3 is connected between the cathode of the diode D1 and the key switch, and the external power supply VCC2 is connected between the cathode of the diode D1 and the gate of the NMOS transistor Q3; the signal input end of the detector is connected between the drain of the NMOS transistor Q3 and the external power supply VCC1, and the signal of the detector is output to the component equipped with the power on / off software.

6. The power on / off circuit according to claim 5, wherein: It also includes a diode D2. The gate of the NMOS tube Q3 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected between the key switch and the cathode of the diode D1. The external power supply VCC2 is connected between the gate of the NMOS tube Q3 and the anode of the diode D2. The external power supply VDD is connected between the cathodes of the diode D1 and the cathodes of the diode D2. The external power supply VDD is the power supply connected to the PMOS tube Q1.

7. The power on / off circuit according to claim 6, wherein: A resistor R3 is also included, and the gate of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q2 and the anode of the diode D1 through the resistor R3.

8. The power on / off circuit according to claim 1, wherein: It also includes LED lamp 1 and LED lamp 2. One end of LED lamp 1 is grounded, and the other end of LED lamp 1 is connected between the source of PMOS tube Q1 and the power supply; one end of LED lamp 2 is grounded, and the other end of LED lamp 2 is connected between the drain of PMOS tube Q1 and the device.

9. A power on / off circuit according to any one of claims 1 to 8, characterized in that: It also includes a power common-mode filter PCMF, through which the power supply is connected to the source of the PMOS tube Q1; the power common-mode filter PCMF has four pins, two of which are connected to the power supply, one pin is grounded, and one pin is connected to the source of the PMOS tube Q1.

10. The power on / off circuit according to claim 9, characterized in that: It also includes TVS tube 1 and TVS tube 2. The two ends of TVS tube 1 are respectively connected to the two pins of the power common mode filter PCMF connected to the power supply; one end of TVS tube 2 is connected to the pin of the key switch connected to the diode D2, and the other end of TVS tube 2 is grounded.

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