NMOS (N-channel metal oxide semiconductor) high-edge anti-reverse circuit
By using the complementary PWM signal to control the switching circuit through the NMOS tube high side anti-reverse circuit, the voltage instability and ground offset problems caused by the NMOS tube low side anti-reverse connection are solved, and low-cost anti-reverse protection is achieved.
Patent Information
- Application Number
- CN202422715477.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2034-11-07
AI Technical Summary
In the prior art, when NMOS tubes are used for low-side reverse polarity protection of power supplies, the power supply ground and the system ground are not at the same potential, resulting in ground offset, unstable power supply voltage, and the need for an internal driver module in the power management chip, which is costly.
It adopts NMOS tube high-side anti-reverse circuit, uses two complementary PWM signals to control multiple switching circuits, realizes anti-reverse function through NMOS tube control circuit, uses common discrete devices, and does not require a special integrated circuit to drive NMOS tube function.
The NMOS tube has high-side reverse connection protection, good circuit stability, low cost, and easy implementation, avoiding the problems of ground offset and voltage instability.
Smart Images
Figure CN223309845U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a protection circuit technology. Background Art
[0002] Reverse polarity protection is a crucial component of port circuit protection. Common reverse polarity protection circuit structures often utilize diodes or MOS transistors. When operating at high currents, diodes typically have much lower current carrying capacity than MOS transistors, leading to excessive junction temperature increases, impacting device lifespan and circuit stability and reliability. In applications using MOS transistors for reverse polarity protection, PMOS transistors are typically used at the power input for high-side reverse polarity protection, while NMOS transistors are used at the GND terminal for low-side reverse polarity protection. PMOS transistors are expensive. While NMOS transistors offer price advantages over PMOS transistors, in practice, NMOS transistors are typically placed at the GND terminal (i.e., at the low-side of the power supply). This can cause the power supply and system grounds to be at different potentials, resulting in a ground offset and unstable power supply voltage. Furthermore, existing reverse polarity protection circuits using NMOS transistors typically utilize a driver module within the power management chip to drive the NMOS transistor. This solution requires the chip to be integrated with the corresponding driver module. Summary of the Invention
[0003] The technical problem to be solved by the utility model is to provide an anti-reverse circuit which uses an NMOS tube to realize the high-side anti-reverse of a power supply end.
[0004] The embodiment of the utility model provides an NMOS tube high-side anti-reverse circuit, including an NMOS tube Q5 and an NMOS tube control circuit; the source of the NMOS tube Q5 is connected to the voltage input terminal Vin, and the drain of the NMOS tube Q5 is connected to the voltage output terminal Vout; the NMOS tube control circuit includes a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a capacitor C1, a unidirectional conductive element D1, a voltage-stabilizing diode D2 and a controller; the first end of the unidirectional conductive element D1 and the first conductive end of the second switch circuit are respectively connected to the voltage input terminal Vin, the second end of the unidirectional conductive element D1 is respectively connected to the first end of the capacitor C1 and the first conductive end of the first switch circuit, the second conductive end of the first switch circuit is respectively connected to the gate of the NMOS tube Q5 and the cathode of the voltage-stabilizing diode D2, and the anode of the voltage-stabilizing diode D2 is grounded; The current conduction direction of the conduction element D1 is from its first end to its second end; the second conduction end of the second switch circuit is respectively connected to the second end of the capacitor C1 and the first conduction end of the third switch circuit, and the second conduction end of the third switch circuit is grounded; the power input end of the controller is connected to the drain of the NMOS transistor Q5, and the output end of the controller is respectively connected to the controlled end of the third switch circuit and the controlled end of the fourth switch circuit. The controller is used to output two complementary PMW signals to the third switch circuit and the fourth switch circuit respectively after power-on; the first conduction end of the fourth switch circuit is respectively connected to the controlled end of the first switch circuit and the controlled end of the second switch circuit, and the second conduction end of the fourth switch circuit is grounded; when the fourth switch circuit is turned on, the first switch circuit and the second switch circuit are turned on, and when the fourth switch circuit is turned off, the first switch circuit and the second switch circuit are turned off.
[0005] The utility model has at least the following advantages and features:
[0006] 1. The NMOS tube high-side anti-reverse circuit of the embodiment of the utility model uses two complementary PWM signals to control multiple switch circuits, thereby realizing the anti-reverse function of the NMOS tube;
[0007] 2. The NMOS tube high-side anti-reverse circuit of the embodiment of the utility model is composed of common discrete devices, and does not require the use of a special integrated circuit with the function of driving the NMOS tube. It is easy to implement and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 The circuit principle diagram of the NMOS tube high-side anti-reverse circuit according to the embodiment of the utility model is shown.
[0009] Figure 2 A control block diagram of a controller according to an embodiment of the present utility model is shown. DETAILED DESCRIPTION
[0010] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0011] Figure 1 The following is a circuit diagram of an NMOS tube high-side anti-reverse circuit according to an embodiment of the present invention. Figure 2 A control block diagram of a controller according to an embodiment of the present invention is shown. Figure 1 and Figure 2 The NMOS transistor high-side anti-reverse circuit of this embodiment includes an NMOS transistor Q5 and an NMOS transistor control circuit 100 .
[0012] The source of the NMOS transistor Q5 is connected to the voltage input terminal Vin, and the drain of the NMOS transistor Q5 is connected to the voltage output terminal Vout. In actual operation, the voltage input terminal Vin is connected to the positive pole of the power supply, and the voltage output terminal Vout is connected to the subsequent circuit. The subsequent circuit can be a load, etc. Figure 1 The GND in it represents the power ground.
[0013] The NMOS transistor control circuit 100 includes a first switch circuit 1 , a second switch circuit 2 , a third switch circuit 3 , a fourth switch circuit 4 , a capacitor C1 , a unidirectional conducting element D1 , a voltage stabilizing diode D2 and a controller 5 .
[0014] The first end of the unidirectional conductive element D1 and the first conductive end of the second switch circuit 2 are respectively connected to the voltage input terminal Vin. The second end of the unidirectional conductive element D1 is respectively connected to the first end of the capacitor C1 and the first conductive end of the first switch circuit 1. The second conductive end of the first switch circuit 1 is respectively connected to the gate of the NMOS transistor Q5 and the cathode of the Zener diode D2. The anode of the Zener diode D2 is grounded. The current conducting direction of the unidirectional conductive element D1 is from its first end to its second end. Optionally, the unidirectional conductive element D1 is formed by a diode, with the anode of the diode forming the first end of the unidirectional conductive element D1 and the cathode of the diode forming the second end of the unidirectional conductive element D1.
[0015] The second conducting end of the second switch circuit 2 is connected to the second end of the capacitor C1 and the first conducting end of the third switch circuit 3 respectively, and the second conducting end of the third switch circuit 3 is grounded.
[0016] The power input terminal of the controller 5 is connected to the drain of the NMOS tube Q5, and the output terminal of the controller 5 is connected to the controlled terminal of the third switch circuit 3 and the controlled terminal of the fourth switch circuit 4 respectively. The controller 5 is used to output two complementary PMW signals to the third switch circuit 3 and the fourth switch circuit 4 respectively after power-on.
[0017] The first conducting end of the fourth switch circuit 4 is respectively connected to the controlled end of the first switch circuit 1 and the controlled end of the second switch circuit 2, and the second conducting end of the fourth switch circuit 4 is grounded; when the fourth switch circuit 4 is turned on, the first switch circuit 1 and the second switch circuit 2 are turned on, and when the fourth switch circuit 4 is turned off, the first switch circuit 1 and the second switch circuit 2 are turned off.
[0018] Furthermore, the NMOS transistor control circuit 100 of this embodiment includes a resistor R1 and a capacitor C2. The first end of the resistor R1 is connected to the second conductive end of the first switch circuit 1, and the second end of the resistor R1 is connected to the cathode of the voltage regulator D2 and the gate of the NMOS transistor Q5. The first end of the capacitor C2 is connected to the first end of the resistor R1 and the second conductive end of the first switch circuit 1, and the second end of the capacitor C2 is grounded. The resistor R1 acts as a current limiter, and the capacitor C2 is used to store energy and quickly turn on the NMOS transistor Q5.
[0019] In this embodiment, the first switch circuit 1 includes a PNP transistor Q1, a resistor R2, and a resistor R4. The common connection point between the emitter of the PNP transistor Q1 and the first end of the resistor R2 constitutes the first conducting end of the first switch circuit 1, the collector of the PNP transistor Q1 constitutes the second conducting end of the first switch circuit 1, and the base of the PNP transistor Q4 is connected to the first end of the resistor R4 and the second end of the resistor R2, respectively, with the second end of the resistor R4 constituting the controlled end of the first switch circuit 1. The second switch circuit 2 includes a PNP transistor Q2, a resistor R5, and a resistor R7. The common connection point between the emitter of the PNP transistor Q2 and the first end of the resistor R5 constitutes the first conducting end of the second switch circuit 2, the collector of the PNP transistor Q2 constitutes the second conducting end of the second switch circuit 2, the base of the PNP transistor Q2 is connected to the first end of the resistor R7, and the common connection point between the second end of the resistor R7 and the second end of the resistor R5 constitutes the controlled end of the second switch circuit 2. The third switch circuit 3 includes an NPN transistor Q3, a resistor R3, and a resistor R6. The collector of the NPN transistor Q3 forms the first conducting terminal of the third switch circuit 3. The common connection point between the emitter of the NPN transistor Q3 and the first end of the resistor R6 forms the second conducting terminal of the third switch circuit 3. The base of the NPN transistor Q3 is connected to the first end of the resistor R3 and the second end of the resistor R6, respectively. The second end of the resistor R3 forms the controlled terminal of the third switch circuit 3. The fourth switch circuit 4 includes an NPN transistor Q4, a resistor R8, and a resistor R9. The collector of the NPN transistor Q4 forms the first conducting terminal of the fourth switch circuit. The common connection point between the emitter of the NPN transistor Q4 and the first end of the resistor R9 forms the second conducting terminal of the fourth switch circuit. The base of the NPN transistor Q4 is connected to the first end of the resistor R8 and the second end of the resistor R9, respectively. The second end of the resistor R8 forms the controlled terminal of the fourth switch circuit 4.
[0020] In this embodiment, the controller 5 is an MCU, the power input terminal of the MCU is connected to the drain of the NMOS tube Q5, and the first general input and output port GPIO1 and the second general input and output port GPIO2 of the MCU are respectively connected to the controlled end of the third switch circuit 3 and the controlled end of the fourth switch circuit 4.
[0021] The working principle of the NMOS tube high-side anti-reverse circuit according to an embodiment of the present invention is described as follows.
[0022] When the power supply Vin is just powered on, the MCU's first general-purpose input / output port GPIO1 and second general-purpose input / output port GPIO2 have no output; the voltage of the input voltage input terminal Vin supplies power to the MCU through the body diode of the NMOS transistor Q5. After the MCU is powered on, two complementary PMW signals are output to the third switch circuit 3 and the fourth switch circuit 4 through the first general-purpose input / output port GPIO1 and the second general-purpose input / output port GPIO2, respectively.
[0023] Because the two PWM signals are complementary, when the output signal of the first general-purpose input / output port GPIO1 is low, the output signal of the second general-purpose input / output port GPIO2 is high. At this point, NPN transistor Q4 is turned off. After NPN transistor Q4 is turned off, PNP transistors Q2 and Q1 are also turned off (i.e., the fourth switch circuit 4, the first switch circuit 1, and the second switch circuit 2 are all in the off state). The gate of NMOS transistor Q5 has no voltage, and its internal trench cannot be opened, so it is in the off state. The output signal of the second general-purpose input / output port GPIO2 is high, NPN transistor Q3 is turned on (i.e., the third switch circuit 3 is in the on state), and the voltage across capacitor C1 is the input voltage Vin minus the voltage drop of diode D1.
[0024] When the output signal of the first general-purpose input / output port GPIO1 is high and the output signal of the second general-purpose input / output port GPIO2 is low, NPN transistor Q3 is turned off and NPN transistor Q4 is turned on. After NPN transistor Q4 is turned on, PNP transistor Q2 and PNP transistor Q1 are also turned on (i.e., the third switch circuit 3 is in the off state, and the fourth switch circuit 4, the first switch circuit 1, and the second switch circuit 2 are all in the on state). Since the voltage across capacitor C1 in the previous stage is approximately the input voltage Vin, after PNP transistor Q2 is turned on, the voltage across capacitor C1 cannot suddenly change. Therefore, the voltage across the other end of capacitor C1 will eventually become twice the input voltage. The twice input voltage flows to the back end through PNP transistor Q1, and after being protected by Zener diode D2, it supplies power to the gate of NMOS transistor Q5. At this time, the Vgs voltage of NMOS transistor Q5 is greater than its Vgs turn-on voltage, and the internal trench will open, increasing the current capacity.
[0025] Afterwards, the MCU continues to output complementary PWM signals to ensure that the Vgs voltage of the NMOS tube Q5 is greater than its conduction voltage, thereby maintaining the conduction of the NMOS tube Q5.
[0026] Taking the input voltage of 13.5V at the voltage input terminal Vin as an example, as the complementary PWM signal is output, the emitter voltage of the PNP transistor Q1 will stabilize at twice the input voltage minus a diode drop, which is approximately 26V. Due to the clamping of the Zener diode D2, the gate voltage of the NMOS transistor Q5 is ultimately limited to 20V. At this time, the Vgs voltage is greater than its turn-on voltage, and the NMOS transistor Q5 is turned on.
[0027] When the power supply is connected reversely, due to the presence of the body diode of the NMOS transistor Q5, there is no potential difference between the gate and source of the NMOS transistor Q5, and the NMOS transistor Q5 is turned off, thereby achieving the function of preventing reverse connection.
[0028] The NMOS tube high-side anti-reverse circuit of the embodiment of the utility model is composed of common discrete devices, and does not need to use a special integrated circuit with the function of driving the NMOS tube. It is easy to implement and low in cost.
[0029] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims
1. An NMOS tube high-side anti-reverse circuit, characterized in that: Including NMOS tube Q5 and NMOS tube control circuit; The source of the NMOS transistor Q5 is connected to the voltage input terminal Vin, and the drain of the NMOS transistor Q5 is connected to the voltage output terminal Vout; The NMOS transistor control circuit includes a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a capacitor C1, a unidirectional conductive element D1, a voltage regulator diode D2 and a controller; The first end of the unidirectional conducting element D1 and the first conducting end of the second switch circuit are respectively connected to the voltage input terminal Vin. The second end of the unidirectional conducting element D1 is respectively connected to the first end of the capacitor C1 and the first conducting end of the first switch circuit. The second conducting end of the first switch circuit is respectively connected to the gate of the NMOS transistor Q5 and the cathode of the Zener diode D2. The anode of the Zener diode D2 is grounded. The current conducting direction of the unidirectional conducting element D1 is from its first end to its second end. The second conducting end of the second switch circuit is connected to the second end of the capacitor C1 and the first conducting end of the third switch circuit respectively, and the second conducting end of the third switch circuit is grounded; The power input terminal of the controller is connected to the drain of the NMOS transistor Q5, and the output terminal of the controller is connected to the controlled terminal of the third switch circuit and the controlled terminal of the fourth switch circuit respectively. The controller is used to output two complementary PMW signals to the third switch circuit and the fourth switch circuit respectively after power-on; The first conduction end of the fourth switch circuit is respectively connected to the controlled end of the first switch circuit and the controlled end of the second switch circuit, and the second conduction end of the fourth switch circuit is grounded; when the fourth switch circuit is turned on, the first switch circuit and the second switch circuit are turned on, and when the fourth switch circuit is turned off, the first switch circuit and the second switch circuit are turned off.
2. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The first switching circuit includes a PNP transistor Q1, a resistor R2 and a resistor R4; the common connection point of the emitter of the PNP transistor Q1 and the first end of the resistor R2 constitutes the first conduction end of the first switching circuit, the collector of the PNP transistor Q1 constitutes the second conduction end of the first switching circuit, the base of the PNP transistor Q4 is respectively connected to the first end of the resistor R4 and the second end of the resistor R2, and the second end of the resistor R4 constitutes the controlled end of the first switching circuit.
3. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The second switching circuit includes a PNP transistor Q2, a resistor R5 and a resistor R7; the common connection point of the emitter of the PNP transistor Q2 and the first end of the resistor R5 constitutes the first conduction end of the second switching circuit, the collector of the PNP transistor Q2 constitutes the second conduction end of the second switching circuit, the base of the PNP transistor Q2 is connected to the first end of the resistor R7, and the common connection point of the second end of the resistor R7 and the second end of the resistor R5 constitutes the controlled end of the second switching circuit.
4. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The third switching circuit includes an NPN transistor Q3, a resistor R3 and a resistor R6; the collector of the NPN transistor Q3 constitutes the first conduction end of the third switching circuit, the common connection point of the emitter of the NPN transistor Q3 and the first end of the resistor R6 constitutes the second conduction end of the third switching circuit, the base of the NPN transistor Q3 is connected to the first end of the resistor R3 and the second end of the resistor R6 respectively, and the second end of the resistor R3 constitutes the controlled end of the third switching circuit.
5. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The fourth switching circuit includes an NPN transistor Q4, a resistor R8 and a resistor R9; the collector of the NPN transistor Q4 constitutes the first conduction end of the fourth switching circuit, the common connection point of the emitter of the NPN transistor Q4 and the first end of the resistor R9 constitutes the second conduction end of the fourth switching circuit, the base of the NPN transistor Q4 is connected to the first end of the resistor R8 and the second end of the resistor R9 respectively, and the second end of the resistor R8 constitutes the controlled end of the fourth switching circuit.
6. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The unidirectional conducting element D1 is formed by a diode, the anode of the diode forms a first end of the unidirectional conducting element D1 , and the cathode of the diode forms a second end of the unidirectional conducting element D1 .
7. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The NMOS transistor control circuit includes a resistor R1, a first end of the resistor R1 is connected to the second conduction end of the first switch circuit, and a second end of the resistor R1 is connected to the cathode of the voltage regulator tube D2 and the gate of the NMOS tube Q5 respectively.
8. The NMOS tube high side anti-reverse circuit according to claim 7, characterized in that: The NMOS transistor control circuit includes a capacitor C2, a first end of the capacitor C2 is respectively connected to the first end of the resistor R1 and the second conduction end of the first switch circuit, and a second end of the capacitor C2 is grounded.
9. The NMOS tube high side anti-reverse circuit according to claim 1, characterized in that: The controller is MCU.