Automatic test system of intelligent substation

Abstract

The utility model relates to the technical field of power system automation, in particular to an automatic test system for an intelligent substation, which comprises a man-machine interaction module, an input and output module, a first signal conditioning module, a second signal conditioning module, a controller module, a wireless communication module, a clock module, a data storage module and a power supply module. The controller module can interact with other modules, the input and output module simulates switching actions to the tested automation device, or the tested automation device outputs switching values to the input and output module, and then the automation device sends action results to the main control unit module. The main control unit module compares self detection data with data sent by the tested automation device, and a test result is obtained rapidly and accurately.

Description

Technical Field

[0001] The utility model relates to the technical field of power system automation, in particular to an intelligent substation automatic testing system. Background Art

[0002] In power systems, automation devices in smart substations, such as protection and measurement and control systems, monitor and control the entire substation's primary and secondary equipment. They also offer time-sensitive testing capabilities, including remote control holdover time, remote signaling anti-shake, and SOE resolution. With the development of smart grids, an increasing number of new smart substations are being built. The reliability and performance of these devices directly impacts the safe operation of substations, making testing of smart substation automation devices crucial.

[0003] Currently, time-correlation testing of automation devices is still performed with the help of debugging tools with single functions, such as multimeters, oscilloscopes, and simple switch quantity testers. Some of these instruments have simple functions, are inconvenient to use, and have low accuracy. Some require the coordination of multiple instruments to complete the test, which cannot meet the needs of smart substation testing. Utility Model Content

[0004] The purpose of the present invention is to provide an intelligent substation automatic testing system to solve the problems of inconvenient and low-precision testing of intelligent substation automation devices in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solutions:

[0006] An intelligent substation automatic test system includes a human-computer interaction module, an input-output module, a first signal conditioning module, a second signal conditioning module, a controller module, a wireless communication module, a clock module, a data storage module and a power supply module; the human-computer interaction module, the wireless communication module, the clock module, the data storage module and the power supply module are respectively connected to the controller module: the output end of the controller module is connected to the input end of the input-output module through the first signal conditioning module, and the output end of the input-output module is connected to the input end of the controller module; the controller module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a Flash data storage control unit and a data reading unit; the AD acquisition control unit, the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the Flash data storage control unit and the data reading unit are respectively connected to the data processing and RAM read-write module unit.

[0007] As a further preferred solution of the intelligent substation automatic test system of the present invention, the first signal conditioning module and the second signal conditioning module both include an amplifier circuit and a dual-op-amp bandpass filter. The amplifier circuit is composed of an OPA277 operational amplifier and resistors and capacitors, and the dual-op-amp bandpass filter is composed of two OPA277 operational amplifiers.

[0008] As a further preferred solution of the intelligent substation automatic test system of the present invention, the data storage module adopts ST's S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128 Mbit and establishes communication with the external controller through the SPI interface. The clock frequency of the interface can reach up to 104 MHz.

[0009] As a further preferred solution of the intelligent substation automatic test system of the present invention, the human-computer interaction module includes an input unit and an output unit, the input unit is electrically connected to the output unit, and the input unit is electrically connected to the controller module.

[0010] As a further preferred solution of the intelligent substation automatic test system of the present invention, the input unit includes a keyboard or a touch screen.

[0011] As a further preferred solution of the intelligent substation automatic testing system of the present utility model, the output unit includes a display screen.

[0012] As a further preferred solution of the intelligent substation automatic test system of the utility model, the circuits of the first signal conditioning module and the second signal conditioning module specifically include a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein the signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power supply pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and the output pin of the first operational amplifier, the signal input +IN terminal is connected to one end of the second resistor, and the other end of the second resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power supply pin of the first operational amplifier. The positive power supply pin of the first operational amplifier, one end of the fourth resistor, and one end of the second capacitor are connected. The other end of the second capacitor is connected to the other end of the fourth resistor and grounded. The output pin of the first operational amplifier is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier. The negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier. The positive power supply pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor. The other end of the ninth resistor is grounded. The other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier. The other end of the seventh resistor is connected to one end of the fourth capacitor. The other end of the fourth capacitor is respectively connected to one end of the ninth resistor. The other end of the ninth resistor is connected to one end of the third capacitor. The other end of the third capacitor is grounded.

[0013] As a further preferred embodiment of the intelligent substation automatic test system of the present invention, the power module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first electrolytic capacitor E1, a second electrolytic capacitor E2, a third electrolytic capacitor E3, a fourth electrolytic capacitor E4, a fifth electrolytic capacitor E5, a first switching power supply chip U1, a second switching power supply chip U2, a voltage stabilizing chip U3, a voltage input terminal, a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal;

[0014] The voltage input terminal is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to one end of the third capacitor C3, the anode of the first electrolytic capacitor E1, one end of the first resistor R1, and the pin 6 of the first switching power supply U1.

[0015] The other end of the first resistor R1 is connected to pin 7 of the first switching power supply chip U1, pin 8 of the first switching power supply chip U1, and pin 1 of the first switching power supply chip U1 respectively;

[0016] Pin 2 of the first switching power supply chip U1 is connected to the cathode of the second diode D2 and one end of the first inductor L1 respectively;

[0017] The other end of the first inductor L1 is respectively connected to the positive electrode of the first electrolytic capacitor E1, one end of the first capacitor C1 and the first voltage output end;

[0018] The other end of the first capacitor C1 is respectively connected to the cathode of the first electrolytic capacitor E1, the anode of the second diode D2, one end of the fourth capacitor C4, pin 4 of the first switching power supply chip U1, one end of the fifth resistor R5, the cathode of the third electrolytic capacitor E3 and the other end of the third capacitor C3;

[0019] The other end of the fourth capacitor C4 is connected to pin 3 of the first switching power supply chip U1;

[0020] The other end of the fifth resistor R5 is connected to the pin 5 of the first switching power supply chip U1 and one end of the third resistor R3 respectively;

[0021] The other end of the third resistor R3 is connected to the first voltage output end;

[0022] The other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, the positive electrode of the fourth electrolytic capacitor E4, one end of the second resistor R2, and pin 6 of the second switching power supply chip U2;

[0023] The other end of the second resistor R2 is connected to pin 7 of the second switching power supply chip U2, pin 8 of the second switching power supply chip U2, and pin 1 of the second switching power supply chip U2 respectively;

[0024] Pin 2 of the second switching power supply chip U2 is connected to the cathode of the second diode D3 and one end of the second inductor L2 respectively;

[0025] The other end of the second inductor L2 is respectively connected to the positive electrode of the second electrolytic capacitor E2, one end of the second capacitor C2, the second voltage output end and the pin 3 of the voltage stabilizing chip U3;

[0026] The other end of the second capacitor C2 is respectively connected to pin 1 of the voltage stabilizing chip U3, the negative electrode of the fifth capacitor E5, one end of the seventh capacitor C7, the negative electrode of the second electrolytic capacitor E2, the positive electrode of the third diode D3, one end of the sixth capacitor C6, pin 4 of the second switching power supply chip U2, one end of the sixth resistor R6, the negative electrode of the fourth electrolytic capacitor E4 and the other end of the fifth capacitor C5;

[0027] The other end of the sixth capacitor C6 is connected to pin 3 of the second switching power supply chip U2, the other end of the sixth resistor R6 is connected to pin 5 of the second switching power supply chip U2 and one end of the fourth resistor R4, respectively, and the other end of the fourth resistor R4 is connected to the second voltage output terminal;

[0028] The other end of the seventh capacitor C7 is respectively connected to the positive electrode of the electrolytic capacitor E5, the pin 2 of the voltage stabilizing chip U3, the pin 4 of the voltage stabilizing chip U3 and the third voltage output terminal.

[0029] Compared with the prior art, the above technical solution adopted by the present invention has the following technical effects:

[0030] The utility model provides an automatic test system for an intelligent substation, comprising a human-computer interaction module, an input-output module, a first signal conditioning module, a second signal conditioning module, a controller module, a wireless communication module, a clock module, a data storage module and a power supply module; the human-computer interaction module, the wireless communication module, the clock module, the data storage module and the power supply module are respectively connected to the controller module: the output end of the controller module is connected to the input end of the input-output module through the first signal conditioning module, and the output end of the input-output module is connected to the input end of the controller module; the controller module can interact with other modules, simulate a switch action to the automated device under test through the input-output module, or the automated device under test outputs a switch value to the input-output module, and then the automated device sends the action result to the main control unit module, and the main control unit module compares its own detection data with the data sent by the automated device under test to quickly and accurately obtain the test result;

[0031] The controller module of the utility model adopts Xilinx's Spartan6 series FPGA as the core control device, realizes the functions of data acquisition control, data caching, data processing, data storage, data transmission and synchronous clock control, and has the characteristics of high precision, fast speed, good reliability, strong real-time performance and low cost. The 16-channel real-time, high-speed and high-precision synchronous data acquisition system with FPGA as the main processor has a sampling frequency of 200 kHz in actual monitoring projects. The FPGA is used to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous and high-speed acquisition functions required by the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application, but do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 This is the structural principle diagram of the utility model intelligent substation automatic testing system;

[0034] Figure 2 This is a schematic diagram of the structure of the controller module of the utility model;

[0035] Figure 3 This is a circuit diagram of the signal conditioning module of the utility model;

[0036] Figure 4 This is a circuit diagram of the power module of the utility model. DETAILED DESCRIPTION

[0037] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The exemplary embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention:

[0039] Smart substation automatic test system, such as Figure 1 As shown, it includes a human-computer interaction module, an input-output module, a first signal conditioning module, a second signal conditioning module, a controller module, a wireless communication module, a clock module, a data storage module and a power supply module; the human-computer interaction module, the wireless communication module, the clock module, the data storage module and the power supply module are respectively connected to the controller module: the output end of the controller module is connected to the input end of the input-output module through the first signal conditioning module, and the output end of the input-output module is connected to the input end of the controller module.

[0040] Principle: It specifically includes the following steps;

[0041] Step 1: Set relevant parameters through the human-computer interaction module and send them to the main control unit module. The parameters include outputting a specified time and a specified interval delay;

[0042] Step 2: The controller module receives the function parameters set by the human-computer interaction module and sends relevant parameter instructions to the input and output module;

[0043] Step 3: The intelligent substation automation device under test receives the control signal of the input and output module, and sends the action result to the main control unit module in the form of a message through the network port. The main control unit module parses the relevant message and obtains the test result.

[0044] like Figure 2As shown, the controller module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a Flash data storage control unit, and a data reading unit. The AD acquisition control unit, the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the Flash data storage control unit, and the data reading unit are respectively connected to the data processing and RAM read-write module unit.

[0045] After the system is powered on, it waits for the FPGA to initialize and enters the waiting-for-connection state. When relevant command parameters are input externally, the FPGA receives and parses the command. The system first controls the operation of the internal selector switch, connecting the selected device signal to the acquisition system. Control information is then sent to the device under test, while the acquisition system monitors the power supply status of the device in real time. The collected data is then cached in the FPGA's internal random access memory (RAM) for processing. Finally, the collected data is transmitted back to an external monitor via the FPGA's on-chip first-in, first-out (FIFO) queue for real-time display. It is then judged and stored according to the corresponding rules to form a test data report.

[0046] The utility model adopts Xilinx's Spartan6 series FPGA as the core control device, realizes the functions of data acquisition control, data caching, data processing, data storage, data transmission and synchronous clock control, and has the characteristics of high precision, fast speed, good reliability, strong real-time performance and low cost. The 16-channel real-time, high-speed and high-precision synchronous data acquisition system with FPGA as the main processor has a sampling frequency of 200 kHz in actual monitoring projects. The FPGA is used to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous and high-speed acquisition functions required by the system.

[0047] like Figure 3As shown, the first signal conditioning module and the second signal conditioning module both include an amplifier circuit and a dual op amp bandpass filter, the amplifier circuit is composed of an OPA277 operational amplifier and a resistor and capacitor, and the dual op amp bandpass filter is composed of two OPA277 operational amplifiers. The circuits of the first signal conditioning module and the second signal conditioning module both specifically include a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein the signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power supply pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and the output pin of the first operational amplifier, the signal input +IN terminal is connected to one end of the second resistor, and the other end of the second resistor is respectively connected to the positive power supply pin of the first operational amplifier. , one end of the fourth resistor, one end of the second capacitor, the other end of the second capacitor is connected to the other end of the fourth resistor and grounded, the output pin of the first operational amplifier is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier, the negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier, the positive power supply pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier, the other end of the seventh resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

[0048] The signal conditioning module amplifies and filters the data before inputting it into the signal conversion circuit, significantly reducing signal noise and signal loss during measurement. The amplifier circuit, comprised of an OPA277 operational amplifier and resistors and capacitors, is a typical differential amplifier circuit. C3 and R6, and C4 and R7 form a low-pass filter, while two OPA277 operational amplifiers form a dual-op-amp bandpass filter. The bandpass filter's Q value and center frequency are adjustable. Adjusting R9 adjusts the circuit's resonant frequency, and adjusting R8 adjusts the circuit's Q value. Notably, after being output to the signal processing circuit, the signal is input into the AD7794 for digital-to-analog conversion, converting the analog signal into a digital signal. This facilitates long-distance wireless signal transmission. The 24-bit Σ-Δ analog-to-digital converter AD7794 boasts a noise level of only 40nV and consumes only 400μA, making it particularly suitable for applications requiring low power consumption and high-precision measurements.

[0049] Preferably, the data storage module uses ST's S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128 Mbit and establishes communication with an external controller via an SPI interface. The maximum clock frequency of the interface can reach 104 MHz.

[0050] The human-computer interaction module includes an input unit and an output unit, wherein the input unit is electrically connected to the output unit, and the input unit is electrically connected to the controller module.

[0051] The input unit includes a keyboard or a touch screen.

[0052] The output unit includes a display screen

[0053] like Figure 4 As shown, the power supply module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first electrolytic capacitor E1, a second electrolytic capacitor E2, a third electrolytic capacitor E3, a fourth electrolytic capacitor E4, a fifth electrolytic capacitor E5, a first switching power supply chip U1, a second switching power supply chip U2, a voltage regulator chip U3, a voltage input terminal, a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal;

[0054] The voltage input terminal is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to one end of the third capacitor C3, the anode of the first electrolytic capacitor E1, one end of the first resistor R1, and the pin 6 of the first switching power supply U1.

[0055] The other end of the first resistor R1 is connected to pin 7 of the first switching power supply chip U1, pin 8 of the first switching power supply chip U1, and pin 1 of the first switching power supply chip U1 respectively;

[0056] Pin 2 of the first switching power supply chip U1 is connected to the cathode of the second diode D2 and one end of the first inductor L1 respectively;

[0057] The other end of the first inductor L1 is respectively connected to the positive electrode of the first electrolytic capacitor E1, one end of the first capacitor C1 and the first voltage output end;

[0058] The other end of the first capacitor C1 is respectively connected to the cathode of the first electrolytic capacitor E1, the anode of the second diode D2, one end of the fourth capacitor C4, pin 4 of the first switching power supply chip U1, one end of the fifth resistor R5, the cathode of the third electrolytic capacitor E3 and the other end of the third capacitor C3;

[0059] The other end of the fourth capacitor C4 is connected to pin 3 of the first switching power supply chip U1;

[0060] The other end of the fifth resistor R5 is connected to the pin 5 of the first switching power supply chip U1 and one end of the third resistor R3 respectively;

[0061] The other end of the third resistor R3 is connected to the first voltage output end;

[0062] The other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, the positive electrode of the fourth electrolytic capacitor E4, one end of the second resistor R2, and pin 6 of the second switching power supply chip U2;

[0063] The other end of the second resistor R2 is connected to pin 7 of the second switching power supply chip U2, pin 8 of the second switching power supply chip U2, and pin 1 of the second switching power supply chip U2 respectively;

[0064] Pin 2 of the second switching power supply chip U2 is connected to the cathode of the second diode D3 and one end of the second inductor L2 respectively;

[0065] The other end of the second inductor L2 is respectively connected to the positive electrode of the second electrolytic capacitor E2, one end of the second capacitor C2, the second voltage output end and the pin 3 of the voltage stabilizing chip U3;

[0066] The other end of the second capacitor C2 is respectively connected to pin 1 of the voltage stabilizing chip U3, the negative electrode of the fifth capacitor E5, one end of the seventh capacitor C7, the negative electrode of the second electrolytic capacitor E2, the positive electrode of the third diode D3, one end of the sixth capacitor C6, pin 4 of the second switching power supply chip U2, one end of the sixth resistor R6, the negative electrode of the fourth electrolytic capacitor E4 and the other end of the fifth capacitor C5;

[0067] The other end of the sixth capacitor C6 is connected to pin 3 of the second switching power supply chip U2, the other end of the sixth resistor R6 is connected to pin 5 of the second switching power supply chip U2 and one end of the fourth resistor R4, respectively, and the other end of the fourth resistor R4 is connected to the second voltage output terminal;

[0068] The other end of the seventh capacitor C7 is respectively connected to the positive electrode of the electrolytic capacitor E5, the pin 2 of the voltage stabilizing chip U3, the pin 4 of the voltage stabilizing chip U3 and the third voltage output terminal.

[0069] This circuit is not only compact, highly efficient, accurately regulated, and has minimal interference, but it can also convert the input voltage into +12V, +5V, and +3.3V DC power via a first switching power supply, a second switching power supply, and a voltage regulator chip, providing +12V, +5V, and +3.3V DC voltages, capable of simultaneously powering multiple chips and circuits.

[0070] The chip models of the first switching power supply chip U1 and the second switching power supply are both MC33063.

[0071] The above description is only a preferred embodiment of the present invention. Therefore, any equivalent changes or modifications made according to the structure, features and principles described in the scope of the present invention patent application are included in the scope of the present invention patent application.

[0072] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which this invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless defined as such, will not be interpreted in an idealized or overly formal sense.

[0073] The above embodiments are only for the purpose of illustrating the technical concept of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications made based on the technical solution in accordance with the technical concept of the present invention shall fall within the scope of protection of the present invention. The above embodiments of the present invention are described in detail, but the present invention is not limited to the above embodiments. Various modifications can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. Intelligent substation automatic test system, characterized by: It includes a human-computer interaction module, an input-output module, a first signal conditioning module, a second signal conditioning module, a controller module, a wireless communication module, a clock module, a data storage module and a power supply module; the human-computer interaction module, the wireless communication module, the clock module, the data storage module and the power supply module are respectively connected to the controller module: the output end of the controller module is connected to the input end of the input-output module through the first signal conditioning module, and the output end of the input-output module is connected to the input end of the controller module; the controller module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a Flash data storage control unit, and a data interpretation unit; the AD acquisition control unit, the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the Flash data storage control unit, and the data interpretation unit are respectively connected to the data processing and RAM read-write module unit.

2. The intelligent substation automatic test system according to claim 1, characterized in that: The first signal conditioning module and the second signal conditioning module both include an amplifier circuit and a dual operational amplifier bandpass filter. The amplifier circuit is composed of an OPA277 operational amplifier and resistors and capacitors. The dual operational amplifier bandpass filter is composed of two OPA277 operational amplifiers.

3. The intelligent substation automatic test system according to claim 1, characterized in that: The data storage module uses ST's S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128Mbit and communicates with an external controller via an SPI interface. The maximum clock frequency of the interface can reach 104MHz.

4. The intelligent substation automatic test system according to claim 1, characterized in that: The human-computer interaction module includes an input unit and an output unit, wherein the input unit is electrically connected to the output unit, and the input unit is electrically connected to the controller module.

5. The intelligent substation automatic test system according to claim 4, characterized in that: The input unit includes a keyboard or a touch screen.

6. The intelligent substation automatic test system according to claim 4, characterized in that: The output unit includes a display screen.

7. The intelligent substation automatic test system according to claim 2, characterized in that: The circuits of the first signal conditioning module and the second signal conditioning module specifically include a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein the signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power supply pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and the output pin of the first operational amplifier, the signal input +IN terminal is connected to one end of the second resistor, and the other end of the second resistor is respectively connected to the positive power supply pin of the first operational amplifier. , one end of the fourth resistor, one end of the second capacitor, the other end of the second capacitor is connected to the other end of the fourth resistor and grounded, the output pin of the first operational amplifier is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the positive power supply pin of the second operational amplifier, the negative power supply pin of the second operational amplifier is connected to the negative power supply pin of the third operational amplifier, the positive power supply pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier, the other end of the seventh resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

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