Display panel and display device

Abstract

The utility model provides a display panel and a display device, and relates to the technical field of display. The display panel includes: a substrate; the plurality of pixel driving circuit columns are arranged along a first direction and are positioned on one side of the substrate; the pixel driving circuit column comprises a plurality of pixel driving circuits arranged along a second direction, and the first direction is crossed with the second direction; the pixel driving circuits in the pixel driving circuit column comprise a first pixel driving circuit and a second pixel driving circuit, and the first pixel driving circuit and the second pixel driving circuit drive light emitting units with different light emitting colors; a plurality of data lines extending along the second direction and arranged along the first direction; the data lines are connected with the first pixel driving circuits in the different pixel driving circuit columns, or the data lines are connected with the second pixel driving circuits in the different pixel driving circuit columns. According to the embodiment of the utility model, the power consumption of the source drive circuit is reduced.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, the same data line in a display panel needs to provide data signals to sub-pixel units of different colors, so that the source driving circuit in the display panel has high power consumption. Utility Model Content

[0003] The utility model provides a display panel and a display device, so as to reduce the power consumption of a source driving circuit.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising:

[0005] substrate;

[0006] A plurality of pixel driving circuit columns are arranged along a first direction and are located on one side of the substrate; the pixel driving circuit columns include a plurality of pixel driving circuits arranged along a second direction, the first direction intersecting the second direction; the pixel driving circuits in the pixel driving circuit columns include a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit driving light-emitting units of different luminous colors;

[0007] A plurality of data lines extend along the second direction and are arranged along the first direction; the data lines are connected to the first pixel driving circuits in different pixel driving circuit columns, or the data lines are connected to the second pixel driving circuits in different pixel driving circuit columns.

[0008] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the first aspect.

[0009] In the display panel provided by an embodiment of the present invention, first pixel drive circuits in different pixel drive circuit columns are connected to the same data line, and multiple first pixel drive circuits connected to the same data line have the same luminous color. Second pixel drive circuits in different pixel drive circuit columns are connected to the same data line. Multiple second pixel drive circuits connected to the same data line have the same luminous color. This ensures that multiple pixel drive circuits connected to the same data line have the same luminous color, reducing power consumption of the source driver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a top view of a display panel provided in an embodiment of the present utility model;

[0011] Figure 2A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0012] Figure 3 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0013] Figure 4 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0014] Figure 5 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0015] Figure 6 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0016] Figure 7 A schematic diagram of the circuit structure of a pixel driving circuit provided by an embodiment of the present utility model;

[0017] Figure 8 A schematic cross-sectional structure diagram of a pixel driving circuit provided by an embodiment of the present utility model;

[0018] Figure 9 A schematic cross-sectional view of a display panel provided in an embodiment of the present invention;

[0019] Figure 10 is a schematic structural diagram of a first semiconductor layer;

[0020] Figure 11 is a schematic structural diagram of a first metal layer;

[0021] Figure 12 is a schematic structural diagram of a first sub-gate metal layer;

[0022] Figure 13 is a schematic structural diagram of a second semiconductor layer;

[0023] Figure 14 is a schematic structural diagram of a second sub-gate metal layer;

[0024] Figure 15 is a schematic structural diagram of a second metal layer;

[0025] Figure 16 is a schematic structural diagram of a third metal layer;

[0026] Figure 17 Schematic diagram of the structure of an anode;

[0027] Figure 18 This is a schematic diagram of a film structure of a pixel driving circuit;

[0028] Figure 19 for Figure 18 A schematic diagram of the structure of part of the film layer of the pixel driving circuit;

[0029] Figure 20 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0030] Figure 21 is a schematic structural diagram of another first semiconductor layer;

[0031] Figure 22 is a schematic structural diagram of another second metal layer;

[0032] Figure 23 A schematic diagram of the structure of a portion of the film layer of another pixel driving circuit;

[0033] Figure 24 is a schematic structural diagram of another second metal layer;

[0034] Figure 25 A schematic diagram of the structure of a portion of the film layer of another pixel driving circuit;

[0035] Figure 26 A schematic cross-sectional view of another pixel driving circuit provided by an embodiment of the present utility model;

[0036] Figure 27 is a schematic structural diagram of another second metal layer;

[0037] Figure 28 is a schematic structural diagram of another third metal layer;

[0038] Figure 29 is a schematic structural diagram of a fourth metal layer;

[0039] Figure 30 A schematic diagram of the structure of a portion of the film layer of another pixel driving circuit;

[0040] Figure 31 is a schematic structural diagram of another second metal layer;

[0041] Figure 32 is a schematic structural diagram of another third metal layer;

[0042] Figure 33 A schematic diagram of the structure of a portion of the film layer of another pixel driving circuit;

[0043] Figure 34 is a schematic structural diagram of another second metal layer;

[0044] Figure 35 is a schematic structural diagram of another third metal layer;

[0045] Figure 36 A schematic diagram of the structure of a portion of the film layer of another pixel driving circuit;

[0046] Figure 37 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0047] Figure 38 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0048] Figure 39 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0049] Figure 40 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0050] Figure 41 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0051] Figure 42 A schematic diagram of a top view of another display panel provided by an embodiment of the present utility model;

[0052] Figure 43 A schematic diagram of a display device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all of its components.

[0054] In the related art, the data line connects multiple sub-pixels located in the same column, and the data line is used to provide data signals to the sub-pixels connected thereto. The source driver circuit is used to provide data signals to each data line. In addition, the source driver circuit can be connected to other driver chips through the main flexible circuit board and the connector. The same data line needs to provide data signals to the red sub-pixel and the blue sub-pixel respectively. The data signal voltage must be smaller than the data signal voltage required by the red sub-pixel. When the display panel scans row by row along the column direction, the voltage on the data line needs to jump between the data signal voltage required by the red sub-pixel and the data signal voltage required by the blue sub-pixel. Larger voltage fluctuations on the data line will increase the power consumption of the source driver circuit.

[0055] Figure 1 A schematic diagram of a top view of a display panel provided by an embodiment of the present invention, referring to Figure 1The display panel includes a substrate 200 and a plurality of pixel driving circuit columns 100. The plurality of pixel driving circuit columns 100 are located on one side of the substrate 200. The plurality of pixel driving circuit columns 100 are arranged along a first direction X. The pixel driving circuit columns 100 extend along a second direction Y. The pixel driving circuit columns 100 include a plurality of pixel driving circuits 110 arranged along a second direction. The first direction X intersects the second direction Y. The pixel driving circuits 110 in the pixel driving circuit columns 100 include a first pixel driving circuit 111 and a second pixel driving circuit 112. The first pixel driving circuit 111 and the second pixel driving circuit 112 drive light-emitting units 130 of different luminous colors.

[0056] Exemplarily, the display panel includes multiple light-emitting units 130. The display panel displays a specific image by controlling the brightness of the light-emitting units 130. The multiple light-emitting units 130 include a first light-emitting unit 131 and a second light-emitting unit 132. The first light-emitting unit 131 is electrically connected to the first pixel driving circuit 111, which drives the first light-emitting unit 131. The second light-emitting unit 132 is electrically connected to the second pixel driving circuit 112, which drives the second light-emitting unit 132.

[0057] The first light emitting unit 131 and the second light emitting unit 132 have different light emitting colors.

[0058] Figure 2 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 1 and Figure 2 The display panel includes a plurality of data lines 120. The plurality of data lines 120 extend along the second direction Y and are arranged along the first direction X. The data lines 120 are configured to transmit data signals and write the data signals into the pixel driving circuits 110 electrically connected to the data lines 120. The data lines 120 are connected to the first pixel driving circuits 111 in different pixel driving circuit columns 100, or the data lines 120 are connected to the second pixel driving circuits 112 in different pixel driving circuit columns 100.

[0059] In the display panel provided by the embodiment of the present invention, the first pixel driving circuits 111 in different pixel driving circuit columns 100 are connected to the same data line 120, and the multiple first pixel driving circuits 111 connected to the same data line 120 have the same luminous color. The second pixel driving circuits 112 in different pixel driving circuit columns 100 are connected to the same data line 120. The multiple second pixel driving circuits 112 connected to the same data line 120 have the same luminous color. This ensures that the multiple pixel driving circuits 110 connected to the same data line 120 have the same luminous color, thereby reducing the power consumption of the source driver circuit.

[0060] For example, refer to Figure 1 and Figure 2 , the pixel driving circuit column 100 includes a first pixel driving circuit column 101 and a second pixel driving circuit column 102. Along the first direction X, the first pixel driving circuit column 101 and the second pixel driving circuit column 102 are arranged alternately. The first pixel driving circuit column 101 includes a first pixel driving circuit 111 and a second pixel driving circuit 112. The pixel driving circuit 110 in the second pixel driving circuit column 102 includes a third pixel driving circuit 113. The third pixel driving circuit 113 drives light-emitting units 130 of different luminous colors together with the first pixel driving circuit 111 and the second pixel driving circuit 112. The light-emitting unit 130 also includes a third light-emitting unit 133. The first light-emitting unit 131, the second light-emitting unit 132, and the third light-emitting unit 133 have different luminous colors. Along the first direction X, the third pixel driving circuit 113 is arranged between adjacent first pixel driving circuits 111 and second pixel driving circuits 112. Along the second direction Y, the first pixel driving circuit 111 and the second pixel driving circuit 112 are arranged alternately. In other embodiments, the display panel may also have other arrangements of pixel driving circuits.

[0061] A pixel drive circuit arrangement can correspond to one or more light-emitting unit arrangements. In other words, when a pixel drive circuit arrangement is determined, the pixel drive circuit in that arrangement can be used to drive light-emitting units in one or more arrangements.

[0062] In one embodiment, the first light emitting unit 131 emits blue light, the second light emitting unit 132 emits red light, and the third light emitting unit 133 emits green light. In other embodiments, the first light emitting unit 131, the second light emitting unit 132, and the third light emitting unit 133 can also be configured to emit other color combinations.

[0063] Optionally, refer to Figure 2, the multiple data lines 120 include a first data line 121 and a second data line 122. The first data line 121 is electrically connected to the first pixel driving circuit 111. The first data line 121 includes the n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit 111 in the n+2th pixel driving circuit column. The second data line 122 is electrically connected to the second pixel driving circuit 112. The second data line 122 includes the n+4th data line, and the n+4th data line is electrically connected to the n+2th pixel driving circuit column and the second pixel driving circuit 112 in the n+4th pixel driving circuit column, where n is a positive integer. In an embodiment of the present utility model, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 are connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 are connected to the second data line 122 at the location of the current pixel driving circuit column 100 .

[0064] For example, refer to Figure 2 The plurality of first data lines 121 include an n+2th data line and an n+6th data line. The n+6th data line is electrically connected to the n+4th pixel driving circuit column and the first pixel driving circuit 111 in the n+6th pixel driving circuit column. The plurality of second data lines 122 include an nth data line and an n+4th data line. The second data line 122 is electrically connected to the second pixel driving circuit 112 in the nth pixel driving circuit column.

[0065] Along the first direction X, two data lines 120 are arranged between two adjacent pixel drive circuit columns 100. The plurality of data lines 120 include a first data line 121, a second data line 122, and a third data line 123. The third data line 123 is electrically connected to the third pixel drive circuit 113 in the second pixel drive circuit column 102. The first data line 121 is located between two adjacent third data lines 123, and the second data line 122 is located between two adjacent third data lines 123. The plurality of third data lines 123 include an n+1th data line, an n+3th data line, an n+5th data line, and an n+7th data line. The n+1th data line is electrically connected to the third pixel drive circuit 113 in the n+1th pixel drive circuit column. The n+3th data line is electrically connected to the third pixel drive circuit 113 in the n+3th pixel drive circuit column. The n+5th data line is electrically connected to the third pixel drive circuit 113 in the n+5th pixel drive circuit column. The (n+7)th data line is electrically connected to the third pixel driving circuit 113 in the (n+7)th pixel driving circuit column.

[0066] Figure 3This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 3 The display panel further includes a first additional data line 210. The first additional data line 210 is located on a side of the (n+4)th data line away from the (n+2)th data line. The first additional data line 210 is connected to the first pixel driving circuit 111 or the second pixel driving circuit 112 in the last pixel driving circuit column 100. Thus, the first additional data line 210 provides a data signal to the first pixel driving circuit 111 or the second pixel driving circuit 112 in the last pixel driving circuit column 100.

[0067] For example, refer to Figure 3 The plurality of data lines 120 and the first additional data line 210 are arranged along the first direction X. The first additional data line 210 is located on a side of each data line 120 facing the first direction X. The first additional data line 210 and the data line 120 can be provided in the same layer or in different layers. The first additional data line 210 can be provided in the display area or the non-display area.

[0068] It is understood that the number of pixel driving circuits 110 connected to the first additional data line 210 and the first data line 120 is less than the number of pixel driving circuits 110 connected to the second through last data lines 120. To balance the loads of the first additional data line 210, the first data line 120, and the second through last data lines 120, an additional load may be connected to the first additional data line 210 and the first data line 120. For example, a dummy pixel driving circuit may be connected to the first additional data line 210 and the first data line 120.

[0069] Figure 4 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 4 , the multiple data lines 120 include a first data line 121 and a second data line 122. The first data line 121 includes the n+2th data line, and the n+2th data line is electrically connected to the first pixel driving circuit 111 in the n+2th pixel driving circuit column and the n+4th pixel driving circuit column. The second data line 122 includes the nth data line, and the nth data line is electrically connected to the second pixel driving circuit 112 in the nth pixel driving circuit column and the n+2th pixel driving circuit column, where n is a positive integer. In an embodiment of the present utility model, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the second data line 122 at the position of the current pixel driving circuit column 100.

[0070] Figure 5 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 5 The display panel further includes a second additional data line 220. The second additional data line 220 is located on a side of the nth data line away from the (n+2)th data line. The second additional data line 220 is connected to the first pixel driving circuit 111 or the second pixel driving circuit 112 in the first pixel driving circuit column 100. Thus, the second additional data line 220 provides a data signal to the first pixel driving circuit 111 or the second pixel driving circuit 112 in the first pixel driving circuit column 100.

[0071] For example, refer to Figure 5 The second additional data line 220 and the plurality of data lines 120 are arranged along the first direction X. The second additional data line 220 is located on a side of the data lines 120 that faces the opposite direction of the first direction X. The second additional data line 220 and the data lines 120 can be arranged in the same layer or in different layers. The second additional data line 220 can be arranged in the display area or the non-display area.

[0072] It is understood that the number of pixel driving circuits 110 connected to the second additional data line 220 and the last data line 120 is less than the number of pixel driving circuits 110 connected to the first through second-to-last data lines 120. To balance the loads on the second additional data line 220, the last data line 120, and the first through second-to-last data lines 120, additional loads may be connected to the second additional data line 220 and the last data line 120. For example, dummy pixel driving circuits may be connected to the second additional data line 220 and the last data line 120.

[0073] Figure 6 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 6, the multiple data lines 120 include a first data line 121 and a second data line 122. The first data line 121 includes the n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit 111 in the n+2th pixel driving circuit column. The second data line 122 includes the nth data line, and the nth data line is electrically connected to the nth pixel driving circuit column and the second pixel driving circuit 112 in the n+2th pixel driving circuit column, where n is a positive integer. In an embodiment of the present invention, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 is connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the second data line 122 at the position of the current pixel driving circuit column 100.

[0074] Figure 7 A schematic diagram of a pixel driving circuit according to an embodiment of the present invention is provided. Figure 7The pixel driving circuit 110 includes a power write transistor T1, a data write transistor T2, a drive transistor T3, a compensation transistor T4, a first reset transistor T5, a light emission control transistor T6, a second reset transistor T7, a regulation transistor T8, and a storage capacitor C. A first electrode of the power write transistor T1 is electrically connected to the first power line VDD, a second electrode of the power write transistor T1 is electrically connected to the second node N2, and a gate of the power write transistor T1 is electrically connected to the light emission control signal line EM. A first electrode of the data write transistor T2 is electrically connected to the second node N2, a second electrode of the data write transistor T2 is electrically connected to the data line 120, and a gate of the data write transistor T2 is electrically connected to the first scan line SP. A first electrode of the drive transistor T3 is electrically connected to the second node N2, a second electrode of the drive transistor T3 is electrically connected to the third node N3, and a gate of the drive transistor T3 is electrically connected to the first node N1. A first electrode of the compensation transistor T4 is electrically connected to the first node N1, a second electrode of the compensation transistor T4 is electrically connected to the third node N3, and a gate of the compensation transistor T4 is electrically connected to the second scan control line SN2. A first electrode of the first reset transistor T5 is electrically connected to the first reset signal transmission line VR1, a second electrode of the first reset transistor T5 is electrically connected to the first node N1, and a gate of the first reset transistor T5 is electrically connected to the first scan control line SN1. A first electrode of the emission control transistor T6 is electrically connected to the third node N3, a second electrode of the emission control transistor T6 is electrically connected to the fourth node N4, and a gate of the emission control transistor T6 is electrically connected to the emission control signal line EM. A first electrode of the second reset transistor T7 is electrically connected to the second reset signal transmission line VR2, a second electrode of the second reset transistor T7 is electrically connected to the fourth node N4, and a gate of the second reset transistor T7 is electrically connected to the second scan line SPX. A first electrode of the regulation transistor T8 is electrically connected to the regulation signal transmission line DVH, a second electrode of the regulation transistor T8 is electrically connected to the second node N2, and a gate of the regulation transistor T8 is electrically connected to the second scan line SPX. A first plate C1 of the storage capacitor C is electrically connected to the first node N1, and a second plate C2 of the storage capacitor C is electrically connected to the first power supply line VDD.

[0075] The first node N1 , the second node N2 , the third node N3 and the fourth node N4 may be virtually existing connection nodes, or may be actually existing connection nodes.

[0076] It should be noted that if Figure 7 The circuit diagram shown is only an example and does not limit the present invention. In other implementations, the pixel driving circuit 110 may have other circuit structures.

[0077] Figure 8 A schematic cross-sectional view of a pixel driving circuit according to an embodiment of the present invention is provided. Figure 7 and Figure 8 The display panel includes a first semiconductor layer POLY, a first metal layer M1, a first sub-gate metal layer MC, a second semiconductor layer IGZO, a second sub-gate metal layer MG, a second metal layer M2, and a third metal layer M3, stacked in sequence. The first semiconductor layer POLY is located between the substrate 200 and the first metal layer M1. The first semiconductor layer POLY comprises silicon. The second semiconductor layer IGZO comprises an oxide semiconductor material.

[0078] The multiple thin-film transistors 21 include a silicon transistor 211 and an oxide transistor 212. The silicon transistor 211 includes a gate 201, a first channel layer 2021, a source 203, and a drain 204. The gate 201 of the silicon transistor 211 is located in the first metal layer M1, the first channel layer 2021 of the silicon transistor 211 is located in the first semiconductor layer POLY, and the source 203 and drain 204 of the silicon transistor 211 are both located in the second metal layer M2. The oxide transistor 212 includes a gate 201, a second channel layer 2022, a source 203, and a drain 204. The gate 201 of the oxide transistor 212 includes a first sub-gate 2011 and a second sub-gate 2012. Perpendicular to the substrate 200, the first sub-gate 2011 is located between the second channel layer 2022 and the substrate 200, and the second sub-gate 2012 is located on the side of the second channel layer 2022 away from the substrate 200. The second channel layer 2022 of the oxide transistor 212 is located in the second semiconductor layer IGZO. The source 203 and the drain 204 of the oxide transistor 212 are both located in the second metal layer M2.

[0079] Exemplarily, the power write transistor T1, the data write transistor T2, the drive transistor T3, the emission control transistor T6, the second reset transistor T7, and the adjustment transistor T8 are silicon transistors 211. The compensation transistor T4 and the first reset transistor T5 are oxide transistors 212. Since both the compensation transistor T4 and the first reset transistor T5 are connected to the first node N1, setting the compensation transistor T4 and the first reset transistor T5 as oxide transistors 212 can reduce leakage current to the first node N1.

[0080] Figure 9 A schematic cross-sectional view of a display panel according to an embodiment of the present invention is provided. Figure 7-Figure 9 The light-emitting unit 130 is electrically connected to the pixel driving circuit 20 and is configured to emit light under the drive of the pixel driving circuit 20. The light-emitting unit 130 includes an anode RE, a light-emitting functional layer 84, and a cathode COM. The light-emitting functional layer 84 is located between the anode RE and the cathode COM. The light-emitting functional layer 84 can include an organic light-emitting material and / or an inorganic light-emitting material. The film layer where the anode RE is located is located on the side of the third metal layer M3 away from the substrate 200.

[0081] The pixel driving circuit 110 is formed by stacking patterned film layers, and various signal lines are also distributed in the film layers. Figures 10 to 17 An exemplary structure of a single film layer is given in sequence, wherein: Figure 10 is a schematic structural diagram of a first semiconductor layer, Figure 11 is a structural schematic diagram of a first metal layer, Figure 12 is a schematic structural diagram of a first sub-gate metal layer, Figure 13 is a schematic structural diagram of a second semiconductor layer. Figure 14 is a schematic structural diagram of a second sub-gate metal layer, Figure 15 is a structural diagram of a second metal layer, Figure 16 is a schematic structural diagram of a third metal layer. Figure 17 A schematic diagram of the structure of an anode.

[0082] refer to Figure 8 、 Figure 10 and Figure 11 The region where the semiconductor traces in the first semiconductor layer POLY overlap with the signal lines in the first metal layer M1 forms the first channel layer 2021 of the silicon transistor 211. The first metal layer M1 includes the second scan line SPX, the emission control signal line EM, the first scan line SP, and the first plate C1 of the storage capacitor C. The first plate C1 of the storage capacitor C also serves as the gate of the drive transistor T3. The second scan line SPX, the emission control signal line EM, and the first scan line SP extend along the first direction X and are arranged along the second direction Y. The intersection of the semiconductor traces in the first semiconductor layer POLY and the second scan line SPX forms the second reset transistor T7 and the regulation transistor T8. The intersection of the semiconductor traces in the first semiconductor layer POLY and the emission control signal line EM forms the power write transistor T1 and the emission control transistor T6.

[0083] refer to Figure 8 、 Figure 12 and Figure 13The first sub-gate metal layer MC includes a second electrode plate C2 of the storage capacitor C. The second electrode plate C2 and the first electrode plate C1 are arranged opposite each other to form the storage capacitor C. The region where the semiconductor trace in the second semiconductor layer IGZO overlaps with the signal line in the first sub-gate metal layer MC forms the second channel layer 2022 of the oxide transistor 212. The first scan control line SN1 includes a first sub-first scan control line SN11. The second scan control line SN2 includes a first sub-second scan control line SN21. The first sub-first scan control line SN11 and the first sub-second scan control line SN21 are located in the first sub-gate metal layer MC. The location where the semiconductor trace in the second semiconductor layer IGZO overlaps with the first scan control line SN1 forms the first reset transistor T5. The location where the semiconductor trace in the second semiconductor layer IGZO overlaps with the second scan control line SN2 forms the compensation transistor T4. The first sub-second scan control line SN21 serves as the bottom gate of the compensation transistor T4, and the first sub-second scan control line SN21 serves as the bottom gate of the first reset transistor T5.

[0084] To reduce the impedance of the first power line VDD, the first power line VDD is often provided in multiple film layers, and the first power lines VDD in these different film layers are electrically connected. The first power line VDD includes a first sub-first power line VDD1. The second plate C2 of the storage capacitor C is electrically connected to the first sub-first power line VDD1 provided in the same layer. Similarly, to reduce impedance, the first reset signal transmission line VR1 and the second reset signal transmission line VR2 are often provided in multiple film layers. The first reset signal transmission line VR1 includes a first sub-first reset signal transmission line VR11. The second reset signal transmission line VR2 includes a first sub-second reset signal transmission line VR21. The first sub-first power line VDD1, the first sub-first reset signal transmission line VR11, and the first sub-second reset signal transmission line VR21 are located in the first sub-gate metal layer MC. The first sub-first scan control line SN11, the first sub-second scan control line SN21, the first sub-first power line VDD1, the first sub-first reset signal transmission line VR11, and the first sub-second reset signal transmission line VR21 extend along the first direction X and are arranged along the second direction Y.

[0085] refer to Figure 8 、 Figure 12 、 Figure 13 and Figure 14The first scan control line SN1 includes a second sub-first scan control line SN12. The second scan control line SN2 includes a second sub-second scan control line SN22. The second sub-first scan control line SN12 and the second sub-second scan control line SN22 are located on the second sub-gate metal layer MG. Perpendicular to the substrate 200, the second sub-first scan control line SN12 overlaps with the first sub-first scan control line SN11, and the second sub-second scan control line SN22 overlaps with the first sub-second scan control line SN21. The second sub-second scan control line SN22 serves as the top gate of the compensation transistor T4 and the second sub-second scan control line SN22 serves as the top gate of the first reset transistor T5.

[0086] In order to reduce the impedance on the adjustment signal transmission line DVH, the adjustment signal transmission line DVH is often provided in multiple film layers, and the adjustment signal transmission lines DVH of these different film layers are electrically connected. The adjustment signal transmission line DVH includes a first adjustment signal transmission line DVH1, which is located in the second sub-gate metal layer MG. The second sub-gate metal layer MG also includes a shielding component 40. Figure 12 and Figure 14 The shielding member 40 is electrically connected to the first sub-first power line VDD1 through a via. The shielding member 40 is configured to apply a DC voltage signal provided on the first power line VDD. This prevents the light emission control scanning signal on the light emission control signal line EM from coupling with the potential of the first electrode of the driving transistor T3, thereby improving display uniformity.

[0087] The first adjustment signal transmission line DVH1 , the second sub-first scan control line SN12 , and the second sub-second scan control line SN22 extend along the first direction X and are arranged along the second direction Y.

[0088] refer to Figure 8 and Figure 15 The second reset signal transmission line VR2 includes a second sub-second reset signal transmission line VR22. The second sub-second reset signal transmission line VR22 is located in the second metal layer M2. The second sub-second reset signal transmission line VR22 extends along the first direction X and is electrically connected to the first sub-second reset signal transmission line VR21 through a via.

[0089] refer to Figure 8 and Figure 16The first reset signal transmission line VR1 includes a second sub-first reset signal transmission line VR12. The second reset signal transmission line VR2 includes a third sub-second reset signal transmission line VR23. The first power line VDD includes a second sub-first power line VDD2, and the adjustment signal transmission line DVH includes a second adjustment signal transmission line DVH2. The second sub-first reset signal transmission line VR12, the third sub-second reset signal transmission line VR23, the second sub-first power line VDD2, and the second adjustment signal transmission line DVH2 are located on the third metal layer M3. The second sub-first reset signal transmission line VR12, the third sub-second reset signal transmission line VR23, the second sub-first power line VDD2, and the second adjustment signal transmission line DVH2 extend along the second direction Y and are arranged along the first direction X.

[0090] The second sub-first reset signal transmission line VR12 intersects the extension direction of the first sub-first reset signal transmission line VR11 and is electrically connected to form a conductive mesh. The third sub-second reset signal transmission line VR23 intersects the extension direction of the second sub-second reset signal transmission line VR22 and the first sub-second reset signal transmission line VR21 and is electrically connected to form a conductive mesh. The second sub-first power supply line VDD2 intersects the extension direction of the first sub-first power supply line VDD1 and is electrically connected to form a conductive mesh. The second adjustment signal transmission line DVH2 intersects the extension direction of the first adjustment signal transmission line DVH1 and is electrically connected to form a conductive mesh.

[0091] The third metal layer M3 further includes a data line 120. The third metal layer M3 includes a first data line 121, a second data line 122, and a third data line 123.

[0092] refer to Figure 8 、 Figure 9 、 Figure 10 and Figure 17 The second electrode of the light emitting control transistor T6 is connected to the second metal layer M2 through the first semiconductor layer POLY through a via hole, connected to the third metal layer M3 through the second metal layer M2 through a via hole, and connected to the anode RE of the light emitting unit 130 through the third metal layer M3 through a via hole.

[0093] Figure 18 This is a schematic diagram of the film structure of a pixel driving circuit. Figure 18 The pixel driving circuit shown in Figures 10 to 16 The single film layers shown are stacked layer by layer, corresponding to Figure 6 The simplified circuit shown. Figure 19 for Figure 18 Schematic diagram of the structure of some film layers of the pixel driving circuit, Figure 19 The first semiconductor layer POLY, the second metal layer M2 and the third metal layer M3 are schematically shown, and other film layers are not shown.

[0094] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 The display panel further includes a connecting line 140, which extends along a first direction X. The connecting line 140 and the data line 120 are arranged in different layers. The connecting line 140 and the data line 120 are arranged in different film layers and are electrically connected through vias. The connecting line 140 connects the data line 120 to the first pixel driving circuit 111, or the connecting line 140 connects the data line 120 to the second pixel driving circuit 112. The data line 120 at the current pixel driving circuit column 100 is connected to the first pixel driving circuit 111 or the second pixel driving circuit 112 in other pixel driving circuit columns 100 through the connecting line 140.

[0095] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 The plurality of data lines 120 include a first data line 121 and a second data line 122. The plurality of connection lines 140 include a first connection line 141 and a second connection line 142. The first connection line 141 connects the first data line 121 to the first pixel driving circuit 111, and the second connection line 142 connects the second data line 122 to the second pixel driving circuit 112. The first data line 121 at the current pixel driving circuit column 100 is connected to the first pixel driving circuit 111 in the other pixel driving circuit columns 100 via the first connection line 141. The second data line 122 at the current pixel driving circuit column 100 is connected to the second pixel driving circuit 112 in the other pixel driving circuit columns 100 via the second connection line 142.

[0096] For example, refer to Figure 6 The n+2th data line is electrically connected to the first pixel driving circuit 111 in the nth pixel driving circuit column through the first connecting line 141. The nth data line is electrically connected to the second pixel driving circuit 112 in the n+2th pixel driving circuit column through the second connecting line 142.

[0097] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 , multiple pixel driving circuits 110 form a pixel driving circuit row 300 along the first direction X. The first connecting line 141 and the second connecting line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are located on the same side of the pixel driving circuit row 300. The first connecting line 141 and the second connecting line 142 are arranged on the same side of the pixel driving circuit row 300, so that only one side of the pixel driving circuit row 300 needs to be changed to the original layout, which reduces the modification of the original layout and reduces the difficulty of designing and manufacturing the pixel driving circuit 110.

[0098] For example, refer to Figure 6 The first connection line 141 and the second connection line 142 connected to the second pixel driving circuit row 300 are arranged between the second pixel driving circuit row 300 and the third pixel driving circuit row 300. The first connection line 141 and the second connection line 142 connected to the fourth pixel driving circuit row 300 are arranged on a side of the fourth pixel driving circuit row 300 away from the second direction Y.

[0099] Figure 20 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 20 The first connection line 141 and the second connection line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are located on opposite sides of the pixel driving circuit row 300. For example, the first connection line 141 connected to the second pixel driving circuit row 300 is arranged between the second pixel driving circuit row 300 and the third pixel driving circuit row 300. The second connection line 142 connected to the second pixel driving circuit row 300 is arranged between the second pixel driving circuit row 300 and the first pixel driving circuit row 300.

[0100] Figure 21 is a schematic structural diagram of another first semiconductor layer, Figure 22 is a schematic diagram of the structure of another second metal layer, Figure 23 This is a schematic diagram of the structure of part of the film layer of another pixel driving circuit. Figure 23 The first semiconductor layer POLY, the second metal layer M2 and the third metal layer M3 are schematically shown, and other film layers are not shown. Figure 23 The first semiconductor layer POLY in Figure 21 As shown, Figure 23 The second metal layer M2 in Figure 22 The remaining film layers not shown (such as the first metal layer, the third metal layer, etc.) can be referred to Figures 10 to 17 . Figure 23 The pixel driving circuit shown corresponds to Figure 2 The simplified circuit shown.

[0101] Optionally, refer to Figure 2 、 Figure 22 and Figure 23The direction in which the end of the first connecting line 141 is away from the first data line 121 is the same as the direction in which the end of the second connecting line 142 is away from the second data line 122. Taking the first data line 121 as a reference, after the first connecting line 141 is electrically connected to the first data line 121, it extends in a direction away from the first connecting line 141. Taking the second data line 122 as a reference, after the second connecting line 142 is electrically connected to the second data line 122, it extends in a direction away from the second connecting line 142. The first connecting line 141 and the second connecting line 142 are arranged in the same direction. For example, the first connecting line 141 and the second connecting line 142 are both arranged in a direction opposite to the first direction. The first connecting lines 141 and the second connecting lines 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are arranged alternately along the first direction X. Along the first direction X, one second connecting line 142 is arranged between two first connecting lines 141, and one first connecting line 141 is arranged between two second connecting lines 142.

[0102] For example, refer to Figure 2 、 Figure 22 and Figure 23 , along the first direction X, the first data lines 121 and the second data lines 122 are arranged alternately. The first connection lines 141 and the second connection lines 142 are arranged in the same direction. Corresponding to the arrangement of the alternating arrangement of the data lines 120, the first connection lines 141 and the second connection lines 142 are arranged alternately along the first direction X. The first connection lines 141 and the second connection lines 142 are arranged in the same area. Along the first direction X, the two sub-pixel areas 400 ( Figure 22 and Figure 23 The diagram shows 18 sub-pixel regions 400 arranged in 3 rows and 6 columns as a sub-pixel region group. The first connection line 141 and the second connection line 142 are arranged in different sub-pixel region groups. Along the first direction X, each sub-pixel region group is provided with a first connection line 141 or a second connection line 142.

[0103] Optionally, refer to Figure 2 、 Figure 22 and Figure 23 The first connection line 141 and the second connection line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are collinearly arranged. The main portion of the first connection line 141 and the main portion of the second connection line 142 are arranged on the same straight line. The first connection line 141 and the second connection line 142 are arranged at the same position relative to the sub-pixel area 400. As a result, the first connection line 141 and the second connection line 142 have similar or identical coupling effects on each node or thin film transistor 21 in the pixel driving circuit 110.

[0104] For example, refer to Figure 2 、 Figure 22 and Figure 23 The first connection line 141 includes a first connection line main portion 1411 and a first connection line bend portion 1412 connected to each other. The first end of the first connection line main portion 1411 is electrically connected to the first data line 121, and the second end of the first connection line main portion 1411 is electrically connected to the first end of the first connection line bend portion 1412. The second end of the first connection line bend portion 1412 is electrically connected to the first pixel driving circuit 111. The length of the first connection line main portion 1411 is greater than the length of the first connection line bend portion 1412. The first connection line main portion 1411 is the portion of the first connection line 141 that extends along the first direction X. The first connection line bend portion 1412 intersects the extension direction of the first connection line main portion 1411. In the same sub-pixel area 400, along the second direction Y, the first connection line main portion 1411 is located on the side of the first connection line bend portion 1412 away from the driving transistor T3.

[0105] The second connection line 142 includes a second connection line main portion 1421 and a second connection line bend portion 1422. The first end of the second connection line main portion 1421 is electrically connected to the second data line 122, and the second end of the second connection line main portion 1421 is electrically connected to the first end of the second connection line bend portion 1422. The second end of the second connection line bend portion 1422 is electrically connected to the second pixel driving circuit 112. The length of the second connection line main portion 1421 is greater than the length of the second connection line bend portion 1422. The second connection line main portion 1421 is the portion of the second connection line 142 that extends along the first direction X. The second connection line bend portion 1422 intersects the extension direction of the second connection line main portion 1421. In the same sub-pixel region 400, along the second direction Y, the second connection line main portion 1421 is located on the side of the second connection line bend portion 1422 away from the driving transistor T3.

[0106] Along the first direction X, the first connecting line main portion 1411 and the second connecting line main portion 1421 are arranged collinearly. The first connecting line main portion 1411 and the second connecting line main portion 1421 are arranged on the same straight line. Along the first direction X, the first connecting line bent portion 1412 and the second connecting line bent portion 1422 overlap. The projections of the first connecting line bent portion 1412 and the second connecting line bent portion 1422 along the first direction X overlap. As a feasible embodiment, the first connecting line bent portion 1412 and the second connecting line bent portion 1422 are arranged in parallel on the same layer.

[0107] The first connecting wire 141 and the second connecting wire 142 are located in the same film layer and extend along the first direction X. The first connecting wire bend 1412 is disposed away from the adjacent second connecting wire main body 1421. The second connecting wire bend 1422 is disposed away from the adjacent first connecting wire main body 1411. This prevents short circuiting between the first connecting wire 141 and the second connecting wire 142.

[0108] Figure 24 is a schematic diagram of the structure of another second metal layer, Figure 25 This is a schematic diagram of the structure of part of the film layer of another pixel driving circuit. Figure 25 The first semiconductor layer POLY, the second metal layer M2 and the third metal layer M3 are schematically shown, and other film layers are not shown. Figure 25 The second metal layer M2 in Figure 24 The remaining film layers not shown (such as the first metal layer, the third metal layer, etc.) can be referred to Figures 10 to 17 . Figure 25 The pixel driving circuit shown corresponds to Figure 4 The simplified circuit shown.

[0109] Optionally, refer to Figure 4 、 Figure 24 and Figure 25 The direction in which the end of the first connecting line 141 is away from the first data line 121 is the same as the direction in which the end of the second connecting line 142 is away from the second data line 122. Taking the first data line 121 as a reference, the first connecting line 141 is electrically connected to the first data line 121 and then extends in a direction away from the first connecting line 141. Taking the second data line 122 as a reference, the second connecting line 142 is electrically connected to the second data line 122 and then extends in a direction away from the second connecting line 142. The first connecting line 141 and the second connecting line 142 are arranged in the same direction. Both the first connecting line 141 and the second connecting line 142 are arranged in the first direction X.

[0110] In some embodiments, the data line 120 and other traces may be disposed in a film layer above the third metal layer M3. The process of disposing the data line 120 and other traces in the third metal layer M3 is called a 2SD process. Figure 26 A schematic cross-sectional view of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 26 The display panel also includes a fourth metal layer M4, which is located between the third metal layer M3 and the film layer containing the anode RE. Data lines 120 and other traces are disposed in the fourth metal layer M4. The process of disposing data lines 120 and other traces in the fourth metal layer M4 is called a 3SD process.

[0111] refer to Figure 15In the 2SD process, the second sub-second reset signal transmission line VR22 is set in the second metal layer M2. Figure 27 This is a schematic diagram of the structure of another second metal layer, refer to Figure 15 and Figure 27 Since the second metal layer M2 is provided with a large number of vias and bridges, the wiring space in the second metal layer M2 is relatively small. Figure 27 In the illustrated 3SD process, the second sub-second reset signal transmission line VR22 is removed from the second metal layer M2. The second sub-second reset signal transmission line VR22 is disposed in a film layer above the second metal layer M2. A bridge trace is a trace that acts as a bridge to avoid overlapping traces.

[0112] Figure 28 This is a schematic diagram of the structure of another third metal layer, refer to Figure 28 The third metal layer M3 includes a second sub-second reset signal transmission line VR22. The second sub-second reset signal transmission line VR22 extends along the first direction X.

[0113] Figure 29 is a schematic diagram of the structure of the fourth metal layer, refer to Figure 29 The fourth metal layer M4 includes a second sub-first reset signal transmission line VR12, a third sub-second reset signal transmission line VR23, a second sub-first power line VDD2, and a second adjustment signal transmission line DVH2. The second sub-first reset signal transmission line VR12, the third sub-second reset signal transmission line VR23, the second sub-first power line VDD2, and the second adjustment signal transmission line DVH2 extend along the second direction Y and are arranged along the first direction X.

[0114] The fourth metal layer M4 further includes a data line 120. The fourth metal layer M4 includes a first data line 121, a second data line 122, and a third data line 123.

[0115] Figure 30 This is a schematic diagram of the structure of part of the film layer of another pixel driving circuit. Figure 30 Schematically shows a first semiconductor layer POLY, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4, and other film layers are not shown. Figure 30 The second metal layer M2 in Figure 27 shown. Figure 30 The third metal layer M3 in Figure 28 shown. Figure 30 The fourth metal layer M4 in Figure 29 The remaining film layers not shown (such as the first metal layer, the first semiconductor layer, etc.) can be referred to Figures 10 to 17 . Figure 30 The pixel driving circuit shown corresponds to Figure 6The simplified circuit shown.

[0116] Figure 31 is a schematic diagram of the structure of another second metal layer, Figure 32 is a schematic diagram of the structure of another third metal layer, Figure 33 This is a schematic diagram of the structure of part of the film layer of another pixel driving circuit. Figure 33 Schematically shows a first semiconductor layer POLY, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4, and other film layers are not shown. Figure 33 The second metal layer M2 in Figure 31 As shown, Figure 33 The third metal layer M3 in Figure 32 shown. Figure 33 The pixel driving circuit shown corresponds to Figure 2 The simplified circuit shown.

[0117] Optionally, refer to Figure 2 、 Figure 32 and Figure 33 The direction in which the end of the first connecting line 141 is away from the first data line 121 is the same as the direction in which the end of the second connecting line 142 is away from the second data line 122. The first connecting line 141 and the second connecting line 142 are arranged in the same direction. The first connecting line 141 and the second connecting line 142 are both arranged in the opposite direction of the first direction X.

[0118] Figure 34 is a schematic diagram of the structure of another second metal layer, Figure 35 is a schematic diagram of the structure of another third metal layer, Figure 36 This is a schematic diagram of the structure of part of the film layer of another pixel driving circuit, refer to Figure 36 ,exist Figure 36 Schematically shows a first semiconductor layer POLY, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4, and other film layers are not shown. Figure 36 The second metal layer M2 in Figure 34 As shown, Figure 36 The third metal layer M3 in Figure 35 shown. Figure 36 The pixel driving circuit shown corresponds to Figure 4 The simplified circuit shown.

[0119] Optionally, refer to Figure 4 、 Figure 35 and Figure 36 The direction in which the end of the first connection line 141 is away from the first data line 121 is the same as the direction in which the end of the second connection line 142 is away from the second data line 122. The first connection line 141 and the second connection line 142 are arranged in the same direction. The first connection line 141 and the second connection line 142 are both arranged in the first direction X.

[0120] Optionally, refer to Figure 32-Figure 36 The first connecting line 141 and the second connecting line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are vertically offset along the second direction Y. The main portion of the first connecting line 141 and the main portion of the second connecting line 142 are not arranged on the same straight line. The first connecting line 141 and the second connecting line 142 are located on the same film layer and extend along the first direction X. The first connecting line 141 and the second connecting line 142 are staggered along the second direction Y. This prevents short circuits between the first connecting line 141 and the second connecting line 142.

[0121] For example, refer to Figure 32 Along the second direction Y, the distance between the first connection line 141 and the second sub-second reset signal transmission line VR22 is a first distance, and the distance between the second connection line 142 and the second sub-second reset signal transmission line VR22 is a second distance. The first distance and the second distance are not equal.

[0122] Optionally, refer to Figure 32-Figure 36 The display panel also includes a horizontal constant voltage line extending along a first direction X, and the horizontal constant voltage line, the first connection line 141 and the second connection line 142 are arranged in the same layer. Along the second direction Y, the horizontal constant voltage line is located between adjacent pixel drive circuit rows 300. Along the second direction Y, the first connection line 141 is located on the side of the extension line of the second connection line 142 away from the horizontal constant voltage line. The first distance is greater than the second distance. As a result, the first connection line 141 avoids the narrow space between the second connection line 142 and the horizontal constant voltage line, avoiding short circuit between the first connection line 141, the second connection line 142 and the horizontal constant voltage line. On the other hand, the first connection line 141 is arranged on the side of the second connection line 142 away from the horizontal constant voltage line, and the additional first connection line 141 and the second connection line 142 can be wired without changing the original position of the horizontal constant voltage line.

[0123] For example, refer to Figure 32 and Figure 33 The lateral constant voltage line includes a second sub-second reset signal transmission line VR22. The second sub-second reset signal transmission line VR22, the first connecting line 141, and the second connecting line 142 are located in the third metal layer M3. In the same sub-pixel region 400, along the second direction Y, the second connecting line 142 is located between the first connecting line 141 and the second sub-second reset signal transmission line VR22. In other embodiments, the lateral constant voltage line may also include, for example, a regulation signal transmission line DVH.

[0124] For example, refer to Figure 33The third data line 123 is electrically connected to the second electrode of the data write transistor T2 through a third via 153. The second electrode of the data write transistor T2 is located in the first semiconductor layer POLY. The third via 153 includes a via connection line connecting the fourth metal layer M4 to the third metal layer M3, a via connection line connecting the third metal layer M3 to the second metal layer M2, and a via connection line connecting the second metal layer M2 to the first semiconductor layer POLY. In the same sub-pixel area 400, along the second direction Y, the third via 153 is located between the second connection line 142 and the horizontal constant voltage line.

[0125] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 The direction in which the end of the first connection line 141 is away from the first data line 121 is opposite to the direction in which the end of the second connection line 142 is away from the second data line 122. The first connection line 141 and the second connection line 142 are arranged opposite each other. For example, the first connection line 141 is arranged in a first direction, and the second connection line 142 is arranged in a direction opposite to the first direction. In other embodiments, the first connection line 141 is arranged in a direction opposite to the first direction, and the second connection line 142 is arranged in the first direction.

[0126] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 The first connection line 141 and the second connection line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are arranged along the second direction Y. In the same sub-pixel region 400, the first connection line 141 and the second connection line 142 overlap along the second direction Y, and the second connection line 142 and the first connection line 141 are arranged sequentially along the second direction Y.

[0127] For example, refer to Figure 6 、 Figure 15 and Figure 19 , the first connecting line 141 and the second connecting line 142 are arranged in the same sub-pixel area group. Along the first direction X, the sub-pixel area group where the connecting line 140 is set and the sub-pixel area group where the connecting line 140 is not set are arranged alternately. Take the third pixel driving circuit row 300 as an example. The connecting line 140 is not set in the area where the first pixel driving circuit 110 and the second pixel driving circuit 110 are located. The first connecting line 141 and the second connecting line 142 are set in the area where the third pixel driving circuit 110 and the fourth pixel driving circuit 110 are located. The connecting line 140 is not set in the area where the fifth pixel driving circuit 110 and the sixth pixel driving circuit 110 are located.

[0128] For example, refer to Figure 6 、 Figure 15 and Figure 19 The transverse constant voltage line (eg, the second sub-second reset signal transmission line VR22), the first connection line 141, and the second connection line 142 are disposed on the same layer. Along the second direction Y, the first connection line 141 is located between the second connection line 142 and the transverse constant voltage line.

[0129] In the 2SD process, the first connection line 141 includes a first connection line main portion 1411 and a first connection line bend portion 1412, which are connected to each other. The first end of the first connection line main portion 1411 is electrically connected to the first data line 121, and the second end of the first connection line main portion 1411 is electrically connected to the first end of the first connection line bend portion 1412. The second end of the first connection line bend portion 1412 is electrically connected to the first pixel driving circuit 111. The length of the first connection line main portion 1411 is greater than the length of the first connection line bend portion 1412. The first connection line main portion 1411 is the portion of the first connection line 141 that extends along the first direction X. To avoid short circuiting with the fourth via 154, the first connection line bend portion 1412 is bent relative to the first connection line main portion 1411 toward a side away from the driving transistor T3. In the same sub-pixel region 400 , along the second direction Y, the distance between the first connection line main portion 1411 and the second connection line 142 is smaller than the distance between the first connection line bent portion 1412 and the second connection line 142 .

[0130] For example, refer to Figure 6 、 Figure 28 and Figure 30 In the 3SD process, the first connection line 141 and the second connection line 142 are both straight. There is no need to provide a bend in the first connection line 141 or the second connection line 142. This reduces the difficulty of designing and routing the first connection line 141 and the second connection line 142.

[0131] Optionally, refer to Figure 2-Figure 6 ,as well as Figures 15-36 The connection line 140 overlaps with the second pixel driving circuit column 102. The pixel driving circuit 110 and the data line 120 connected thereto span one second pixel driving circuit column 102. In other words, the connection line 140 spans one second pixel driving circuit column 102.

[0132] For example, refer to Figure 2 The (n+2)th data line is electrically connected to the first pixel driving circuit 111 in the n-th pixel driving circuit column. The (n+2)th data line is located at the position of the (n+2)th pixel driving circuit column. There is a second pixel driving circuit column 102 between the (n+2)th data line and the first pixel driving circuit 111 in the n-th pixel driving circuit column.

[0133] Optionally, refer to Figures 15-36The film layer where the connecting line 140 is located is located between the film layer where the data line 120 is located and the substrate 200. Therefore, the existing film layer between the film layer where the data line 120 is located and the substrate 200 can be used to form the connecting line 140, eliminating the need for a new film layer for the connecting line 140. This does not increase the thickness or cost of the display panel.

[0134] Optionally, refer to Figure 6 、 Figure 15 and Figure 19 The pixel driving circuit includes a driving transistor T3 and a data writing transistor T2. The first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3. The display panel includes a first scan line SP. The first scan line SP extends along a first direction X and is electrically connected to the gate electrode of the data writing transistor T2. The first scan line SP is located in the first metal layer M1. The portion where the first scan line SP overlaps with the semiconductor trace in the first semiconductor layer POLY forms the gate electrode of the data writing transistor T2.

[0135] Combined with reference Figure 13 、 Figure 15 and Figure 19 The display panel also includes a jumper 161, which is connected to the gate of the drive transistor T3 and the first node N1. The jumper 161 is connected to the first electrode of the compensation transistor T4 in the second semiconductor layer IGZO through a via, and to the second electrode of the first reset transistor T5 in the second semiconductor layer IGZO. The jumper 161 overlaps with the first scan line SP, and the film layer where the first scan line SP is located is located between the film layer where the jumper 161 is located and the substrate 200. The connecting line 140 and the jumper 161 are provided on the same layer. As a result, the connecting line 140 and the jumper 161 can be formed simultaneously in the same process, using the same process and materials, saving process steps.

[0136] Exemplarily, the first scan line SP is located in the first metal layer M1. The jumper line 161 and the connecting line 140 are located in the second metal layer M2. The impedance of the second metal layer M2 is lower than that of the first metal layer M1, and the second metal layer M2 has better conductivity than the first metal layer M1. Placing the connecting line 140 in the second metal layer M2 can reduce the voltage drop across the connecting line 140 and improve the signal transmission capability of the connecting line 140. It should be noted that in other embodiments, other film layers can also be used to form the connecting line 140. For example, the connecting line 140 can be disposed in the first sub-gate metal layer MC or the second sub-gate metal layer MG.

[0137] Optionally, refer to Figure 6 、 Figure 15 and Figure 19The connecting line 140 is electrically connected to the second electrode of the data write transistor T2. The second electrode of the data write transistor T2 is located in the first semiconductor layer POLY, which is located between the film layer where the first scan line SP is located and the substrate 200. The area where the semiconductor trace in the first semiconductor layer POLY overlaps with the first scan line SP forms the first channel layer 2021 of the data write transistor T2. The semiconductor trace connected to the first channel layer 2021 of the data write transistor T2 is heavily doped to improve its conductivity. In other words, the semiconductor trace connected to the first channel layer 2021 of the data write transistor T2 is a connecting trace used to connect various thin film transistors 21.

[0138] For example, refer to Figure 19 The second data line 122 in the third metal layer M3 is connected to the second connection line 142 in the second metal layer M2 through the fourth via 154. The second connection line 142 extends in a direction opposite to the first direction X. The second connection line 142 passes through the via and is connected from the second metal layer M2 to the second electrode of the data write transistor T2 in the first semiconductor layer POLY.

[0139] Optionally, refer to Figures 27-30 , the pixel driving circuit 110 includes a driving transistor T3 and a data writing transistor T2, and the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3. The display panel also includes a first scanning line SP and a jumper 161. The first scanning line SP extends along the first direction X, and the first scanning line SP is electrically connected to the gate of the data writing transistor T2. The jumper 161 is connected to the gate of the driving transistor T3, and the jumper 161 overlaps with the first scanning line SP. The film layer where the first scanning line SP is located is located between the film layer where the jumper 161 is located and the substrate 200. The connecting line 140 is located between the film layer where the jumper 161 is located and the film layer where the data line 120 is located. The jumper 161 is located in the second metal layer M2. The second metal layer M2 is provided with a large number of vias and bridge wiring. The wiring space in the second metal layer M2 is relatively narrow. In the case of Figure 28 In the 3SD process shown, the connection line 140 is set in the film layer between the second metal layer M2 and the film layer where the data line 120 is located. The connection line 140 does not occupy the wiring space in the second metal layer M2, thereby reducing the wiring difficulty in the second metal layer M2.

[0140] For example, refer to Figures 27-30, the first scan line SP is located in the first metal layer M1. The jumper line 161 is located in the second metal layer M2. The connecting line 140 is located in the third metal layer M3. The data line 120 is located in the fourth metal layer M4. The impedance of the third metal layer M3 is lower than that of the first metal layer M1, and the third metal layer M3 has better conductivity than the first metal layer M1. Setting the connecting line 140 in the third metal layer M3 can reduce the voltage drop on the connecting line 140 and improve the signal transmission capability of the connecting line 140. It should be noted that in other embodiments, other film layers can also be used to form the connecting line 140. For example, the connecting line 140 can be set in the first sub-gate metal layer MC, the second sub-gate metal layer MG, or the second metal layer M2.

[0141] For example, refer to Figure 28 The third metal layer M3 includes a connection line 140 and a second sub-second reset signal transmission line VR22. Thus, the connection line 140 and the second sub-second reset signal transmission line VR22 can be formed simultaneously in the same process using the same process and materials, saving process steps.

[0142] Optionally, refer to Figures 31-36 The data line 120 includes a first data line 121, and the connecting line 140 includes a first connecting line 141. The display panel also includes an auxiliary connecting line 162, which is disposed on the same layer as the jumper line 161. The auxiliary connecting line 162 and the jumper line 161 are located in the second metal layer M2. The auxiliary connecting line 162 connects the first connecting line 141 to the second electrode of the data write transistor T2. The second electrode of the data write transistor T2 is located in the first semiconductor layer POLY, which is located between the film layer where the first scan line SP is located and the substrate 200.

[0143] For example, refer to Figures 31-36 The first data line 121 located in the fourth metal layer M4 is connected to the first connection line 141 in the third metal layer M3 through a via. The first connection line 141 in the third metal layer M3 is connected to the auxiliary connection line 162 in the second metal layer M2 through a via. The auxiliary connection line 162 in the second metal layer M2 is connected to the second electrode of the data write transistor T2 in the first semiconductor layer POLY through a via. This achieves electrical connection between the first data line 121 and the second electrode of the data write transistor T2.

[0144] Optionally, refer to Figures 31-36, the data line 120 also includes a second data line 122. The auxiliary connection line 162 extends along the second direction Y, and the auxiliary connection line 162 overlaps with the second data line 122. The auxiliary connection line 162 and the second data line 122 located in different film layers are arranged opposite each other, that is, the auxiliary connection line 162 is arranged below the second data line 122. The area jointly occupied by the auxiliary connection line 162 and the second data line 122 is reduced. As a result, the width of the sub-pixel area 400 can be reduced along the second direction Y, thereby increasing the PPI. On the other hand, the auxiliary connection line 162 overlaps with the second data line 122 in a direction perpendicular to the plane of the substrate 200, reducing the area jointly occupied by the auxiliary connection line 162 and the second data line 122, thereby reducing the light shielding area jointly occupied by the auxiliary connection line 162 and the second data line 122.

[0145] Optionally, refer to Figures 31-36 , the auxiliary connection line 162 is electrically connected to the second electrode of the data write transistor T2 through the first via 151. The first via 151 includes a via connection line connected from the second metal layer M2 to the first semiconductor layer POLY. The data line 120 also includes a second data line 122, and the connection line 140 also includes a second connection line 142. The second connection line 142 is electrically connected to the second data line 122 through the second via 152. The second via 152 includes a via connection line connected from the fourth metal layer M4 to the third metal layer M3. Perpendicular to the plane of the substrate 200, the first via 151 and the second via 152 overlap. The first via 151 and the second via 152 are on different layers and will not be short-circuited due to the overlap. The first via 151 and the second via 152 are arranged to face each other in a direction perpendicular to the plane of the substrate 200, thereby reducing the area occupied by the first via 151 and the second via 152. The PPI is increased, and the light shielding area of ​​the first via hole 151 and the second via hole 152 is reduced.

[0146] Optionally, refer to Figure 28 and Figure 30The display panel also includes a longitudinal constant voltage line, which is arranged in the same layer as the data line 120. The longitudinal constant voltage line extends along the second direction Y. Along the first direction X, the longitudinal constant voltage line is located between two adjacent data lines 120. The first connecting line 141 includes a first conductive segment 171 and a second conductive segment 172 connected to each other. The first end of the first conductive segment 171 is electrically connected to the first data line 121, and the second end of the first conductive segment 171 is electrically connected to the first pixel driving circuit 111. The second conductive segment 172 is located on both sides of the first conductive segment 171 on the second data line 122, and the second conductive segment 172 overlaps with the longitudinal constant voltage line. The first conductive segment 171 overlaps with the longitudinal constant voltage line on one side of the second pixel driving circuit column 102. The second conductive segment 172 overlaps with the longitudinal constant voltage line on the other side of the second pixel driving circuit column 102. Therefore, after the first conductive segment 171 connects the first data line 121 and the first pixel driving circuit 111, the second conductive segment 172 is provided in the extending direction of the first connecting line 141. This allows the first connecting line 141 to overlap with the longitudinal constant voltage line on opposite sides of the second pixel driving circuit column 102, thereby balancing the coupling effects of the first connecting line 141 on different pixel driving circuits 110 arranged in the first direction X.

[0147] The second connection line 142 includes a third conductive segment 173 and a fourth conductive segment 174 connected to each other. The first end of the third conductive segment 173 is electrically connected to the second data line 122, and the second end of the third conductive segment 173 is electrically connected to the second pixel driving circuit 112. The fourth conductive segment 174 is located on either side of the third conductive segment 173 and overlaps with the longitudinal constant voltage line.

[0148] The third conductive segment 173 overlaps with the longitudinal constant voltage line on one side of the second pixel driving circuit column 102. The fourth conductive segment 174 overlaps with the longitudinal constant voltage line on the other side of the second pixel driving circuit column 102. Thus, after the third conductive segment 173 connects the second data line 122 and the second pixel driving circuit 112, the fourth conductive segment 174 is provided in the extending direction of the second connecting line 142, so that the second connecting line 142 overlaps with the longitudinal constant voltage line on both opposite sides of the second pixel driving circuit column 102, thereby balancing the coupling effect of the second connecting line 142 on different pixel driving circuits 110 arranged in the first direction X.

[0149] Illustratively, the first conductive segment 171 is located between the first data line 121 and the second data line 122 electrically connected thereto. The third conductive segment 173 is located between the second data line 122 and the first data line 121 electrically connected thereto. The longitudinal constant voltage line includes at least one of a second sub-first reset signal transmission line VR12, a third sub-second reset signal transmission line VR23, and a second adjustment signal transmission line DVH2.

[0150] It should be noted that the coupling effect of the equalizing connection line 140 on the different pixel driving circuits 110 arranged in the first direction X is not only applicable to the following Figure 30 The case where the first connecting line 141 and the second connecting line 142 are arranged in opposite directions is also applicable to the case where the first connecting line 141 and the second connecting line 142 are arranged in the same direction. The method of balancing the coupling effect of the connecting line 140 on different pixel driving circuits 110 arranged in the first direction X is not only applicable to the case where the first connecting line 141 and the second connecting line 142 are arranged in the same direction. Figure 30 The 3SD process shown is also applicable to the 2SD process.

[0151] Figure 37 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figures 29-37 The display panel further includes a first lead line 181 and a second lead line 182. The first lead line 181 extends along a first direction X, and the second lead line 182 extends along a second direction Y. A plurality of first lead lines 181 are arranged along the second direction Y. A plurality of second lead lines 182 are arranged along the first direction X. The second lead line 182 is in the same layer as the data line 120. For example, the second lead line 182 and the data line 120 are located in the third metal layer M3, or the second lead line 182 and the data line 120 are located in the fourth metal layer M4. The first lead line 181 connects the data line 120 and the second lead line 182. The connecting line 140 is arranged in the same layer as the first lead line 181. As a result, the connecting line 140 and the first lead line 181 can be formed simultaneously in the same process using the same process and materials, saving process steps. On the other hand, the connecting wires 140 and the first lead wires 181 both extend along the first direction X. The connecting wires 140 and the first lead wires 181 are arranged on the same layer, and the connecting wires 140 and the first lead wires 181 extending in the same direction will not cross or short-circuit.

[0152] For example, refer to Figures 29-37, the first lead line 181 and the second lead line 182 are arranged in different layers. In the direction perpendicular to the plane where the substrate 200 is located, the film layer where the first lead line 181 is located is located between the film layer where the second lead line 182 is located and the substrate 200. The display panel includes a display area 301 and a non-display area 302. The non-display area 302 is located at the periphery of the display area 301. The light-emitting unit 130 is located in the display area 301. In one embodiment, the pixel driving circuit 110 is located in the display area 301. In another embodiment, the pixel driving circuit 110 is located in the display area 301 and the non-display area 302. The non-display area 302 includes a bottom non-display area 3021. The source driving circuit 500 is provided in the bottom non-display area 3021. The first lead line 181 and the second lead line 182 are used to transmit the signal of the source driving circuit 500 to the data line 120. A first lead line 181 and a second lead line 182 are set in the display area 301 to lead the data line 120 to the source driver circuit 500 of the bottom non-display area 3021, thereby eliminating the need to set a fan-out line in the bottom non-display area 3021, reducing the space of the bottom non-display area 3021, and facilitating reducing the border and increasing the screen-to-body ratio.

[0153] Optionally, refer to Figure 2-Figure 6 ,as well as Figures 15-36 , multiple pixel driving circuits 110 form pixel driving circuit rows 300 along a first direction X. The multiple pixel driving circuit rows 300 include a first pixel driving circuit row 310 and a second pixel driving circuit row 320. Along a second direction Y, the first pixel driving circuit row 310 and the second pixel driving circuit row 320 are arranged alternately. Along the second direction Y, a second pixel driving circuit row 320 is arranged between two first pixel driving circuit rows 310, and a first pixel driving circuit row 310 is arranged between two second pixel driving circuit rows 320. Of the first pixel driving circuit row 310 and the second pixel driving circuit row 320, only the pixel driving circuits 110 in the first pixel driving circuit row 310 are electrically connected to the connecting line 140. The pixel driving circuits 110 in the second pixel driving circuit row 320 are not electrically connected to the connecting line 140. In the embodiment of the present invention, the connecting lines 140 are arranged in alternate rows. Between two adjacent rows of sub-pixel regions 400 provided with connecting lines 140, there is a row of sub-pixel regions 400 not provided with connecting lines 140.

[0154] Optionally, refer to Figures 15-36, the display panel also includes a dummy connection line 190. The first end of the dummy connection line 190 is electrically connected to the data line 120, and the second end of the dummy connection line 190 is floating. The second end of the dummy connection line 190 is floating, and the second end of the dummy connection line 190 is not connected to the second electrode of the data write transistor T2. Along the second direction Y, the dummy connection lines 190 and the connection lines 140 in the same column are arranged alternately. The connection line 140 is arranged in the first pixel driving circuit row 310, and the dummy connection line 190 is arranged in the second pixel driving circuit row 320. The dummy connection line 190 and the connection line 140 are arranged alternately according to the pixel driving circuit row 300. The connection line 140 is arranged in the first pixel driving circuit row 310, and the connection line 140 has a coupling effect on each node or thin film transistor 21 in the first pixel driving circuit row 310. In the embodiment of the present invention, dummy connection lines 190 are provided in the second pixel driving circuit row 320. The dummy connection lines 190 generate coupling effects on the nodes or thin film transistors 21 in the second pixel driving circuit row 320. This reduces the differences in coupling effects on the pixel driving circuits 110 in each row and enhances display uniformity.

[0155] Exemplarily, the plurality of dummy connection lines 190 include a first dummy connection line 191 and a second dummy connection line 192. The first dummy connection line 191 is connected to the first data line 121, and the second dummy connection line 192 is connected to the second data line 122. The first dummy connection line 191 and the first connection line 141 are both connected to the first data line 121, and the first dummy connection line 191 is a line corresponding to the first connection line 141. The second dummy connection line 192 and the second connection line 142 are both connected to the second data line 122, and the second dummy connection line 192 is a line corresponding to the second connection line 142.

[0156] For example, refer to Figure 15 、 Figure 19 、 Figure 28 and Figure 30 The first connection line 141 and the second connection line 142 are arranged opposite to each other. The first dummy connection line 191 and the second dummy connection line 192 are arranged opposite to each other. The first dummy connection line 191 and the first connection line 141 are arranged in the first direction X. The second dummy connection line 192 and the second connection line 142 are arranged in the opposite direction of the first direction X.

[0157] For example, refer to Figure 15 and Figure 19In the same sub-pixel region 400, the second connection line 142 and the first connection line 141 are sequentially arranged along the second direction Y, and the second dummy connection line 192 and the first dummy connection line 191 are sequentially arranged along the second direction Y. In the same sub-pixel region 400, along the second direction Y, the second connection line 142 is located between the first connection line 141 and the second sub-second reset signal transmission line VR22. In the same sub-pixel region 400, along the second direction Y, the first dummy connection line 191 is located between the second dummy connection line 192 and the second sub-second reset signal transmission line VR22.

[0158] For example, refer to Figure 28 and Figure 30 In the same sub-pixel region 400, the first connection line 141 and the second connection line 142 are sequentially arranged along the second direction Y, and the second dummy connection line 192 and the first dummy connection line 191 are sequentially arranged along the second direction Y. In the same sub-pixel region 400, along the second direction Y, the second dummy connection line 192 is located between the first dummy connection line 191 and the second sub-second reset signal transmission line VR22. As a result, the first dummy connection line 191 and the first connection line 141 are arranged at the same or similar position relative to the sub-pixel region 400. The second dummy connection line 192 and the second connection line 142 are arranged at the same or similar position relative to the sub-pixel region 400. The difference between the coupling effects on the pixel driving circuits 110 of each row is reduced, thereby enhancing display uniformity.

[0159] For example, refer to Figure 15 、 Figure 19 、 Figure 28 and Figure 30 The display panel further includes a connecting lead 83. The connecting lead 83 is disposed on the same layer as the dummy connecting line 190. The connecting lead 83 connects the first data line 121 to the second electrode of the data writing transistor T2. The first data line 121 is connected to the pixel driving circuit 110 in the current pixel driving circuit column 100 via the connecting lead 83. In one embodiment, the connecting lead 83 overlaps the first data line 121 perpendicular to the plane of the substrate 200. This increases the PPI and light transmittance.

[0160] For example, refer to Figure 22-Figure 25 The first connection line 141 and the second connection line 142 are arranged in the same direction. The first dummy connection line 191 and the second dummy connection line 192 are arranged in the same direction.

[0161] For example, refer to Figure 22 and Figure 23The first connection line 141, the second connection line 142, the first dummy connection line 191 and the second dummy connection line 192 are arranged in the same direction. The first dummy connection line 191, the first connection line 141, the second dummy connection line 192 and the second connection line 142 are arranged in the opposite direction of the first direction X.

[0162] For example, refer to Figure 24 、 Figure 25 、 Figure 32 、 Figure 33 、 Figure 35 and Figure 36 , the first connection line 141 and the second connection line 142 are arranged in the same direction. The first dummy connection line 191 and the second dummy connection line 192 are arranged in the same direction. The first connection line 141 and the first dummy connection line 191 are arranged opposite to each other. The first connection line 141 and the second connection line 142 are arranged in the first direction X. The first dummy connection line 191 and the second dummy connection line 192 are arranged in the opposite direction of the first direction X. Alternatively, the first connection line 141 and the second connection line 142 are arranged in the opposite direction of the first direction X. The first dummy connection line 191 and the second dummy connection line 192 are arranged in the first direction X.

[0163] Optionally, refer to Figure 24-25 , Figure 32-Figure 36 The dummy connection lines 190 and the connection lines 140 connected to the same data line 120 are located on opposite sides of the data line 120. The dummy connection lines 190 and the connection lines 140 connected to the same data line 120 are alternately arranged along the second direction Y.

[0164] For example, refer to Figure 24 and Figure 25 The second dummy connection line 192 connected to the second data line 122 is arranged in the opposite direction of the first direction X. The second dummy connection line 192 overlaps with the sub-pixel area 400 where the second pixel driving circuit 112 and the third pixel driving circuit 113 are located (eg Figure 24 The second dummy connection line 192 has a coupling effect on the second pixel driving circuit 112 and the third pixel driving circuit 113. The second connection line 142 connected to the second data line 122 is arranged in the first direction X. The second connection line 142 also overlaps with the sub-pixel area 400 where the second pixel driving circuit 112 and the third pixel driving circuit 113 are located (as shown in the dotted line in the figure). Figure 24 As a result, the difference in coupling effects on the pixel driving circuits 110 at different locations is reduced.

[0165] Optionally, Figure 15 、 Figure 19 、 Figure 22 、 Figure 23 、 Figure 28 and Figure 30 , a dummy connection line 190 connected to the same data line 120, the dummy connection line 190 and the connection line 140 are located on the same side of the data line 120, and the dummy connection line 190 and the connection line 140 are alternately arranged along the second direction Y.

[0166] For example, refer to Figure 15 、 Figure 19 、 Figure 22 、 Figure 23 、 Figure 28 and Figure 30 The second connection line 142 connected to the second data line 122 is arranged in the opposite direction of the first direction X, and the second dummy connection line 192 connected to the second data line 122 is arranged in the opposite direction of the first direction X. The second connection line 142 and the second dummy connection line 192 connected to the same second data line 122 are located on the same side of the second data line 122.

[0167] For example, refer to Figure 15 、 Figure 19 、 Figure 28 and Figure 30 Along the second direction Y, two dummy connection lines 190 form a dummy connection line group, and the two dummy connection lines 190 are respectively a first dummy connection line 191 and a second dummy connection line 192. Along the second direction Y, two connection lines 140 form a connection line group, and the two connection lines 140 are respectively a first connection line 141 and a second connection line 142. Along the second direction Y, the dummy connection line groups and the connection line groups are arranged alternately. In other words, the following are repeatedly arranged along the second direction Y: two dummy connection lines 190, two connection lines 140, ..., two dummy connection lines 190 and two connection lines 140.

[0168] For example, refer to Figure 22 and Figure 23 Along the second direction Y, the first dummy connection lines 191 and the first connection lines 141 in the same column are alternately arranged. Along the second direction Y, the second dummy connection lines 192 and the second connection lines 142 in the same column are alternately arranged.

[0169] For example, refer to Figure 24 、 Figure 25 、 Figure 32-Figure 36 Along the second direction Y, the second dummy connection lines 192 and the first connection lines 141 in the same column are alternately arranged. Along the second direction Y, the first dummy connection lines 191 and the second connection lines 142 in the same column are alternately arranged.

[0170] Optionally, refer to Figures 15-36, the dummy connecting line 190 is insulated and overlapped with at least one data line 120. A second pixel driving circuit column 102 is provided between the pixel driving circuit 110 and the data line 120 connected thereto. For example, a second pixel driving circuit column 102 is provided between the n+2th data line and the first pixel driving circuit 111 in the nth pixel driving circuit column. As a result, the connecting line 140 is insulated and overlapped with at least one data line 120. In the embodiment of the present invention, a dummy connecting line 190 is provided to be insulated and overlapped with at least one data line 120. This reduces the difference in coupling effects on the pixel driving circuits 110 in each row, thereby enhancing display uniformity.

[0171] Figure 38 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 38 , the pixel driving circuit column 100 includes a first pixel driving circuit column 101 and a second pixel driving circuit column 102. The first pixel driving circuit column 101 includes a first pixel driving circuit 111 and a second pixel driving circuit 112. The pixel driving circuit 110 in the second pixel driving circuit column 102 includes a third pixel driving circuit 113. The third pixel driving circuit 113 drives light-emitting units 130 of different luminous colors together with the first pixel driving circuit 111 and the second pixel driving circuit 112. Along the first direction X, the second pixel driving circuit column 102 is located between the two first pixel driving circuit columns 101. Along the first direction X, the first pixel driving circuit 111, the second pixel driving circuit 112 and the third pixel driving circuit 113 are arranged sequentially. The three pixel driving circuits 110 arranged sequentially and adjacent to each other along the first direction X include the first pixel driving circuit 111, the second pixel driving circuit 112 and the third pixel driving circuit 113. Along the first direction X, the first pixel driving circuit 111 is located between the second pixel driving circuit 112 and the third pixel driving circuit 113, the second pixel driving circuit 112 is located between the first pixel driving circuit 111 and the third pixel driving circuit 113, and the third pixel driving circuit 113 is located between the first pixel driving circuit 111 and the second pixel driving circuit 112.

[0172] For example, refer to Figure 38Along the second direction Y, the first light-emitting unit 131, the second light-emitting unit 132, and the third light-emitting unit 133 are arranged in sequence to form a light-emitting unit column. Three adjacent light-emitting units 130 arranged in sequence along the second direction Y include the first light-emitting unit 131, the second light-emitting unit 132, and the third light-emitting unit 133. Along the second direction Y, the first light-emitting unit 131 is located between the second light-emitting unit 132 and the third light-emitting unit 133, the second light-emitting unit 132 is located between the first light-emitting unit 131 and the third light-emitting unit 133, and the third light-emitting unit 133 is located between the first light-emitting unit 131 and the second light-emitting unit 132. Multiple light-emitting unit columns are staggered along the first direction X. Along the first direction X, the first light-emitting unit 131 and the second light-emitting unit 132 are arranged alternately, or the second light-emitting unit 132 and the third light-emitting unit 133 are arranged alternately.

[0173] Optionally, refer to Figure 38 , the multiple data lines 120 include a first data line 121 and a second data line 122. The first data line 121 includes the n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit 111 in the n+2th pixel driving circuit column. The second data line 122 includes the nth data line, and the nth data line is electrically connected to the nth pixel driving circuit column and the second pixel driving circuit 112 in the n+2th pixel driving circuit column, where n is a positive integer. In an embodiment of the present invention, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 is connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the second data line 122 at the position of the current pixel driving circuit column 100.

[0174] Figure 39 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 39, the plurality of data lines 120 include a first data line 121 and a second data line 122. The first data line 121 includes an n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit 111 in the n+2th pixel driving circuit column. The second data line 122 includes an n+3th data line, and the n+3th data line is electrically connected to the n+2th pixel driving circuit column and the second pixel driving circuit 112 in the n+3th pixel driving circuit column, where n is a positive integer. In an embodiment of the present invention, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 is connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the previous pixel driving circuit column 100 is connected to the second data line 122 at the position of the current pixel driving circuit column 100.

[0175] Figure 40 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention, referring to Figure 40 , the multiple data lines 120 include a first data line 121 and a second data line 122. The first data line 121 includes the n+2th data line, and the n+2th data line is electrically connected to the first pixel driving circuit 111 in the n+2th pixel driving circuit column and the n+3th pixel driving circuit column. The second data line 122 includes the nth data line, and the nth data line is electrically connected to the second pixel driving circuit 112 in the nth pixel driving circuit column and the n+2th pixel driving circuit column, where n is a positive integer. In an embodiment of the present utility model, the first pixel driving circuit 111 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the first data line 121 at the position of the current pixel driving circuit column 100. The second pixel driving circuit 112 in the current pixel driving circuit column 100 and the subsequent pixel driving circuit column 100 is connected to the second data line 122 at the position of the current pixel driving circuit column 100.

[0176] For example, refer to Figures 38-40 The first connection line 141 and the second connection line 142 connecting the pixel driving circuits 110 in the same pixel driving circuit row 300 are located on the same side of the pixel driving circuit row 300, or on opposite sides of the pixel driving circuit row 300.

[0177] A pixel drive circuit arrangement can correspond to one or more light-emitting unit arrangements. In other words, when a pixel drive circuit arrangement is determined, the pixel drive circuit in that arrangement can be used to drive light-emitting units in one or more arrangements.

[0178] Figure 41 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention. Figure 41 Indicate Figure 2 An arrangement of light-emitting units under the arrangement of the pixel driving circuit shown. Figure 42 This is a schematic diagram of a top view of another display panel provided by an embodiment of the present invention. Figure 42 Indicate Figure 2 Another arrangement of the light-emitting units under the arrangement of the pixel driving circuit shown.

[0179] refer to Figure 2 、 Figure 41 and Figure 42 , along the first direction X, the first light-emitting units 131 and the second light-emitting units 132 are arranged alternately. Along the second direction Y, the first light-emitting units 131 and the second light-emitting units 132 are arranged alternately. A plurality of third light-emitting units 133 are arranged in a row along the first direction X. A plurality of third light-emitting units 133 are arranged in a column along the second direction Y. The second light-emitting unit 132 is surrounded by four adjacent third light-emitting units 133. The third light-emitting unit 133 is surrounded by four adjacent third light-emitting units 133. In other embodiments, the display panel may also have other arrangements of light-emitting units.

[0180] For example, refer to Figure 41 , the third light-emitting unit 133 has a center that coincides with the center of the virtual square VS1. The second light-emitting unit 132 is spaced apart from the third light-emitting unit 133, and the second light-emitting unit 132 has a center at the first vertex P1 of the virtual square VS1. The first light-emitting unit 131 is spaced apart from the second light-emitting unit 132 and the third light-emitting unit 133, and the first light-emitting unit 131 has a center at the second vertex P2 adjacent to the first vertex P1 of the virtual square VS1. The angle between the two adjacent sides formed by the second light-emitting unit 132 and the third light-emitting unit 133 of this design is 90° and constitutes the virtual square VS1. The shape is similar to a rhombus / diamond structure, and those skilled in the art usually call it a "diamond" pixel arrangement.

[0181] For example, refer to Figure 42The plurality of third light-emitting units 133 form a first virtual trapezoid VS2, with the centers of the plurality of third light-emitting units 133 respectively located at the vertices of the first virtual trapezoid VS2, and the second light-emitting units 132 are located inside the first virtual trapezoid VS2. The plurality of second light-emitting units 132 and the plurality of first light-emitting units 131 form a second virtual trapezoid VS3, with the centers of the first light-emitting units 131 located at the second vertex P2 of the second virtual trapezoid VS3, and the centers of the second light-emitting units 132 located at the first vertex P1 of the second virtual trapezoid VS3. The first vertex P1 and the second vertex P2 are alternately and spaced apart, and the third light-emitting units 133 are located inside the second virtual trapezoid VS3.

[0182] For example, the centers of the four third light-emitting units 133 form a first virtual trapezoid VS2, meaning that compared to the "diamond" pixel arrangement, at least one of the four third light-emitting units 133 is offset. The offset of at least one third light-emitting unit 133 means that the third light-emitting unit 133 moves toward the edge of a different display area.

[0183] The centers of multiple second light-emitting units 132 and multiple first light-emitting units 131 constitute a second virtual trapezoid VS3. For example, the centers of two second light-emitting units 132 and two first light-emitting units 131 constitute a second virtual trapezoid VS3, that is, compared with the "diamond" pixel arrangement, at least one sub-pixel in the second light-emitting unit 132 and the first light-emitting unit 131 is offset, wherein the offset of at least one sub-pixel in the second light-emitting unit 132 and the first light-emitting unit 131 refers to the second light-emitting unit 132 or the first light-emitting unit 131 moving to different edges of the display area.

[0184] refer to Figure 41 and Figure 42 , the arrangement of the two light-emitting units satisfies the following requirements: a plurality of second light-emitting units 132 and a plurality of first light-emitting units 131 form a virtual figure. The third light-emitting unit 133 is located within the virtual figure. The second light-emitting unit 132 is spaced apart from the third light-emitting unit 133, and the second light-emitting unit 132 has its center at the first vertex P1 of the virtual figure. The first light-emitting unit 131 is spaced apart from the second light-emitting unit 132 and the third light-emitting unit 133, and the first light-emitting unit 131 has its center at the second vertex P2 adjacent to the first vertex P1 of the virtual figure. The virtual figure can include a virtual square VS1 or a second virtual trapezoid VS3.

[0185] Figure 43 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 43As shown, the display device includes any of the display panels provided in the above embodiments. Therefore, the display device also has the beneficial effects of the display panels in the above embodiments. The similarities can be understood by referring to the above explanation of the display panel, which will not be repeated below.

[0186] The display device provided by the embodiment of the utility model can be Figure 43 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present utility model do not specifically limit this.

[0187] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of pixel driving circuit columns are arranged along a first direction and are located on one side of the substrate; the pixel driving circuit columns include a plurality of pixel driving circuits arranged along a second direction, the first direction intersecting the second direction; the pixel driving circuits in the pixel driving circuit columns include a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit driving light-emitting units of different luminous colors; A plurality of data lines extend along the second direction and are arranged along the first direction; the data lines are connected to the first pixel driving circuits in different pixel driving circuit columns, or the data lines are connected to the second pixel driving circuits in different pixel driving circuit columns.

2. The display panel according to claim 1, wherein: The plurality of data lines include a first data line and a second data line; The first data line includes an n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit in the n+2th pixel driving circuit column; The second data lines include an n+4th data line, the n+4th data line is electrically connected to the n+2th pixel driving circuit column and the second pixel driving circuit in the n+4th pixel driving circuit column, where n is a positive integer.

3. The display panel according to claim 2, wherein: It also includes a first additional data line, which is located on the side of the (n+4)th data line away from the (n+2)th data line and is connected to the first pixel driving circuit or the second pixel driving circuit in the last pixel driving circuit column.

4. The display panel according to claim 1, wherein: The plurality of data lines include a first data line and a second data line; The first data line includes an n+2th data line, and the n+2th data line is electrically connected to the first pixel driving circuits in the n+2th pixel driving circuit column and the n+4th pixel driving circuit column; The second data lines include an nth data line, the nth data line is electrically connected to the second pixel driving circuits in the nth pixel driving circuit column and the n+2th pixel driving circuit column, where n is a positive integer.

5. The display panel according to claim 4, wherein: It also includes a second additional data line, which is located on a side of the nth data line away from the (n+2)th data line and is connected to the first pixel driving circuit or the second pixel driving circuit in the first pixel driving circuit column.

6. The display panel according to claim 1, wherein: The plurality of data lines include a first data line and a second data line; The first data line includes an n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit in the n+2th pixel driving circuit column; The second data lines include an nth data line, the nth data line is electrically connected to the second pixel driving circuits in the nth pixel driving circuit column and the n+2th pixel driving circuit column, where n is a positive integer.

7. The display panel according to claim 1, wherein: It also includes a connecting line, which extends along the first direction and is arranged in a different layer from the data line; The connecting line is connected to the data line and is connected to the first pixel driving circuit or the second pixel driving circuit.

8. The display panel according to claim 7, wherein: The plurality of data lines include a first data line and a second data line, and the plurality of connection lines include a first connection line and a second connection line; The first connecting line connects the first data line and the first pixel driving circuit, and the second connecting line connects the second data line and the second pixel driving circuit.

9. The display panel according to claim 8, wherein: A plurality of the pixel driving circuits form a pixel driving circuit row along the first direction; The first connection line and the second connection line connecting the pixel driving circuits in the same pixel driving circuit row are located on the same side of the pixel driving circuit row.

10. The display panel according to claim 9, wherein: The direction in which the end of the first connecting line is away from the first data line is the same as the direction in which the end of the second connecting line is away from the second data line; The first connection lines and the second connection lines connecting the pixel driving circuits in the same pixel driving circuit row are alternately arranged along the first direction.

11. The display panel according to claim 10, wherein: The first connection line and the second connection line connecting the pixel driving circuits in the same pixel driving circuit row are arranged on the same line.

12. The display panel according to claim 10, wherein: The first connection line and the second connection line connecting the pixel driving circuits in the same pixel driving circuit row are staggered up and down along the second direction.

13. The display panel according to claim 12, wherein: It also includes a transverse constant voltage line extending along the first direction, wherein the transverse constant voltage line, the first connecting line and the second connecting line are arranged in the same layer; Along the second direction, the horizontal constant voltage line is located between adjacent rows of pixel driving circuits; Along the second direction, the first connecting line is located on a side of an extension line of the second connecting line away from the transverse constant-voltage line.

14. The display panel according to claim 9, wherein: The direction in which the end of the first connecting line is away from the first data line is opposite to the direction in which the end of the second connecting line is away from the second data line; The first connection lines and the second connection lines connecting the pixel driving circuits in the same pixel driving circuit row are arranged along the second direction.

15. The display panel according to claim 7, wherein: The pixel driving circuit columns include a first pixel driving circuit column and a second pixel driving circuit column, and along the first direction, the first pixel driving circuit column and the second pixel driving circuit column are alternately arranged; The first pixel driving circuit column includes the first pixel driving circuit and the second pixel driving circuit; The pixel driving circuits in the second pixel driving circuit column include a third pixel driving circuit; the third pixel driving circuit, the first pixel driving circuit, and the second pixel driving circuit drive light-emitting units of different luminous colors; The connecting line overlaps with the second pixel driving circuit column.

16. The display panel according to claim 7, wherein: The film layer where the connecting line is located is located between the film layer where the data line is located and the substrate.

17. The display panel according to claim 16, wherein: The pixel driving circuit includes a driving transistor and a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor; The display panel further includes a first scan line and a jumper line, wherein the first scan line extends along the first direction and is electrically connected to the gate of the data writing transistor; the jumper line is connected to the gate of the driving transistor and overlaps with the first scan line, and the film layer where the first scan line is located is located between the film layer where the jumper line is located and the substrate; The connecting wires and the jumper wires are arranged on the same layer.

18. The display panel according to claim 17, wherein: The connecting line is electrically connected to the second electrode of the data writing transistor; The second electrode of the data writing transistor is located in the first semiconductor layer, and the first semiconductor layer is located between the film layer where the first scanning line is located and the substrate.

19. The display panel according to claim 16, wherein: The pixel driving circuit includes a driving transistor and a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor; The display panel further includes a first scan line and a jumper line, wherein the first scan line extends along the first direction and is electrically connected to the gate of the data writing transistor; the jumper line is connected to the gate of the driving transistor and overlaps with the first scan line, and the film layer where the first scan line is located is located between the film layer where the jumper line is located and the substrate; The connecting line is located between the film layer where the jumper line is located and the film layer where the data line is located.

20. The display panel according to claim 19, wherein The data line includes a first data line, and the connection line includes a first connection line; The display panel further includes an auxiliary connection line, which is provided on the same layer as the jumper line; the auxiliary connection line connects the first connection line and the second electrode of the data writing transistor; The second electrode of the data writing transistor is located in the first semiconductor layer, and the first semiconductor layer is located between the film layer where the first scanning line is located and the substrate.

21. The display panel according to claim 20, wherein: The data lines further include a second data line, and the auxiliary connection line extends along the second direction and overlaps with the second data line.

22. The display panel according to claim 20, wherein: The auxiliary connection line is electrically connected to the second electrode of the data writing transistor through the first via hole; The data line further includes a second data line, and the connecting line further includes a second connecting line, wherein the second connecting line is electrically connected to the second data line through a second via hole; In a direction perpendicular to the plane of the substrate, the first via hole overlaps with the second via hole.

23. The display panel according to claim 8, wherein It also includes a longitudinal constant voltage line, which is arranged in the same layer as the data line and extends along the second direction; along the first direction, the longitudinal constant voltage line is located between two adjacent data lines; The first connecting line includes a first conductive segment and a second conductive segment connected to each other, a first end of the first conductive segment being electrically connected to the first data line, and a second end of the first conductive segment being electrically connected to the first pixel driving circuit; the second conductive segment and the first conductive segment are located on either side of the second data line, and the second conductive segment overlaps with the longitudinal constant voltage line; And / or, the second connecting line includes a third conductive segment and a fourth conductive segment connected to each other, a first end of the third conductive segment is electrically connected to the second data line, and a second end of the third conductive segment is electrically connected to the second pixel driving circuit; the fourth conductive segment and the third conductive segment are located on both sides of the second data line, and the fourth conductive segment overlaps with the longitudinal constant voltage line.

24. The display panel according to claim 7, wherein: Also comprising a first lead wire and a second lead wire, wherein the first lead wire extends along the first direction, and the second lead wire extends along the second direction; The second lead-out line is in the same layer as the data line, the first lead-out line connects the data line and the second lead-out line; and the connecting line is provided in the same layer as the first lead-out line.

25. The display panel according to claim 7, wherein: The plurality of pixel driving circuits form a pixel driving circuit row along the first direction, and the plurality of pixel driving circuit rows include a first pixel driving circuit row and a second pixel driving circuit row; Along the second direction, the first pixel driving circuit rows and the second pixel driving circuit rows are alternately arranged; of the first pixel driving circuit rows and the second pixel driving circuit rows, only the pixel driving circuits in the first pixel driving circuit row are electrically connected to the connecting line.

26. The display panel according to claim 25, wherein: Also included is a dummy connection line, wherein a first end of the dummy connection line is electrically connected to the data line, and a second end of the dummy connection line is floating; Along the second direction, the dummy connection lines and the connection lines in the same column are arranged alternately.

27. The display panel according to claim 26, wherein: The dummy connection lines and the connection lines connected to the same data line are located on opposite sides of the data line and are alternately arranged along the second direction.

28. The display panel according to claim 26, wherein: The dummy connection lines and the connection lines connected to the same data line are located on the same side of the data line and are alternately arranged along the second direction.

29. The display panel according to claim 26, wherein: The dummy connection line is insulated and overlapped with at least one of the data lines.

30. The display panel according to claim 1, wherein The plurality of data lines include a first data line and a second data line; The first data line includes an n+2th data line, and the n+2th data line is electrically connected to the nth pixel driving circuit column and the first pixel driving circuit in the n+2th pixel driving circuit column; The second data lines include an n+3th data line, the n+3th data line is electrically connected to the n+2th pixel driving circuit column and the second pixel driving circuit in the n+3th pixel driving circuit column, where n is a positive integer.

31. The display panel according to claim 1, wherein The plurality of data lines include a first data line and a second data line; The first data line includes an n+2th data line, and the n+2th data line is electrically connected to the first pixel driving circuits in the n+2th pixel driving circuit column and the n+3th pixel driving circuit column; The second data lines include an nth data line, the nth data line is electrically connected to the second pixel driving circuits in the nth pixel driving circuit column and the n+2th pixel driving circuit column, where n is a positive integer.

32. A display device, characterized in that: A display panel comprising any one of claims 1-31.

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