Lead frame, semiconductor power device and semiconductor module
By setting a double groove structure on the lead frame, the problem of unstable solder thickness is solved, stable control of solder thickness is achieved, and the welding quality and the performance and reliability of the integrated circuit are improved.
Patent Information
- Application Number
- CN202422645863.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-10-30
AI Technical Summary
Existing technologies make it difficult to precisely control the thickness of the solder layer, resulting in unstable solder thickness, which affects thermal resistance consistency and integrated circuit performance.
A first groove slightly larger than the chip size is set on the lead frame for filling solder, and a second groove is set around the first groove to collect overflow solder, control the solder climbing height, and ensure stable solder thickness.
The double-groove structure design improves the stability of solder thickness, improves welding quality and performance stability of integrated circuits, simplifies the operation process, and improves production efficiency and yield.
Smart Images
Figure CN223321268U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of device packaging technology, and in particular to a lead frame, a semiconductor power device, and a semiconductor module. Background Art
[0002] The solder layer is a crucial structure in integrated circuit devices, connecting the chip and the frame. If the solder layer is too thin, it can lead to solder voids, increasing thermal resistance. Conversely, if the solder layer is too thick, it also increases thermal resistance, thereby reducing product performance. Furthermore, excessive fluctuations in solder thickness can lead to reduced thermal resistance consistency between samples of the same product, significantly reducing thermal resistance yield.
[0003] However, integrated circuit devices currently using lead-tin solder have difficulty precisely controlling parameters such as the solder dissolution rate and wire feed speed, resulting in the solder thickness being unable to remain stable within a small range. Therefore, improving the stability of solder thickness is a key issue. Utility Model Content
[0004] The purpose of the embodiments of the present application is to provide a lead frame, a semiconductor power device, and a semiconductor module, which can improve the stability of solder thickness.
[0005] In order to solve the above technical problems, an embodiment of the present application provides a lead frame, which includes a first groove and a second groove. The first groove is filled with solder to form a solder part. The solder part includes a first surface and a second surface arranged opposite to each other. The second surface is connected to the bottom surface of the first groove. A chip supporting area is provided on the first surface. The second groove is arranged on the lead frame around the first groove, and a preset distance is provided between the first groove and the second groove.
[0006] An embodiment of the present application further provides a semiconductor power device, comprising the above-mentioned lead frame.
[0007] An embodiment of the present application further provides a semiconductor module, comprising the above-mentioned semiconductor power device.
[0008] The lead frame, semiconductor power device, and semiconductor module provided in the embodiments of this application address the issue of unstable solder thickness by providing a first groove slightly larger than the chip size and of a fixed depth on the lead frame for filling with solder. Furthermore, a second groove is provided around the first groove to collect excess solder and control its rise, ensuring that the solder thickness is stably controlled to a level equivalent to the height of the first groove, thereby improving solder thickness stability.
[0009] In some embodiments, the area of the first surface is larger than the area of the chip-carrying area.
[0010] In some embodiments, the area of the first surface is greater than the area of the second surface.
[0011] In some embodiments, the depth of the first groove is less than the depth of the second groove.
[0012] In some embodiments, the depth of the first groove is greater than or equal to 45 um and less than or equal to 55 um.
[0013] In some embodiments, a depth of the second groove is greater than or equal to 100 um and less than or equal to 130 um, and a width of the second groove is greater than or equal to 10 um and less than or equal to 20 um.
[0014] In some embodiments, the predetermined distance is greater than or equal to 5 um and less than or equal to 20 um. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0016] Figure 1 is a schematic structural diagram of a lead frame provided in some embodiments of the present application;
[0017] Figure 2 is a top view of a lead frame provided in some embodiments of the present application. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.
[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.
[0020] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.
[0021] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.
[0022] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, or electrical connections; direct connections, or indirect connections through an intermediate medium; and can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.
[0023] In current integrated circuit devices, the solder dissolution rate and wire feed speed are key parameters affecting soldering quality. The solder dissolution rate determines how quickly it melts during heating; either too fast or too slow melting can affect solder layer formation. The wire feed speed refers to the speed at which the solder wire is fed during the soldering process. If the wire feed speed is too fast, the solder may not fully dissolve, resulting in poor soldering; if it is too slow, excessive solder accumulation may occur, leading to an excessively thick solder layer. Because these parameters are affected by multiple factors, such as heating temperature, equipment settings, and material properties, they are often difficult to precisely control. This instability in control makes it difficult to maintain solder thickness within a narrow range, resulting in fluctuations in the solder layer thickness. This fluctuation not only affects soldering quality but can also lead to inconsistent thermal resistance, which in turn affects the performance and reliability of the integrated circuit.
[0024] To this end, some embodiments of the present application provide a lead frame having a first groove, slightly larger than the chip size and of a fixed depth, for filling with solder. A second groove is provided around the first groove to collect excess solder and control its height, ensuring that the solder thickness is stably controlled to a level equivalent to the height of the first groove, thereby improving solder thickness stability.
[0025] The following combination Figures 1 to 2 , illustrating the structure of the lead frame provided in some embodiments of the present application.
[0026] like Figures 1 to 2 As shown, the lead frame 10 provided in some embodiments of the present application includes a first groove 11 and a second groove 12. The first groove 11 is filled with solder to form a solder portion. The solder portion includes a first surface 111 and a second surface 112 that are relatively arranged. The second surface 112 is connected to the bottom surface of the first groove 11. A chip supporting area is provided on the first surface 111. The second groove 12 is arranged on the lead frame around the first groove 11. A preset distance is provided between the first groove 11 and the second groove 12.
[0027] The first groove 11 can be filled with solder to form a solder portion, and the solder portion has a first surface 111 and a second surface 112. Figure 1 As shown, the first surface 111 is the top surface of the solder portion and is provided with a chip supporting area for supporting and fixing the chip 20. The second surface 112 is the bottom surface of the solder portion, connected to the bottom surface of the first groove 11 and arranged opposite to the first surface 111 to ensure the stability of the soldering between the chip 20 and the lead frame 10.
[0028] A second groove 12 is provided around the perimeter of the first groove 11, surrounding it and positioned on the lead frame 10. A predetermined distance can be set between the first and second grooves 11, with the lead frame 10 acting as a gap between them to separate them. The primary function of the second groove 12 is to control the height of solder run-up and prevent excessive solder overflow, significantly improving soldering quality and ensuring device performance stability.
[0029] During wafer loading, a slight excess of solder can be used to ensure that after die pressing, the solder fills the first groove 11 and slightly overflows. This design allows the solder thickness to be stably controlled at a level equivalent to the height of the first groove 11, avoiding solder shortages and reducing the high requirements for wafer loading parameter accuracy, thereby simplifying operations and improving production efficiency and soldering yield.
[0030] In some embodiments, the area of the first surface 111 is larger than the area of the chip supporting area.
[0031] The area of the first surface 111 can be larger than the area of the chip supporting area. Specifically, its area can be 50-80um larger than the area of the chip supporting area, ensuring that even if the solder or chip 20 is slightly offset during the mounting process, the first surface 111 can still provide sufficient support area, thereby improving the stability and reliability of the welding process.
[0032] In some embodiments, the area of the first surface 111 is greater than the area of the second surface 112 .
[0033] The area of the first surface 111 is larger than that of the second surface 112, making the upper portion of the first groove 11 wider than the lower portion, forming a wide-mouthed cavity structure. This structure provides more operating space during chip 20 loading and solder filling, allowing for more even solder distribution and effectively reducing solder voids, while also ensuring the stability of the surrounding structure of the first groove 11.
[0034] In practice, to enhance the stability of the structure surrounding the first groove 11, a certain thickness is set at the boundary area of the first groove 11. This thickness design not only enhances the mechanical strength of the groove boundary, but also prevents structural deformation or damage due to thermal expansion, contraction, or mechanical stress during welding and subsequent processing.
[0035] In some embodiments, the depth of the first groove 11 is less than the depth of the second groove 12 .
[0036] In some embodiments, the depth of the first groove 11 is greater than or equal to 45 um and less than or equal to 55 um.
[0037] In actual situations, the depth of the first groove 11 may be 45 um, 50 um or 55 um.
[0038] In some embodiments, the depth of the second groove 12 is greater than or equal to 100 um and less than or equal to 130 um, and the width of the second groove 12 is greater than or equal to 10 um and less than or equal to 20 um.
[0039] In actual situations, the depth of the second groove 12 may be 100 um, 120 um, or 130 um, and the width of the second groove 12 may be 10 um, 15 um, or 20 um.
[0040] In some embodiments, the predetermined distance is greater than or equal to 5 um and less than or equal to 20 um.
[0041] In practice, the preset distance can be 5um, 10um, 15um, or 20um. This effectively improves the stability and consistency of the soldering process, ensuring soldering quality and avoiding solder defects caused by solder overflow. Furthermore, an appropriate gap provides a buffer for thermal expansion, further improving the overall reliability and performance of the integrated circuit device.
[0042] Some embodiments of the present application further provide a semiconductor power device, which includes a chip 20, the above-mentioned lead frame 10 and a plastic package. The chip 20 is arranged on the chip supporting area, and the plastic package is covered on the chip 20 and the lead frame 10.
[0043] The chip 20 is placed on the chip supporting area of the lead frame to ensure a good connection between the chip 20 and the solder. At the same time, the plastic package is wrapped around the chip 20 and the lead frame to provide the necessary protection and insulation effect.
[0044] Some embodiments of the present application further provide a semiconductor module, which includes the above-mentioned semiconductor power device.
[0045] By combining the dual-groove design of first groove 11 and second groove 12 with the power MOSFET assembly process, the semiconductor module can fully utilize existing packaging production line equipment and materials. This design effectively controls solder thickness without increasing product costs.
[0046] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.
Claims
1. A lead frame, characterized in that: include: It includes a first groove and a second groove, the first groove is filled with solder to form a solder part, the solder part includes a first surface and a second surface arranged opposite to each other, the second surface is connected to the bottom surface of the first groove, a chip supporting area is provided on the first surface, the second groove is arranged around the first groove on the lead frame, and a preset distance is provided between the first groove and the second groove.
2. The lead frame according to claim 1, wherein: The area of the first surface is larger than the area of the chip carrying area.
3. The lead frame according to claim 2, wherein: An area of the first surface is greater than an area of the second surface.
4. The lead frame according to claim 3, wherein: The depth of the first groove is smaller than the depth of the second groove.
5. The lead frame according to claim 4, wherein: The depth of the first groove is greater than or equal to 45 um and less than or equal to 55 um.
6. The lead frame according to claim 5, characterized in that: A depth of the second groove is greater than or equal to 100 um and less than or equal to 130 um, and a width of the second groove is greater than or equal to 10 um and less than or equal to 20 um.
7. The lead frame according to claim 6, wherein: The preset distance is greater than or equal to 5 um and less than or equal to 20 um.
8. A semiconductor power device, characterized in that: The invention comprises a chip, a lead frame according to any one of claims 1 to 7, and a plastic package, wherein the chip is arranged on the chip carrying area, and the plastic package is coated on the chip and the lead frame.
9. A semiconductor module, characterized in that: Comprising the semiconductor power device according to claim 8.