Control circuit of current mode interleaving Buck

Abstract

The utility model relates to the field of Buck control circuits, and discloses a current mode interleaved parallel Buck control circuit, which comprises a VBUS + and an IBUS +, the VBUS + and the IBUS + are arranged in parallel, the output end of the VBUS + is provided with a Buck circuit, the output end of the Buck circuit is provided with a CT1, the output end of the CT1 is provided with two first diodes, the output ends of the two first diodes are fixedly connected with two first resistors, and the output ends of the two first diodes are fixedly connected with two second resistors. A comparator is arranged at the output ends of the two first resistors, a power circuit is arranged at the output end of the comparator, and a second resistor is arranged at the output end of the power circuit. According to the utility model, the pulse current transformer CT1 and a series of resistors R74, R75 and R76 are used to accurately sample and feed back the current of the MOS tube Q1, the current is allowed to be monitored in real time, and accurate control is carried out through IN + and IN-ports of the comparator U3, so that the stability and efficiency of the circuit can be improved through the optimization of the current sampling and feedback mechanism; and energy loss is reduced.

Description

Technical Field

[0001] The utility model relates to the field of Buck control circuits, in particular to a current mode interleaved parallel Buck control circuit. Background Art

[0002] Multiphase buck circuits, due to their high reliability and bidirectional power flow, are increasingly being adopted as core technology solutions in products such as waveform generators and energy storage converters. However, their control all relies on DSP chips combined with software algorithms to achieve multiphase buck control.

[0003] Conventional multi-phase interleaved parallel Buck control circuits employ DSP chips, generating control signals for each phase via software algorithms. These expensive DSP chips require software development. Furthermore, the accuracy of these conventional control methods depends on the precision of the PWM wave generated by the DSP chip, making it virtually impossible to achieve control accuracy exceeding 16 bits. Therefore, those skilled in the art have provided a current-mode interleaved parallel Buck control circuit to address the issues raised in the aforementioned background technology. Utility Model Content

[0004] The purpose of the present utility model is to address the shortcomings of the prior art and propose a current mode interleaved parallel Buck control circuit. By using a pulse current transformer CT1 and a series of resistors R74, R75, and R76, accurate sampling and feedback of the current of the MOS tube Q1 are achieved, allowing real-time monitoring of the current and precise control through the IN+ and IN- ports of the comparator U3. The optimization of this current sampling and feedback mechanism can improve the stability and efficiency of the circuit and reduce energy loss. The output voltage and current are controlled by adjusting the drive duty cycle of the MOS tube Q1. This dynamic adjustment mechanism allows the circuit to adapt to different load conditions and maintain the stability of the output voltage and current. This design not only improves the adaptability of the circuit, but also improves energy efficiency. The current sampling signal of the power circuit is processed and the output of U1 is controlled by the comparator U2, thereby realizing protection and control of the power circuit. This integrated protection mechanism can prevent abnormal conditions such as overcurrent and overvoltage from damaging the circuit, ensuring safe and stable operation of the circuit.

[0005] To achieve the above objectives, the present invention provides the following technical solutions: a current-mode interleaved parallel Buck control circuit, comprising VBUS+ and IBUS+, wherein the VBUS+ and IBUS+ are arranged in parallel, a Buck circuit is provided at the output end of the VBUS+, a CT1 is provided at the output end of the Buck circuit, two first diodes are provided at the output end of the CT1, two first resistors are fixedly connected to the output ends of the two first diodes, a comparator is provided at the output end of the two first resistors, a power circuit is provided at the output end of the comparator, a second resistor is provided at the output end of the power circuit, a voltage source is provided at the output end of the second resistor, and the output end of the voltage source is fixedly connected to the input end of the IBUS+;

[0006] Through the above technical solution, by using a pulse current transformer CT1 and a series of resistors R74, R75, and R76, accurate sampling and feedback of the current of the MOS tube Q1 are achieved, allowing real-time monitoring of the current and precise control through the IN+ and IN- ports of the comparator U3. This optimization of the current sampling and feedback mechanism can improve the stability and efficiency of the circuit and reduce energy loss. By adjusting the drive duty cycle of the MOS tube Q1 to control the output voltage and current, this dynamic adjustment mechanism allows the circuit to adapt to different load conditions and maintain the stability of the output voltage and current. This design not only improves the adaptability of the circuit, but also improves energy efficiency. The current sampling signal of the power circuit is processed and the output of U1 is controlled by the comparator U2, thereby achieving protection and control of the power circuit. This integrated protection mechanism can prevent abnormal conditions such as overcurrent and overvoltage from damaging the circuit, ensuring safe and stable operation of the circuit.

[0007] Furthermore, the Buck circuit includes a MOS transistor Q1, a diode D1 and an inductor L1, and the MOS transistor Q1, the diode D1 and the inductor L1 constitute a basic Buck circuit;

[0008] With the above technical solution, when MOS tube Q1 is turned on, the input voltage VBUS+ is applied to inductor L1, the inductor current rises linearly, and electrical energy is stored in the inductor. At the same time, diode D1 is reverse-blocked. When MOS tube Q1 is turned off, the current in inductor L1 cannot change suddenly. The current flows through diode D1, releasing energy to the load, thereby achieving voltage reduction. By controlling the on-time of Q1, the voltage and current output to IBUS+ can be adjusted.

[0009] Furthermore, the CT1 is a pulse current transformer;

[0010] Through the above technical solution, when current passes through the circuit (connected in series with the primary winding), a current signal proportional to the primary current will be induced in the secondary winding.

[0011] Furthermore, the two first diodes are connected in series;

[0012] Through the above technical solution, the voltage reduction capability of the circuit is increased, which helps to adjust the voltage input to the IN+ port of the comparator.

[0013] Furthermore, the two first resistors and the second resistor are R74, R75 and R76 respectively;

[0014] Through the above technical solution, resistors R74 and R75 form a voltage divider circuit, which divides the signal passing through the first diode to obtain a suitable voltage input to the comparator IN+ port, and the second resistor R76 is used to convert the current sampling signal from the power circuit 7 into a suitable voltage input to the comparator IN- port.

[0015] Further, the voltage source is U1;

[0016] Through the above technical solution, a stable voltage output is provided to meet the operating voltage requirements of various components in the circuit.

[0017] Furthermore, VBUS+ is the input, IBUS+ is the input, and the input and output of all phases are connected in parallel. The basic Buck circuit is formed through the MOS tube Q1, diode D1, and inductor L1. By controlling the drive duty cycle of Q1, the voltage and current of IBUS+ can be controlled. CT1 is a pulse current transformer, which, together with D8, R18, and R19, forms the current sampling circuit of the MOS tube Q1;

[0018] With the above technical solution, VBUS+ serves as the input power source. Buck circuit components work together to achieve step-down conversion. The charge and discharge time of the inductor is controlled by adjusting the on-time duty cycle of MOS tube Q1, thereby changing the voltage and current output to IBUS+. CT1 cooperates with other components to detect the current of MOS tube Q1 in real time.

[0019] Furthermore, taking the circuit composed of U2 and U1 as an example, FB is the output signal from the output error amplifier. After the FB signal passes through the two first diodes connected in series with D31, it is divided by the voltage divider circuit composed of R74 and R75, and a voltage of *30 / 130≈ / 4 is obtained at the IN+ port of the comparator U3. The higher the FB, the higher the voltage of the IN+ port.

[0020] Through the above technical solution, the FB signal generates a voltage drop after passing through the first diode in series, and then is proportionally divided by the voltage divider circuit to obtain a specific voltage related to FB and input to the IN+ port of the comparator. Due to the voltage division ratio, the higher the FB, the higher the voltage of the IN+ port.

[0021] Furthermore, the current sampling signal from the power circuit is input to the IN- port of the comparator through R76. When the voltage of the IN- port is higher than the voltage of the IN+ port, the OUT pin of the comparator U2 generates a low-level pulse. This low-level pulse is applied to the clear port of U1, causing the Q port of U1 to output a low level.

[0022] Through the above technical solution, when the current sampling signal from the power circuit is converted into a voltage through the first resistor R76 and input to the IN- port of the comparator, and the voltage is higher than the voltage of the IN+ port, the OUT pin of the comparator U2 generates a low-level pulse. This pulse acts on the reset port of U1, causing the Q port of U1 to output a low level.

[0023] Furthermore, the signal from PWM1A is applied to the CLK clock pulse input port of U1. Each high-level pulse of PWM1A can make the Q port of U1 output a high level. The signal output from the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1 of the first phase in the power circuit.

[0024] Through the above technical solution, when the high-level pulse of PWM1A is applied to the CLK clock pulse input port of U1, the Q port of U1 outputs a high level. The signal output by the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1 of the first phase in the power circuit.

[0025] The utility model has the following beneficial effects:

[0026] 1. In the present invention, the current mode interleaved parallel Buck control circuit uses a pulse current transformer CT1 and a series of resistors R74, R75, and R76 to achieve accurate sampling and feedback of the current of the MOS tube Q1, allowing real-time monitoring of the current and precise control through the IN+ and IN- ports of the comparator U3. This optimization of the current sampling and feedback mechanism can improve the stability and efficiency of the circuit and reduce energy loss.

[0027] 2. In the present invention, the output voltage and current are controlled by adjusting the driving duty cycle of the MOS tube Q1. This dynamic adjustment mechanism allows the circuit to adapt to different load conditions and maintain the stability of the output voltage and current. This design not only improves the adaptability of the circuit, but also improves energy efficiency.

[0028] 3. In the present invention, the current sampling signal of the power circuit is processed, and the output of U1 is controlled by the comparator U2, thereby realizing protection and control of the power circuit. This integrated protection mechanism can prevent abnormal conditions such as overcurrent and overvoltage from damaging the circuit, ensuring safe and stable operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a circuit diagram of the first power circuit of a current mode interleaved parallel Buck control circuit proposed in the present invention;

[0030] Figure 2 This is a circuit diagram of the second power circuit of a current mode interleaved parallel Buck control circuit proposed in the present invention;

[0031] Figure 3 This is a circuit diagram of the first pulse generating circuit of a current mode interleaved parallel Buck control circuit proposed by the present invention;

[0032] Figure 4 This is a circuit diagram of the second pulse generating circuit of a current mode interleaved parallel Buck control circuit proposed by the present invention;

[0033] Figure 5 This is a timing diagram of the control circuit of a current-mode interleaved parallel Buck proposed in this utility model.

[0034] Legend: 1. VBUS+; 2. Buck circuit; 201. MOS tube Q1; 202. Diode D1; 203. Inductor L1; 3. CT1; 4. First diode; 5. First resistor; 6. Comparator; 7. Power circuit; 8. Second resistor; 9. Voltage source; 10. IBUS+. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0036] Reference Figure 1-4The present invention provides an embodiment of a current mode interleaved parallel Buck control circuit, including VBUS+1 and IBUS+10, VBUS+1 and IBUS+10 are arranged in parallel, a Buck circuit 2 is provided at the output end of VBUS+1, a CT13 is provided at the output end of CT13, two first diodes 4 are provided at the output end of the two first diodes 4, two first resistors 5 are fixedly connected to the output ends of the two first resistors 5, a comparator 6 is provided at the output end of the comparator 6, a power circuit 7 is provided at the output end of the power circuit 7, a second resistor 8 is provided at the output end of the second resistor 8, a voltage source 9 is provided at the output end of the voltage source 9, the output end of the voltage source 9 is fixedly connected to the input end of IBUS+10, and the input VBU S+1 passes through the parallel-connected IBUS+10 and enters Buck circuit 2. In Buck circuit 2, step-down conversion is achieved through the switching action of MOS tube Q1201, the freewheeling of diode D1202, and the energy storage and release of inductor L1203. Pulse current transformer CT13 samples the current of MOS tube Q1201. The sampled current passes through two first diodes 4 and two first resistors 5 connected in series and is input to comparator 6. At the same time, the current sampling signal from power circuit 7 is also input to comparator 6 through second resistor 8. Based on the comparison result of the input signals, comparator 6 controls the on / off switching of the MOS tube in power circuit 7 through D flip-flop U1, thereby adjusting the output voltage and current.

[0037] CT13 is a pulse current transformer. When current flows through its primary winding, which is the circuit connected in series with the MOS tube Q1201, a current signal proportional to the primary current is induced in the secondary winding. The two first diodes 4 are arranged in series, which increases the circuit's voltage-stepping capability and helps adjust the voltage input to the comparator's IN+ port. The two first resistors 5 and the second resistor 8 are R74, R75, and R76, respectively. Resistors R74 and R75 form a voltage divider circuit, which divides the signal passing through the first diode 4 to obtain a suitable voltage input to the comparator's 6IN+ port. The second resistor 8R76 is used to convert the current sampling signal from the power circuit 7 into a suitable voltage input to the comparator's 6IN- port. The voltage source is U1, which provides a stable voltage output to meet the operating voltage requirements of various components in the circuit.

[0038] Buck circuit 2 includes MOS transistor Q1201, diode D1202, and inductor L1203. MOS transistor Q1201, diode D1202, and inductor L1203 form the basic Buck circuit 2. When MOS transistor Q1201 is turned on, the input voltage VBUS+1 is applied to inductor L1203, causing the inductor current to rise linearly and storing energy in the inductor. At the same time, diode D1202 is reverse-blocked. When MOS transistor Q1201 is turned off, the current in inductor L1203 cannot change suddenly. Instead, it continues to flow through diode D1202, releasing energy to the load, thereby achieving voltage reduction. By controlling the on-time of Q1, that is, the drive duty cycle, the voltage and current output to IBUS+1 can be adjusted.

[0039] VBUS+1 is the input, IBUS+10 is the input, and the input and output of all phases are connected in parallel. The basic Buck circuit 2 is formed by MOS tube Q1201, diode D1202, and inductor L1203. By controlling the drive duty cycle of Q1, the voltage and current of IBUS+10 can be controlled. CT13 is a pulse current transformer. It and D8, R18, and R19 form the current sampling circuit of MOS tube Q1201. VBUS+1 is used as the input power supply. Through the coordinated work of Buck circuit 2 components, step-down conversion is achieved. By adjusting the on-time duty cycle of MOS tube Q1201, the charge and discharge time of the inductor is controlled, thereby changing the voltage and current output to IBUS+10. CT13 cooperates with other components to detect the current of MOS tube Q1201 in real time.

[0040] Taking the circuit composed of U2 and U1 as an example, FB is the output signal from the output error amplifier. After the FB signal passes through the two first diodes 4 connected in series with D31, it is divided by the voltage divider circuit composed of R74 and R75. At the IN+ port of the comparator 6U3, a voltage of FB-1.4V*30 / 130≈FB-1.4 / 4 is obtained. The higher the FB, the higher the voltage of the IN+ port. The FB signal generates a voltage drop after passing through the first diode 4 connected in series, and then is divided proportionally by the voltage divider circuit to obtain a specific voltage related to FB and input to the IN+ port of the comparator 6. Due to the voltage divider ratio, the higher the FB, the higher the voltage of the IN+ port.

[0041] The current sampling signal from the power circuit 7 is input to the IN- port of the comparator 6 through R76. When the voltage of the IN- port is higher than the voltage of the IN+ port, the OUT pin of the comparator 6U2 generates a low-level pulse. This low-level pulse is applied to the clear port of the U1D trigger, causing the Q port of U1 to output a low level. When the current sampling signal from the power circuit 7 is converted into a voltage through the first resistor 5R76 and input to the IN- port of the comparator 6, and this voltage is higher than the voltage of the IN+ port, the OUT pin of the comparator 6U2 generates a low-level pulse. This pulse acts on the clear port of the U1D trigger, causing the Q port of U1 to output a low level.

[0042] The signal from PWM1A is applied to the CLK clock pulse input port of U1. Each high-level pulse of PWM1A can make the Q port of U1 output a high level. The signal output from the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1201 of the first phase in the power circuit. When the high-level pulse of PWM1A is applied to the CLK clock pulse input port of U1, the Q port of U1 outputs a high level. The signal output from the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1201 of the first phase in the power circuit.

[0043] Working principle: VBUS+1 is the input, IBUS+10 is the input, and the input and output of all phases are connected in parallel. The basic Buck circuit 2 is formed by the MOS tube Q1201, the diode D1202, and the inductor L1203. By controlling the driving duty cycle of Q1, the voltage and current of IBUS+10 can be controlled. CT13 is a pulse current transformer. It and D8, R18, and R19 form the current sampling circuit of the MOS tube Q1201. Taking the circuit composed of U2 and U1 as an example, FB is the output signal from the output error amplifier. After the FB signal passes through the two series-connected first diodes 4 of D31, it is divided by the voltage divider circuit composed of R74 and R75, and FB-1.4 is obtained at the IN+ port of the comparator 6U3. The voltage of V*30 / 130≈FB-1.4 / 4, the higher the FB, the higher the voltage of the IN+ port. The current sampling signal from the power circuit 7 is input to the IN- port of the comparator 6 through R76. When the IN- port voltage is higher than the IN+ port voltage, the OUT pin of the comparator 6U2 generates a low-level pulse. This low-level pulse is applied to the clear port of the U1D trigger, causing the Q port of U1 to output a low level. The signal from PWM1A is applied to the CLK clock pulse input port of U1. Each high-level pulse of PWM1A can cause the Q port of U1 to output a high level. The signal output from the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1201 of the first phase in the power circuit.

[0044] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A current mode interleaved parallel Buck control circuit, comprising VBUS+ (1) and IBUS+ (10), wherein the VBUS+ (1) and IBUS+ (10) are arranged in parallel, and characterized in that: The VBUS+ (1) output end is provided with a Buck circuit (2), the Buck circuit (2) output end is provided with a CT1 (3), the CT1 (3) output end is provided with two first diodes (4), the two first diodes (4) output ends are fixedly connected to two first resistors (5), the two first resistors (5) output ends are provided with a comparator (6), the comparator (6) output end is provided with a power circuit (7), the power circuit (7) output end is provided with a second resistor (8), the second resistor (8) output end is provided with a voltage source (9), and the output end of the voltage source (9) is fixedly connected to the IBUS+ (10) input end.

2. The current-mode interleaved parallel Buck control circuit according to claim 1, characterized in that: The Buck circuit (2) comprises a MOS transistor Q1 (201), a diode D1 (202) and an inductor L1 (203), wherein the MOS transistor Q1 (201), the diode D1 (202) and the inductor L1 (203) constitute a basic Buck circuit (2).

3. The current-mode interleaved parallel Buck control circuit according to claim 1, characterized in that: The CT1 (3) is a pulse current transformer.

4. The current-mode interleaved parallel Buck control circuit according to claim 1, characterized in that: The two first diodes (4) are arranged in series.

5. The current-mode interleaved parallel Buck control circuit according to claim 1, characterized in that: The two first resistors (5) and the second resistor (8) are R74, R75 and R76 respectively.

6. The current-mode interleaved parallel Buck control circuit according to claim 1, characterized in that: The voltage source is U1; A current-mode interleaved parallel Buck control circuit includes the following steps: S1.VBUS+ (1) is the input, IBUS+ (10) is the input, and the input and output of all phases are connected in parallel. The basic Buck circuit (2) is formed by MOS tube Q1 (201), diode D1 (202), and inductor L1 (203). By controlling the driving duty cycle of Q1, the voltage and current of IBUS+ (10) can be controlled. CT1 (3) is a pulse current transformer. It and D8, R18, and R19 form the current sampling circuit of MOS tube Q1 (201); S2. Take the circuit composed of U2 and U1 as an example. FB is the output signal from the output error amplifier. After the FB signal passes through the two first diodes (4) connected in series with D31, it is divided by the voltage divider circuit composed of R74 and R75. The voltage of (FB-1.4V)*30 / 130≈(FB-1.4) / 4 is obtained at the IN+ port of the comparator (6) U3. The higher the FB, the higher the voltage of the IN+ port. S3. The current sampling signal from the power circuit (7) is input to the IN- port of the comparator (6) through R76. When the voltage of the IN- port is higher than the voltage of the IN+ port, the OUT pin of the comparator (6) U2 generates a low-level pulse. This low-level pulse is applied to the clear port of the D flip-flop in U1, causing the Q port of U1 to output a low level. S4. The signal from PWM1A is applied to the CLK clock pulse input port of U1. Each high-level pulse of PWM1A can make the Q port of U1 output a high level. The signal output from the Q port of U1 passes through the drive circuit to control the opening and closing of the MOS tube Q1 (201) of the first phase in the power circuit.

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